arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2020 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <init.h>
  12 #include <hang.h>
  13 #include <log.h>
  14 #include <net.h>
  15 #include <vsprintf.h>
  16 #include <asm/cache.h>
  17 #include <asm/io.h>
  18 #include <asm/ptrace.h>
  19 #include <linux/errno.h>
  20 #include <asm/system.h>
  21 #include <fm_eth.h>
  22 #include <asm/armv8/mmu.h>
  23 #include <asm/io.h>
  24 #include <asm/arch/fsl_serdes.h>
  25 #include <asm/arch/soc.h>
  26 #include <asm/arch/cpu.h>
  27 #include <asm/arch/speed.h>
  28 #include <fsl_immap.h>
  29 #include <asm/arch/mp.h>
  30 #include <efi_loader.h>
  31 #include <fsl-mc/fsl_mc.h>
  32 #ifdef CONFIG_FSL_ESDHC
  33 #include <fsl_esdhc.h>
  34 #endif
  35 #include <asm/armv8/sec_firmware.h>
  36 #ifdef CONFIG_SYS_FSL_DDR
  37 #include <fsl_ddr.h>
  38 #endif
  39 #include <asm/arch/clock.h>
  40 #include <hwconfig.h>
  41 #include <fsl_qbman.h>
  42
  43 #ifdef CONFIG_TFABOOT
  44 #include <env_internal.h>
  45 #ifdef CONFIG_CHAIN_OF_TRUST
  46 #include <fsl_validate.h>
  47 #endif
  48 #endif
  49 #include <linux/mii.h>
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 static struct cpu_type cpu_type_list[] = {
  54         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  55         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  56         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  57         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  58         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  59         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  60         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  61         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  62         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  63         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  64         CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
  65         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  66         CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
  67         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  68         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  69         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  70         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  71         CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
  72         CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
  73         CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
  74         CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
  75         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  76         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  77         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  78         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  79         CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
  80         CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
  81         CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
  82         CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
  83         CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
  84         CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
  85 };
  86
  87 #define EARLY_PGTABLE_SIZE 0x5000
  88 static struct mm_region early_map[] = {
  89 #ifdef CONFIG_FSL_LSCH3
  90         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  91           CONFIG_SYS_FSL_CCSR_SIZE,
  92           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  93           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  94         },
  95         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  96           SYS_FSL_OCRAM_SPACE_SIZE,
  97           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  98         },
  99         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 100           CONFIG_SYS_FSL_QSPI_SIZE1,
 101           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
 102 #ifdef CONFIG_FSL_IFC
 103         /* For IFC Region #1, only the first 4MB is cache-enabled */
 104         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
 105           CONFIG_SYS_FSL_IFC_SIZE1_1,
 106           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 107         },
 108         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 109           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 110           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 111           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 112         },
 113         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 114           CONFIG_SYS_FSL_IFC_SIZE1,
 115           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 116         },
 117 #endif
 118         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 119           CONFIG_SYS_FSL_DRAM_SIZE1,
 120 #if defined(CONFIG_TFABOOT) || \
 121         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 122           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 123 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 124           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 125 #endif
 126           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 127         },
 128 #ifdef CONFIG_FSL_IFC
 129         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 130         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 131           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 132           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 133         },
 134 #endif
 135         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 136           CONFIG_SYS_FSL_DCSR_SIZE,
 137           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 138           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 139         },
 140         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 141           CONFIG_SYS_FSL_DRAM_SIZE2,
 142           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 143           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 144         },
 145 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 146         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 147           CONFIG_SYS_FSL_DRAM_SIZE3,
 148           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 149           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 150         },
 151 #endif
 152 #elif defined(CONFIG_FSL_LSCH2)
 153         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 154           CONFIG_SYS_FSL_CCSR_SIZE,
 155           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 156           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 157         },
 158         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 159           SYS_FSL_OCRAM_SPACE_SIZE,
 160           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 161         },
 162         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 163           CONFIG_SYS_FSL_DCSR_SIZE,
 164           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 165           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 166         },
 167         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 168           CONFIG_SYS_FSL_QSPI_SIZE,
 169           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 170         },
 171 #ifdef CONFIG_FSL_IFC
 172         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 173           CONFIG_SYS_FSL_IFC_SIZE,
 174           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 175         },
 176 #endif
 177         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 178           CONFIG_SYS_FSL_DRAM_SIZE1,
 179 #if defined(CONFIG_TFABOOT) || \
 180         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 181           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 182 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 183           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 184 #endif
 185           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 186         },
 187         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 188           CONFIG_SYS_FSL_DRAM_SIZE2,
 189           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 190           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 191         },
 192 #endif
 193         {},     /* list terminator */
 194 };
 195
 196 static struct mm_region final_map[] = {
 197 #ifdef CONFIG_FSL_LSCH3
 198         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 199           CONFIG_SYS_FSL_CCSR_SIZE,
 200           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 201           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 202         },
 203         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 204           SYS_FSL_OCRAM_SPACE_SIZE,
 205           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 206         },
 207         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 208           CONFIG_SYS_FSL_DRAM_SIZE1,
 209           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 210           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 211         },
 212         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 213           CONFIG_SYS_FSL_QSPI_SIZE1,
 214           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 215           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 216         },
 217         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 218           CONFIG_SYS_FSL_QSPI_SIZE2,
 219           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 220           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 221         },
 222 #ifdef CONFIG_FSL_IFC
 223         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 224           CONFIG_SYS_FSL_IFC_SIZE2,
 225           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 226           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 227         },
 228 #endif
 229         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 230           CONFIG_SYS_FSL_DCSR_SIZE,
 231           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 232           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 233         },
 234         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 235           CONFIG_SYS_FSL_MC_SIZE,
 236           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 237           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 238         },
 239         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 240           CONFIG_SYS_FSL_NI_SIZE,
 241           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 242           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 243         },
 244         /* For QBMAN portal, only the first 64MB is cache-enabled */
 245         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 246           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 247           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 248           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 249         },
 250         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 251           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 252           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 253           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 254           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 255         },
 256         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 257           CONFIG_SYS_PCIE1_PHYS_SIZE,
 258           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 259           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 260         },
 261         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 262           CONFIG_SYS_PCIE2_PHYS_SIZE,
 263           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 264           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 265         },
 266 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 267         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 268           CONFIG_SYS_PCIE3_PHYS_SIZE,
 269           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 270           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 271         },
 272 #endif
 273 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 274         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 275           CONFIG_SYS_PCIE4_PHYS_SIZE,
 276           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 277           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 278         },
 279 #endif
 280 #ifdef SYS_PCIE5_PHYS_ADDR
 281         { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
 282           SYS_PCIE5_PHYS_SIZE,
 283           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 284           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 285         },
 286 #endif
 287 #ifdef SYS_PCIE6_PHYS_ADDR
 288         { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
 289           SYS_PCIE6_PHYS_SIZE,
 290           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 291           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 292         },
 293 #endif
 294         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 295           CONFIG_SYS_FSL_WRIOP1_SIZE,
 296           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 297           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 298         },
 299         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 300           CONFIG_SYS_FSL_AIOP1_SIZE,
 301           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 302           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 303         },
 304         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 305           CONFIG_SYS_FSL_PEBUF_SIZE,
 306           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 307           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 308         },
 309         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 310           CONFIG_SYS_FSL_DRAM_SIZE2,
 311           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 312           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 313         },
 314 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 315         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 316           CONFIG_SYS_FSL_DRAM_SIZE3,
 317           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 318           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 319         },
 320 #endif
 321 #elif defined(CONFIG_FSL_LSCH2)
 322         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 323           CONFIG_SYS_FSL_BOOTROM_SIZE,
 324           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 325           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 326         },
 327         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 328           CONFIG_SYS_FSL_CCSR_SIZE,
 329           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 330           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 331         },
 332         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 333           SYS_FSL_OCRAM_SPACE_SIZE,
 334           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 335         },
 336         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 337           CONFIG_SYS_FSL_DCSR_SIZE,
 338           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 339           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 340         },
 341         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 342           CONFIG_SYS_FSL_QSPI_SIZE,
 343           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 344           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 345         },
 346 #ifdef CONFIG_FSL_IFC
 347         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 348           CONFIG_SYS_FSL_IFC_SIZE,
 349           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 350         },
 351 #endif
 352         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 353           CONFIG_SYS_FSL_DRAM_SIZE1,
 354           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 355           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 356         },
 357         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 358           CONFIG_SYS_FSL_QBMAN_SIZE,
 359           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 360           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 361         },
 362         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 363           CONFIG_SYS_FSL_DRAM_SIZE2,
 364           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 365           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 366         },
 367         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 368           CONFIG_SYS_PCIE1_PHYS_SIZE,
 369           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 370           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 371         },
 372         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 373           CONFIG_SYS_PCIE2_PHYS_SIZE,
 374           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 375           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 376         },
 377 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 378         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 379           CONFIG_SYS_PCIE3_PHYS_SIZE,
 380           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 381           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 382         },
 383 #endif
 384         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 385           CONFIG_SYS_FSL_DRAM_SIZE3,
 386           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 387           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 388         },
 389 #endif
 390 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 391         {},     /* space holder for secure mem */
 392 #endif
 393         {},
 394 };
 395
 396 struct mm_region *mem_map = early_map;
 397
 398 void cpu_name(char *name)
 399 {
 400         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 401         unsigned int i, svr, ver;
 402
 403         svr = gur_in32(&gur->svr);
 404         ver = SVR_SOC_VER(svr);
 405
 406         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 407                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 408                         strcpy(name, cpu_type_list[i].name);
 409 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 410                         if (IS_C_PROCESSOR(svr))
 411                                 strcat(name, "C");
 412 #endif
 413
 414                         if (IS_E_PROCESSOR(svr))
 415                                 strcat(name, "E");
 416
 417                         sprintf(name + strlen(name), " Rev%d.%d",
 418                                 SVR_MAJ(svr), SVR_MIN(svr));
 419                         break;
 420                 }
 421
 422         if (i == ARRAY_SIZE(cpu_type_list))
 423                 strcpy(name, "unknown");
 424 }
 425
 426 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 427 /*
 428  * To start MMU before DDR is available, we create MMU table in SRAM.
 429  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 430  * levels of translation tables here to cover 40-bit address space.
 431  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 432  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 433  * Note, the debug print in cache_v8.c is not usable for debugging
 434  * these early MMU tables because UART is not yet available.
 435  */
 436 static inline void early_mmu_setup(void)
 437 {
 438         unsigned int el = current_el();
 439
 440         /* global data is already setup, no allocation yet */
 441         if (el == 3)
 442                 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 443         else
 444                 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 445         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 446         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 447
 448         /* Create early page tables */
 449         setup_pgtables();
 450
 451         /* point TTBR to the new table */
 452         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 453                           get_tcr(el, NULL, NULL) &
 454                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 455                           MEMORY_ATTRIBUTES);
 456
 457         set_sctlr(get_sctlr() | CR_M);
 458 }
 459
 460 static void fix_pcie_mmu_map(void)
 461 {
 462 #ifdef CONFIG_ARCH_LS2080A
 463         unsigned int i;
 464         u32 svr, ver;
 465         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 466
 467         svr = gur_in32(&gur->svr);
 468         ver = SVR_SOC_VER(svr);
 469
 470         /* Fix PCIE base and size for LS2088A */
 471         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 472             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 473             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 474                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 475                         switch (final_map[i].phys) {
 476                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 477                                 final_map[i].phys = 0x2000000000ULL;
 478                                 final_map[i].virt = 0x2000000000ULL;
 479                                 final_map[i].size = 0x800000000ULL;
 480                                 break;
 481                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 482                                 final_map[i].phys = 0x2800000000ULL;
 483                                 final_map[i].virt = 0x2800000000ULL;
 484                                 final_map[i].size = 0x800000000ULL;
 485                                 break;
 486 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 487                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 488                                 final_map[i].phys = 0x3000000000ULL;
 489                                 final_map[i].virt = 0x3000000000ULL;
 490                                 final_map[i].size = 0x800000000ULL;
 491                                 break;
 492 #endif
 493 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 494                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 495                                 final_map[i].phys = 0x3800000000ULL;
 496                                 final_map[i].virt = 0x3800000000ULL;
 497                                 final_map[i].size = 0x800000000ULL;
 498                                 break;
 499 #endif
 500                         default:
 501                                 break;
 502                         }
 503                 }
 504         }
 505 #endif
 506 }
 507
 508 /*
 509  * The final tables look similar to early tables, but different in detail.
 510  * These tables are in DRAM. Sub tables are added to enable cache for
 511  * QBMan and OCRAM.
 512  *
 513  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 514  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 515  */
 516 static inline void final_mmu_setup(void)
 517 {
 518         u64 tlb_addr_save = gd->arch.tlb_addr;
 519         unsigned int el = current_el();
 520         int index;
 521
 522         /* fix the final_map before filling in the block entries */
 523         fix_pcie_mmu_map();
 524
 525         mem_map = final_map;
 526
 527         /* Update mapping for DDR to actual size */
 528         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 529                 /*
 530                  * Find the entry for DDR mapping and update the address and
 531                  * size. Zero-sized mapping will be skipped when creating MMU
 532                  * table.
 533                  */
 534                 switch (final_map[index].virt) {
 535                 case CONFIG_SYS_FSL_DRAM_BASE1:
 536                         final_map[index].virt = gd->bd->bi_dram[0].start;
 537                         final_map[index].phys = gd->bd->bi_dram[0].start;
 538                         final_map[index].size = gd->bd->bi_dram[0].size;
 539                         break;
 540 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 541                 case CONFIG_SYS_FSL_DRAM_BASE2:
 542 #if (CONFIG_NR_DRAM_BANKS >= 2)
 543                         final_map[index].virt = gd->bd->bi_dram[1].start;
 544                         final_map[index].phys = gd->bd->bi_dram[1].start;
 545                         final_map[index].size = gd->bd->bi_dram[1].size;
 546 #else
 547                         final_map[index].size = 0;
 548 #endif
 549                 break;
 550 #endif
 551 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 552                 case CONFIG_SYS_FSL_DRAM_BASE3:
 553 #if (CONFIG_NR_DRAM_BANKS >= 3)
 554                         final_map[index].virt = gd->bd->bi_dram[2].start;
 555                         final_map[index].phys = gd->bd->bi_dram[2].start;
 556                         final_map[index].size = gd->bd->bi_dram[2].size;
 557 #else
 558                         final_map[index].size = 0;
 559 #endif
 560                 break;
 561 #endif
 562                 default:
 563                         break;
 564                 }
 565         }
 566
 567 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 568         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 569                 if (el == 3) {
 570                         /*
 571                          * Only use gd->arch.secure_ram if the address is
 572                          * recalculated. Align to 4KB for MMU table.
 573                          */
 574                         /* put page tables in secure ram */
 575                         index = ARRAY_SIZE(final_map) - 2;
 576                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 577                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 578                         final_map[index].phys = final_map[index].virt;
 579                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 580                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 581                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 582                         tlb_addr_save = gd->arch.tlb_addr;
 583                 } else {
 584                         /* Use allocated (board_f.c) memory for TLB */
 585                         tlb_addr_save = gd->arch.tlb_allocated;
 586                         gd->arch.tlb_addr = tlb_addr_save;
 587                 }
 588         }
 589 #endif
 590
 591         /* Reset the fill ptr */
 592         gd->arch.tlb_fillptr = tlb_addr_save;
 593
 594         /* Create normal system page tables */
 595         setup_pgtables();
 596
 597         /* Create emergency page tables */
 598         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 599         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 600         setup_pgtables();
 601         gd->arch.tlb_addr = tlb_addr_save;
 602
 603         /* Disable cache and MMU */
 604         dcache_disable();       /* TLBs are invalidated */
 605         invalidate_icache_all();
 606
 607         /* point TTBR to the new table */
 608         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 609                           MEMORY_ATTRIBUTES);
 610
 611         set_sctlr(get_sctlr() | CR_M);
 612 }
 613
 614 u64 get_page_table_size(void)
 615 {
 616         return 0x10000;
 617 }
 618
 619 int arch_cpu_init(void)
 620 {
 621         /*
 622          * This function is called before U-Boot relocates itself to speed up
 623          * on system running. It is not necessary to run if performance is not
 624          * critical. Skip if MMU is already enabled by SPL or other means.
 625          */
 626         if (get_sctlr() & CR_M)
 627                 return 0;
 628
 629         icache_enable();
 630         __asm_invalidate_dcache_all();
 631         __asm_invalidate_tlb_all();
 632         early_mmu_setup();
 633         set_sctlr(get_sctlr() | CR_C);
 634         return 0;
 635 }
 636
 637 void mmu_setup(void)
 638 {
 639         final_mmu_setup();
 640 }
 641
 642 /*
 643  * This function is called from common/board_r.c.
 644  * It recreates MMU table in main memory.
 645  */
 646 void enable_caches(void)
 647 {
 648         mmu_setup();
 649         __asm_invalidate_tlb_all();
 650         icache_enable();
 651         dcache_enable();
 652 }
 653 #endif  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 654
 655 #ifdef CONFIG_TFABOOT
 656 enum boot_src __get_boot_src(u32 porsr1)
 657 {
 658         enum boot_src src = BOOT_SOURCE_RESERVED;
 659         u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
 660 #if !defined(CONFIG_NXP_LSCH3_2)
 661         u32 val;
 662 #endif
 663         debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
 664
 665 #if defined(CONFIG_FSL_LSCH3)
 666 #if defined(CONFIG_NXP_LSCH3_2)
 667         switch (rcw_src) {
 668         case RCW_SRC_SDHC1_VAL:
 669                 src = BOOT_SOURCE_SD_MMC;
 670         break;
 671         case RCW_SRC_SDHC2_VAL:
 672                 src = BOOT_SOURCE_SD_MMC2;
 673         break;
 674         case RCW_SRC_I2C1_VAL:
 675                 src = BOOT_SOURCE_I2C1_EXTENDED;
 676         break;
 677         case RCW_SRC_FLEXSPI_NAND2K_VAL:
 678                 src = BOOT_SOURCE_XSPI_NAND;
 679         break;
 680         case RCW_SRC_FLEXSPI_NAND4K_VAL:
 681                 src = BOOT_SOURCE_XSPI_NAND;
 682         break;
 683         case RCW_SRC_RESERVED_1_VAL:
 684                 src = BOOT_SOURCE_RESERVED;
 685         break;
 686         case RCW_SRC_FLEXSPI_NOR_24B:
 687                 src = BOOT_SOURCE_XSPI_NOR;
 688         break;
 689         default:
 690                 src = BOOT_SOURCE_RESERVED;
 691         }
 692 #else
 693         val = rcw_src & RCW_SRC_TYPE_MASK;
 694         if (val == RCW_SRC_NOR_VAL) {
 695                 val = rcw_src & NOR_TYPE_MASK;
 696
 697                 switch (val) {
 698                 case NOR_16B_VAL:
 699                 case NOR_32B_VAL:
 700                         src = BOOT_SOURCE_IFC_NOR;
 701                 break;
 702                 default:
 703                         src = BOOT_SOURCE_RESERVED;
 704                 }
 705         } else {
 706                 /* RCW SRC Serial Flash */
 707                 val = rcw_src & RCW_SRC_SERIAL_MASK;
 708                 switch (val) {
 709                 case RCW_SRC_QSPI_VAL:
 710                 /* RCW SRC Serial NOR (QSPI) */
 711                         src = BOOT_SOURCE_QSPI_NOR;
 712                         break;
 713                 case RCW_SRC_SD_CARD_VAL:
 714                 /* RCW SRC SD Card */
 715                         src = BOOT_SOURCE_SD_MMC;
 716                         break;
 717                 case RCW_SRC_EMMC_VAL:
 718                 /* RCW SRC EMMC */
 719                         src = BOOT_SOURCE_SD_MMC;
 720                         break;
 721                 case RCW_SRC_I2C1_VAL:
 722                 /* RCW SRC I2C1 Extended */
 723                         src = BOOT_SOURCE_I2C1_EXTENDED;
 724                         break;
 725                 default:
 726                         src = BOOT_SOURCE_RESERVED;
 727                 }
 728         }
 729 #endif
 730 #elif defined(CONFIG_FSL_LSCH2)
 731         /* RCW SRC NAND */
 732         val = rcw_src & RCW_SRC_NAND_MASK;
 733         if (val == RCW_SRC_NAND_VAL) {
 734                 val = rcw_src & NAND_RESERVED_MASK;
 735                 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
 736                         src = BOOT_SOURCE_IFC_NAND;
 737
 738         } else {
 739                 /* RCW SRC NOR */
 740                 val = rcw_src & RCW_SRC_NOR_MASK;
 741                 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
 742                         src = BOOT_SOURCE_IFC_NOR;
 743                 } else {
 744                         switch (rcw_src) {
 745                         case QSPI_VAL1:
 746                         case QSPI_VAL2:
 747                                 src = BOOT_SOURCE_QSPI_NOR;
 748                                 break;
 749                         case SD_VAL:
 750                                 src = BOOT_SOURCE_SD_MMC;
 751                                 break;
 752                         default:
 753                                 src = BOOT_SOURCE_RESERVED;
 754                         }
 755                 }
 756         }
 757 #endif
 758
 759         if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
 760                 src = BOOT_SOURCE_QSPI_NOR;
 761
 762         debug("%s: src 0x%x\n", __func__, src);
 763         return src;
 764 }
 765
 766 enum boot_src get_boot_src(void)
 767 {
 768         struct pt_regs regs;
 769         u32 porsr1 = 0;
 770
 771 #if defined(CONFIG_FSL_LSCH3)
 772         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 773 #elif defined(CONFIG_FSL_LSCH2)
 774         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 775 #endif
 776
 777         if (current_el() == 2) {
 778                 regs.regs[0] = SIP_SVC_RCW;
 779
 780                 smc_call(&regs);
 781                 if (!regs.regs[0])
 782                         porsr1 = regs.regs[1];
 783         }
 784
 785         if (current_el() == 3 || !porsr1) {
 786 #ifdef CONFIG_FSL_LSCH3
 787                 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 788 #elif defined(CONFIG_FSL_LSCH2)
 789                 porsr1 = in_be32(&gur->porsr1);
 790 #endif
 791         }
 792
 793         debug("%s: porsr1 0x%x\n", __func__, porsr1);
 794
 795         return __get_boot_src(porsr1);
 796 }
 797
 798 #ifdef CONFIG_ENV_IS_IN_MMC
 799 int mmc_get_env_dev(void)
 800 {
 801         enum boot_src src = get_boot_src();
 802         int dev = CONFIG_SYS_MMC_ENV_DEV;
 803
 804         switch (src) {
 805         case BOOT_SOURCE_SD_MMC:
 806                 dev = 0;
 807                 break;
 808         case BOOT_SOURCE_SD_MMC2:
 809                 dev = 1;
 810                 break;
 811         default:
 812                 break;
 813         }
 814
 815         return dev;
 816 }
 817 #endif
 818
 819 enum env_location env_get_location(enum env_operation op, int prio)
 820 {
 821         enum boot_src src = get_boot_src();
 822         enum env_location env_loc = ENVL_NOWHERE;
 823
 824         if (prio)
 825                 return ENVL_UNKNOWN;
 826
 827 #ifdef  CONFIG_ENV_IS_NOWHERE
 828         return env_loc;
 829 #endif
 830
 831         switch (src) {
 832         case BOOT_SOURCE_IFC_NOR:
 833                 env_loc = ENVL_FLASH;
 834                 break;
 835         case BOOT_SOURCE_QSPI_NOR:
 836                 /* FALLTHROUGH */
 837         case BOOT_SOURCE_XSPI_NOR:
 838                 env_loc = ENVL_SPI_FLASH;
 839                 break;
 840         case BOOT_SOURCE_IFC_NAND:
 841                 /* FALLTHROUGH */
 842         case BOOT_SOURCE_QSPI_NAND:
 843                 /* FALLTHROUGH */
 844         case BOOT_SOURCE_XSPI_NAND:
 845                 env_loc = ENVL_NAND;
 846                 break;
 847         case BOOT_SOURCE_SD_MMC:
 848                 /* FALLTHROUGH */
 849         case BOOT_SOURCE_SD_MMC2:
 850                 env_loc =  ENVL_MMC;
 851                 break;
 852         case BOOT_SOURCE_I2C1_EXTENDED:
 853                 /* FALLTHROUGH */
 854         default:
 855                 break;
 856         }
 857
 858         return env_loc;
 859 }
 860 #endif  /* CONFIG_TFABOOT */
 861
 862 u32 initiator_type(u32 cluster, int init_id)
 863 {
 864         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 865         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 866         u32 type = 0;
 867
 868         type = gur_in32(&gur->tp_ityp[idx]);
 869         if (type & TP_ITYP_AV)
 870                 return type;
 871
 872         return 0;
 873 }
 874
 875 u32 cpu_pos_mask(void)
 876 {
 877         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 878         int i = 0;
 879         u32 cluster, type, mask = 0;
 880
 881         do {
 882                 int j;
 883
 884                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 885                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 886                         type = initiator_type(cluster, j);
 887                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 888                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 889                 }
 890                 i++;
 891         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 892
 893         return mask;
 894 }
 895
 896 u32 cpu_mask(void)
 897 {
 898         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 899         int i = 0, count = 0;
 900         u32 cluster, type, mask = 0;
 901
 902         do {
 903                 int j;
 904
 905                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 906                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 907                         type = initiator_type(cluster, j);
 908                         if (type) {
 909                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 910                                         mask |= 1 << count;
 911                                 count++;
 912                         }
 913                 }
 914                 i++;
 915         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 916
 917         return mask;
 918 }
 919
 920 /*
 921  * Return the number of cores on this SOC.
 922  */
 923 int cpu_numcores(void)
 924 {
 925         return hweight32(cpu_mask());
 926 }
 927
 928 int fsl_qoriq_core_to_cluster(unsigned int core)
 929 {
 930         struct ccsr_gur __iomem *gur =
 931                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 932         int i = 0, count = 0;
 933         u32 cluster;
 934
 935         do {
 936                 int j;
 937
 938                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 939                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 940                         if (initiator_type(cluster, j)) {
 941                                 if (count == core)
 942                                         return i;
 943                                 count++;
 944                         }
 945                 }
 946                 i++;
 947         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 948
 949         return -1;      /* cannot identify the cluster */
 950 }
 951
 952 u32 fsl_qoriq_core_to_type(unsigned int core)
 953 {
 954         struct ccsr_gur __iomem *gur =
 955                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 956         int i = 0, count = 0;
 957         u32 cluster, type;
 958
 959         do {
 960                 int j;
 961
 962                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 963                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 964                         type = initiator_type(cluster, j);
 965                         if (type) {
 966                                 if (count == core)
 967                                         return type;
 968                                 count++;
 969                         }
 970                 }
 971                 i++;
 972         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 973
 974         return -1;      /* cannot identify the cluster */
 975 }
 976
 977 #ifndef CONFIG_FSL_LSCH3
 978 uint get_svr(void)
 979 {
 980         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 981
 982         return gur_in32(&gur->svr);
 983 }
 984 #endif
 985
 986 #ifdef CONFIG_DISPLAY_CPUINFO
 987 int print_cpuinfo(void)
 988 {
 989         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 990         struct sys_info sysinfo;
 991         char buf[32];
 992         unsigned int i, core;
 993         u32 type, rcw, svr = gur_in32(&gur->svr);
 994
 995         puts("SoC: ");
 996
 997         cpu_name(buf);
 998         printf(" %s (0x%x)\n", buf, svr);
 999         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
1000         get_sys_info(&sysinfo);
1001         puts("Clock Configuration:");
1002         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
1003                 if (!(i % 3))
1004                         puts("\n       ");
1005                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
1006                 printf("CPU%d(%s):%-4s MHz  ", core,
1007                        type == TY_ITYP_VER_A7 ? "A7 " :
1008                        (type == TY_ITYP_VER_A53 ? "A53" :
1009                        (type == TY_ITYP_VER_A57 ? "A57" :
1010                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
1011                        strmhz(buf, sysinfo.freq_processor[core]));
1012         }
1013         /* Display platform clock as Bus frequency. */
1014         printf("\n       Bus:      %-4s MHz  ",
1015                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1016         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1017 #ifdef CONFIG_SYS_DPAA_FMAN
1018         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1019 #endif
1020 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1021         if (soc_has_dp_ddr()) {
1022                 printf("     DP-DDR:   %-4s MT/s",
1023                        strmhz(buf, sysinfo.freq_ddrbus2));
1024         }
1025 #endif
1026         puts("\n");
1027
1028         /*
1029          * Display the RCW, so that no one gets confused as to what RCW
1030          * we're actually using for this boot.
1031          */
1032         puts("Reset Configuration Word (RCW):");
1033         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1034                 rcw = gur_in32(&gur->rcwsr[i]);
1035                 if ((i % 4) == 0)
1036                         printf("\n       %08x:", i * 4);
1037                 printf(" %08x", rcw);
1038         }
1039         puts("\n");
1040
1041         return 0;
1042 }
1043 #endif
1044
1045 #ifdef CONFIG_FSL_ESDHC
1046 int cpu_mmc_init(struct bd_info *bis)
1047 {
1048         return fsl_esdhc_mmc_init(bis);
1049 }
1050 #endif
1051
1052 int cpu_eth_init(struct bd_info *bis)
1053 {
1054         int error = 0;
1055
1056 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1057         error = fsl_mc_ldpaa_init(bis);
1058 #endif
1059 #ifdef CONFIG_FMAN_ENET
1060         fm_standard_init(bis);
1061 #endif
1062         return error;
1063 }
1064
1065 static inline int check_psci(void)
1066 {
1067         unsigned int psci_ver;
1068
1069         psci_ver = sec_firmware_support_psci_version();
1070         if (psci_ver == PSCI_INVALID_VER)
1071                 return 1;
1072
1073         return 0;
1074 }
1075
1076 static void config_core_prefetch(void)
1077 {
1078         char *buf = NULL;
1079         char buffer[HWCONFIG_BUFFER_SIZE];
1080         const char *prefetch_arg = NULL;
1081         size_t arglen;
1082         unsigned int mask;
1083         struct pt_regs regs;
1084
1085         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1086                 buf = buffer;
1087         else
1088                 return;
1089
1090         prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1091                                          &arglen, buf);
1092
1093         if (prefetch_arg) {
1094                 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1095                 if (mask & 0x1) {
1096                         printf("Core0 prefetch can't be disabled\n");
1097                         return;
1098                 }
1099
1100 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1101                 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1102                 regs.regs[1] = mask;
1103                 smc_call(&regs);
1104
1105                 if (regs.regs[0])
1106                         printf("Prefetch disable config failed for mask ");
1107                 else
1108                         printf("Prefetch disable config passed for mask ");
1109                 printf("0x%x\n", mask);
1110         }
1111 }
1112
1113 #ifdef CONFIG_PCIE_ECAM_GENERIC
1114 __weak void set_ecam_icids(void)
1115 {
1116 }
1117 #endif
1118
1119 int arch_early_init_r(void)
1120 {
1121 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1122         u32 svr_dev_id;
1123         /*
1124          * erratum A009635 is valid only for LS2080A SoC and
1125          * its personalitiesi
1126          */
1127         svr_dev_id = get_svr();
1128         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1129                 erratum_a009635();
1130 #endif
1131 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1132         erratum_a009942_check_cpo();
1133 #endif
1134         if (check_psci()) {
1135                 debug("PSCI: PSCI does not exist.\n");
1136
1137                 /* if PSCI does not exist, boot secondary cores here */
1138                 if (fsl_layerscape_wake_seconday_cores())
1139                         printf("Did not wake secondary cores\n");
1140         }
1141
1142         config_core_prefetch();
1143
1144 #ifdef CONFIG_SYS_HAS_SERDES
1145         fsl_serdes_init();
1146 #endif
1147 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1148         /* some dpmacs in armv8a based freescale layerscape SOCs can be
1149          * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1150          * EC*_PMUX(rgmii) bits in RCW.
1151          * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1152          * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1153          * Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes
1154          * precedence over SerDes protocol. i.e. in LX2160A if we select serdes
1155          * protocol that configures dpmac17 as SGMII and set the EC1_PMUX as
1156          * RGMII, then the dpmac is RGMII and not SGMII.
1157          *
1158          * Therefore, even thought fsl_rgmii_init is after fsl_serdes_init
1159          * function of SOC, the dpmac will be enabled as RGMII even if it was
1160          * also enabled before as SGMII. If ECx_PMUX is not configured for
1161          * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
1162          */
1163         fsl_rgmii_init();
1164 #endif
1165 #ifdef CONFIG_FMAN_ENET
1166 #ifndef CONFIG_DM_ETH
1167         fman_enet_init();
1168 #endif
1169 #endif
1170 #ifdef CONFIG_SYS_DPAA_QBMAN
1171         setup_qbman_portals();
1172 #endif
1173 #ifdef CONFIG_PCIE_ECAM_GENERIC
1174         set_ecam_icids();
1175 #endif
1176         return 0;
1177 }
1178
1179 int timer_init(void)
1180 {
1181         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1182 #ifdef CONFIG_FSL_LSCH3
1183         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1184 #endif
1185 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1186         defined(CONFIG_ARCH_LS1028A)
1187         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1188         u32 svr_dev_id;
1189 #endif
1190 #ifdef COUNTER_FREQUENCY_REAL
1191         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1192
1193         /* Update with accurate clock frequency */
1194         if (current_el() == 3)
1195                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1196 #endif
1197
1198 #ifdef CONFIG_FSL_LSCH3
1199         /* Enable timebase for all clusters.
1200          * It is safe to do so even some clusters are not enabled.
1201          */
1202         out_le32(cltbenr, 0xf);
1203 #endif
1204
1205 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1206         defined(CONFIG_ARCH_LS1028A)
1207         /*
1208          * In certain Layerscape SoCs, the clock for each core's
1209          * has an enable bit in the PMU Physical Core Time Base Enable
1210          * Register (PCTBENR), which allows the watchdog to operate.
1211          */
1212         setbits_le32(pctbenr, 0xff);
1213         /*
1214          * For LS2080A SoC and its personalities, timer controller
1215          * offset is different
1216          */
1217         svr_dev_id = get_svr();
1218         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1219                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1220
1221 #endif
1222
1223         /* Enable clock for timer
1224          * This is a global setting.
1225          */
1226         out_le32(cntcr, 0x1);
1227
1228         return 0;
1229 }
1230
1231 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1232
1233 void __efi_runtime reset_cpu(ulong addr)
1234 {
1235 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
1236         /* clear the RST_REQ_MSK and SW_RST_REQ */
1237         out_le32(rstcr, 0x0);
1238
1239         /* initiate the sw reset request */
1240         out_le32(rstcr, 0x1);
1241 #else
1242         u32 val;
1243
1244         /* Raise RESET_REQ_B */
1245         val = scfg_in32(rstcr);
1246         val |= 0x02;
1247         scfg_out32(rstcr, val);
1248 #endif
1249 }
1250
1251 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1252
1253 void __efi_runtime EFIAPI efi_reset_system(
1254                        enum efi_reset_type reset_type,
1255                        efi_status_t reset_status,
1256                        unsigned long data_size, void *reset_data)
1257 {
1258         switch (reset_type) {
1259         case EFI_RESET_COLD:
1260         case EFI_RESET_WARM:
1261         case EFI_RESET_PLATFORM_SPECIFIC:
1262                 reset_cpu(0);
1263                 break;
1264         case EFI_RESET_SHUTDOWN:
1265                 /* Nothing we can do */
1266                 break;
1267         }
1268
1269         while (1) { }
1270 }
1271
1272 efi_status_t efi_reset_system_init(void)
1273 {
1274         return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1275 }
1276
1277 #endif
1278
1279 /*
1280  * Calculate reserved memory with given memory bank
1281  * Return aligned memory size on success
1282  * Return (ram_size + needed size) for failure
1283  */
1284 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1285 {
1286         phys_size_t ram_top = ram_size;
1287
1288 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1289         ram_top = mc_get_dram_block_size();
1290         if (ram_top > ram_size)
1291                 return ram_size + ram_top;
1292
1293         ram_top = ram_size - ram_top;
1294         /* The start address of MC reserved memory needs to be aligned. */
1295         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1296 #endif
1297
1298         return ram_size - ram_top;
1299 }
1300
1301 phys_size_t get_effective_memsize(void)
1302 {
1303         phys_size_t ea_size, rem = 0;
1304
1305         /*
1306          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1307          * first region is 2GB space at 0x8000_0000. Secure memory needs to
1308          * allocated from first region. If the memory extends to  the second
1309          * region (or the third region if applicable), Management Complex (MC)
1310          * memory should be put into the highest region, i.e. the end of DDR
1311          * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1312          * U-Boot doesn't relocate itself into higher address. Should DDR be
1313          * configured to skip the first region, this function needs to be
1314          * adjusted.
1315          */
1316         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1317                 ea_size = CONFIG_MAX_MEM_MAPPED;
1318                 rem = gd->ram_size - ea_size;
1319         } else {
1320                 ea_size = gd->ram_size;
1321         }
1322
1323 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1324         /* Check if we have enough space for secure memory */
1325         if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1326                 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1327         else
1328                 printf("Error: No enough space for secure memory.\n");
1329 #endif
1330         /* Check if we have enough memory for MC */
1331         if (rem < board_reserve_ram_top(rem)) {
1332                 /* Not enough memory in high region to reserve */
1333                 if (ea_size > board_reserve_ram_top(ea_size))
1334                         ea_size -= board_reserve_ram_top(ea_size);
1335                 else
1336                         printf("Error: No enough space for reserved memory.\n");
1337         }
1338
1339         return ea_size;
1340 }
1341
1342 #ifdef CONFIG_TFABOOT
1343 phys_size_t tfa_get_dram_size(void)
1344 {
1345         struct pt_regs regs;
1346         phys_size_t dram_size = 0;
1347
1348         regs.regs[0] = SMC_DRAM_BANK_INFO;
1349         regs.regs[1] = -1;
1350
1351         smc_call(&regs);
1352         if (regs.regs[0])
1353                 return 0;
1354
1355         dram_size = regs.regs[1];
1356         return dram_size;
1357 }
1358
1359 static int tfa_dram_init_banksize(void)
1360 {
1361         int i = 0, ret = 0;
1362         struct pt_regs regs;
1363         phys_size_t dram_size = tfa_get_dram_size();
1364
1365         debug("dram_size %llx\n", dram_size);
1366
1367         if (!dram_size)
1368                 return -EINVAL;
1369
1370         do {
1371                 regs.regs[0] = SMC_DRAM_BANK_INFO;
1372                 regs.regs[1] = i;
1373
1374                 smc_call(&regs);
1375                 if (regs.regs[0]) {
1376                         ret = -EINVAL;
1377                         break;
1378                 }
1379
1380                 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1381                       regs.regs[2]);
1382                 gd->bd->bi_dram[i].start = regs.regs[1];
1383                 gd->bd->bi_dram[i].size = regs.regs[2];
1384
1385                 dram_size -= gd->bd->bi_dram[i].size;
1386
1387                 i++;
1388         } while (dram_size);
1389
1390         if (i > 0)
1391                 ret = 0;
1392
1393 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1394         /* Assign memory for MC */
1395 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1396         if (gd->bd->bi_dram[2].size >=
1397             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1398                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1399                             gd->bd->bi_dram[2].size -
1400                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1401         } else
1402 #endif
1403         {
1404                 if (gd->bd->bi_dram[1].size >=
1405                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1406                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1407                                 gd->bd->bi_dram[1].size -
1408                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1409                 } else if (gd->bd->bi_dram[0].size >
1410                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1411                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1412                                 gd->bd->bi_dram[0].size -
1413                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1414                 }
1415         }
1416 #endif  /* CONFIG_RESV_RAM */
1417
1418         return ret;
1419 }
1420 #endif
1421
1422 int dram_init_banksize(void)
1423 {
1424 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1425         phys_size_t dp_ddr_size;
1426 #endif
1427
1428 #ifdef CONFIG_TFABOOT
1429         if (!tfa_dram_init_banksize())
1430                 return 0;
1431 #endif
1432         /*
1433          * gd->ram_size has the total size of DDR memory, less reserved secure
1434          * memory. The DDR extends from low region to high region(s) presuming
1435          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1436          * the location of secure memory. gd->arch.resv_ram tracks the location
1437          * of reserved memory for Management Complex (MC). Because gd->ram_size
1438          * is reduced by this function if secure memory is reserved, checking
1439          * gd->arch.secure_ram should be done to avoid running it repeatedly.
1440          */
1441
1442 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1443         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1444                 debug("No need to run again, skip %s\n", __func__);
1445
1446                 return 0;
1447         }
1448 #endif
1449
1450         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1451         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1452                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1453                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1454                 gd->bd->bi_dram[1].size = gd->ram_size -
1455                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
1456 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1457                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1458                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1459                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1460                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
1461                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1462                 }
1463 #endif
1464         } else {
1465                 gd->bd->bi_dram[0].size = gd->ram_size;
1466         }
1467 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1468         if (gd->bd->bi_dram[0].size >
1469                                 CONFIG_SYS_MEM_RESERVE_SECURE) {
1470                 gd->bd->bi_dram[0].size -=
1471                                 CONFIG_SYS_MEM_RESERVE_SECURE;
1472                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1473                                       gd->bd->bi_dram[0].size;
1474                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1475                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1476         }
1477 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
1478
1479 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1480         /* Assign memory for MC */
1481 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1482         if (gd->bd->bi_dram[2].size >=
1483             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1484                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1485                             gd->bd->bi_dram[2].size -
1486                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1487         } else
1488 #endif
1489         {
1490                 if (gd->bd->bi_dram[1].size >=
1491                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1492                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1493                                 gd->bd->bi_dram[1].size -
1494                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1495                 } else if (gd->bd->bi_dram[0].size >
1496                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1497                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1498                                 gd->bd->bi_dram[0].size -
1499                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1500                 }
1501         }
1502 #endif  /* CONFIG_RESV_RAM */
1503
1504 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1505 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1506 #error "This SoC shouldn't have DP DDR"
1507 #endif
1508         if (soc_has_dp_ddr()) {
1509                 /* initialize DP-DDR here */
1510                 puts("DP-DDR:  ");
1511                 /*
1512                  * DDR controller use 0 as the base address for binding.
1513                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1514                  */
1515                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1516                                           CONFIG_DP_DDR_CTRL,
1517                                           CONFIG_DP_DDR_NUM_CTRLS,
1518                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1519                                           NULL, NULL, NULL);
1520                 if (dp_ddr_size) {
1521                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1522                         gd->bd->bi_dram[2].size = dp_ddr_size;
1523                 } else {
1524                         puts("Not detected");
1525                 }
1526         }
1527 #endif
1528
1529 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1530         debug("%s is called. gd->ram_size is reduced to %lu\n",
1531               __func__, (ulong)gd->ram_size);
1532 #endif
1533
1534         return 0;
1535 }
1536
1537 #if CONFIG_IS_ENABLED(EFI_LOADER)
1538 void efi_add_known_memory(void)
1539 {
1540         int i;
1541         phys_addr_t ram_start;
1542         phys_size_t ram_size;
1543
1544         /* Add RAM */
1545         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1546 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1547 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1548 #error "This SoC shouldn't have DP DDR"
1549 #endif
1550                 if (i == 2)
1551                         continue;       /* skip DP-DDR */
1552 #endif
1553                 ram_start = gd->bd->bi_dram[i].start;
1554                 ram_size = gd->bd->bi_dram[i].size;
1555 #ifdef CONFIG_RESV_RAM
1556                 if (gd->arch.resv_ram >= ram_start &&
1557                     gd->arch.resv_ram < ram_start + ram_size)
1558                         ram_size = gd->arch.resv_ram - ram_start;
1559 #endif
1560                 efi_add_memory_map(ram_start, ram_size,
1561                                    EFI_CONVENTIONAL_MEMORY);
1562         }
1563 }
1564 #endif
1565
1566 /*
1567  * Before DDR size is known, early MMU table have DDR mapped as device memory
1568  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1569  * needs to be set for these mappings.
1570  * If a special case configures DDR with holes in the mapping, the holes need
1571  * to be marked as invalid. This is not implemented in this function.
1572  */
1573 void update_early_mmu_table(void)
1574 {
1575         if (!gd->arch.tlb_addr)
1576                 return;
1577
1578         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1579                 mmu_change_region_attr(
1580                                         CONFIG_SYS_SDRAM_BASE,
1581                                         gd->ram_size,
1582                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1583                                         PTE_BLOCK_OUTER_SHARE           |
1584                                         PTE_BLOCK_NS                    |
1585                                         PTE_TYPE_VALID);
1586         } else {
1587                 mmu_change_region_attr(
1588                                         CONFIG_SYS_SDRAM_BASE,
1589                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1590                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1591                                         PTE_BLOCK_OUTER_SHARE           |
1592                                         PTE_BLOCK_NS                    |
1593                                         PTE_TYPE_VALID);
1594 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1595 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1596 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1597 #endif
1598                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1599                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
1600                         mmu_change_region_attr(
1601                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1602                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1603                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1604                                         PTE_BLOCK_OUTER_SHARE           |
1605                                         PTE_BLOCK_NS                    |
1606                                         PTE_TYPE_VALID);
1607                         mmu_change_region_attr(
1608                                         CONFIG_SYS_DDR_BLOCK3_BASE,
1609                                         gd->ram_size -
1610                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
1611                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1612                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1613                                         PTE_BLOCK_OUTER_SHARE           |
1614                                         PTE_BLOCK_NS                    |
1615                                         PTE_TYPE_VALID);
1616                 } else
1617 #endif
1618                 {
1619                         mmu_change_region_attr(
1620                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1621                                         gd->ram_size -
1622                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1623                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1624                                         PTE_BLOCK_OUTER_SHARE           |
1625                                         PTE_BLOCK_NS                    |
1626                                         PTE_TYPE_VALID);
1627                 }
1628         }
1629 }
1630
1631 __weak int dram_init(void)
1632 {
1633         fsl_initdram();
1634 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1635         defined(CONFIG_SPL_BUILD)
1636         /* This will break-before-make MMU for DDR */
1637         update_early_mmu_table();
1638 #endif
1639
1640         return 0;
1641 }
1642
1643 #ifdef CONFIG_ARCH_MISC_INIT
1644 __weak int serdes_misc_init(void)
1645 {
1646         return 0;
1647 }
1648
1649 int arch_misc_init(void)
1650 {
1651         serdes_misc_init();
1652
1653         return 0;
1654 }
1655 #endif