arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <fsl_ddr_sdram.h>
   9 #include <asm/io.h>
  10 #include <linux/errno.h>
  11 #include <asm/system.h>
  12 #include <fm_eth.h>
  13 #include <asm/armv8/mmu.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/fsl_serdes.h>
  16 #include <asm/arch/soc.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/speed.h>
  19 #include <fsl_immap.h>
  20 #include <asm/arch/mp.h>
  21 #include <efi_loader.h>
  22 #include <fsl-mc/fsl_mc.h>
  23 #ifdef CONFIG_FSL_ESDHC
  24 #include <fsl_esdhc.h>
  25 #endif
  26 #include <asm/armv8/sec_firmware.h>
  27 #ifdef CONFIG_SYS_FSL_DDR
  28 #include <fsl_ddr.h>
  29 #endif
  30 #include <asm/arch/clock.h>
  31 #include <hwconfig.h>
  32 #include <fsl_qbman.h>
  33
  34 #ifdef CONFIG_TFABOOT
  35 #include <environment.h>
  36 #endif
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 static struct cpu_type cpu_type_list[] = {
  41         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  42         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  43         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  44         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  45         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  46         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  47         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  48         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  49         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  50         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  51         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  52         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  53         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  54         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  55         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  56         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  57         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  58         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  59         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  60 };
  61
  62 #define EARLY_PGTABLE_SIZE 0x5000
  63 static struct mm_region early_map[] = {
  64 #ifdef CONFIG_FSL_LSCH3
  65         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  66           CONFIG_SYS_FSL_CCSR_SIZE,
  67           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  68           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  69         },
  70         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  71           SYS_FSL_OCRAM_SPACE_SIZE,
  72           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  73         },
  74         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
  75           CONFIG_SYS_FSL_QSPI_SIZE1,
  76           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
  77 #ifdef CONFIG_FSL_IFC
  78         /* For IFC Region #1, only the first 4MB is cache-enabled */
  79         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  80           CONFIG_SYS_FSL_IFC_SIZE1_1,
  81           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  82         },
  83         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  84           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  85           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
  86           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
  87         },
  88         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
  89           CONFIG_SYS_FSL_IFC_SIZE1,
  90           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
  91         },
  92 #endif
  93         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  94           CONFIG_SYS_FSL_DRAM_SIZE1,
  95 #if defined(CONFIG_TFABOOT) || \
  96         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
  97           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  98 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
  99           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 100 #endif
 101           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 102         },
 103 #ifdef CONFIG_FSL_IFC
 104         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 105         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 106           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 107           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 108         },
 109 #endif
 110         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 111           CONFIG_SYS_FSL_DCSR_SIZE,
 112           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 113           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 114         },
 115         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 116           CONFIG_SYS_FSL_DRAM_SIZE2,
 117           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 118           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 119         },
 120 #elif defined(CONFIG_FSL_LSCH2)
 121         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 122           CONFIG_SYS_FSL_CCSR_SIZE,
 123           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 124           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 125         },
 126         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 127           SYS_FSL_OCRAM_SPACE_SIZE,
 128           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 129         },
 130         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 131           CONFIG_SYS_FSL_DCSR_SIZE,
 132           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 133           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 134         },
 135         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 136           CONFIG_SYS_FSL_QSPI_SIZE,
 137           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 138         },
 139 #ifdef CONFIG_FSL_IFC
 140         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 141           CONFIG_SYS_FSL_IFC_SIZE,
 142           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 143         },
 144 #endif
 145         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 146           CONFIG_SYS_FSL_DRAM_SIZE1,
 147 #if defined(CONFIG_TFABOOT) || \
 148         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 149           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 150 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 151           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 152 #endif
 153           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 154         },
 155         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 156           CONFIG_SYS_FSL_DRAM_SIZE2,
 157           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 158           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 159         },
 160 #endif
 161         {},     /* list terminator */
 162 };
 163
 164 static struct mm_region final_map[] = {
 165 #ifdef CONFIG_FSL_LSCH3
 166         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 167           CONFIG_SYS_FSL_CCSR_SIZE,
 168           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 169           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 170         },
 171         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 172           SYS_FSL_OCRAM_SPACE_SIZE,
 173           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 174         },
 175         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 176           CONFIG_SYS_FSL_DRAM_SIZE1,
 177           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 178           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 179         },
 180         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 181           CONFIG_SYS_FSL_QSPI_SIZE1,
 182           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 183           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 184         },
 185         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 186           CONFIG_SYS_FSL_QSPI_SIZE2,
 187           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 188           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 189         },
 190 #ifdef CONFIG_FSL_IFC
 191         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 192           CONFIG_SYS_FSL_IFC_SIZE2,
 193           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 194           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 195         },
 196 #endif
 197         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 198           CONFIG_SYS_FSL_DCSR_SIZE,
 199           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 200           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 201         },
 202         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 203           CONFIG_SYS_FSL_MC_SIZE,
 204           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 205           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 206         },
 207         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 208           CONFIG_SYS_FSL_NI_SIZE,
 209           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 210           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 211         },
 212         /* For QBMAN portal, only the first 64MB is cache-enabled */
 213         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 214           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 215           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 216           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 217         },
 218         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 219           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 220           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 221           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 222           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 223         },
 224         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 225           CONFIG_SYS_PCIE1_PHYS_SIZE,
 226           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 227           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 228         },
 229         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 230           CONFIG_SYS_PCIE2_PHYS_SIZE,
 231           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 232           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 233         },
 234         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 235           CONFIG_SYS_PCIE3_PHYS_SIZE,
 236           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 237           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 238         },
 239 #ifdef CONFIG_ARCH_LS2080A
 240         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 241           CONFIG_SYS_PCIE4_PHYS_SIZE,
 242           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 243           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 244         },
 245 #endif
 246         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 247           CONFIG_SYS_FSL_WRIOP1_SIZE,
 248           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 249           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 250         },
 251         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 252           CONFIG_SYS_FSL_AIOP1_SIZE,
 253           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 254           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 255         },
 256         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 257           CONFIG_SYS_FSL_PEBUF_SIZE,
 258           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 259           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 260         },
 261         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 262           CONFIG_SYS_FSL_DRAM_SIZE2,
 263           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 264           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 265         },
 266 #elif defined(CONFIG_FSL_LSCH2)
 267         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 268           CONFIG_SYS_FSL_BOOTROM_SIZE,
 269           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 270           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 271         },
 272         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 273           CONFIG_SYS_FSL_CCSR_SIZE,
 274           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 275           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 276         },
 277         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 278           SYS_FSL_OCRAM_SPACE_SIZE,
 279           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 280         },
 281         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 282           CONFIG_SYS_FSL_DCSR_SIZE,
 283           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 284           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 285         },
 286         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 287           CONFIG_SYS_FSL_QSPI_SIZE,
 288           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 289           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 290         },
 291 #ifdef CONFIG_FSL_IFC
 292         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 293           CONFIG_SYS_FSL_IFC_SIZE,
 294           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 295         },
 296 #endif
 297         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 298           CONFIG_SYS_FSL_DRAM_SIZE1,
 299           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 300           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 301         },
 302         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 303           CONFIG_SYS_FSL_QBMAN_SIZE,
 304           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 305           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 306         },
 307         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 308           CONFIG_SYS_FSL_DRAM_SIZE2,
 309           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 310           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 311         },
 312         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 313           CONFIG_SYS_PCIE1_PHYS_SIZE,
 314           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 315           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 316         },
 317         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 318           CONFIG_SYS_PCIE2_PHYS_SIZE,
 319           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 320           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 321         },
 322         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 323           CONFIG_SYS_PCIE3_PHYS_SIZE,
 324           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 325           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 326         },
 327         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 328           CONFIG_SYS_FSL_DRAM_SIZE3,
 329           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 330           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 331         },
 332 #endif
 333 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 334         {},     /* space holder for secure mem */
 335 #endif
 336         {},
 337 };
 338
 339 struct mm_region *mem_map = early_map;
 340
 341 void cpu_name(char *name)
 342 {
 343         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 344         unsigned int i, svr, ver;
 345
 346         svr = gur_in32(&gur->svr);
 347         ver = SVR_SOC_VER(svr);
 348
 349         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 350                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 351                         strcpy(name, cpu_type_list[i].name);
 352
 353                         if (IS_E_PROCESSOR(svr))
 354                                 strcat(name, "E");
 355
 356                         sprintf(name + strlen(name), " Rev%d.%d",
 357                                 SVR_MAJ(svr), SVR_MIN(svr));
 358                         break;
 359                 }
 360
 361         if (i == ARRAY_SIZE(cpu_type_list))
 362                 strcpy(name, "unknown");
 363 }
 364
 365 #ifndef CONFIG_SYS_DCACHE_OFF
 366 /*
 367  * To start MMU before DDR is available, we create MMU table in SRAM.
 368  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 369  * levels of translation tables here to cover 40-bit address space.
 370  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 371  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 372  * Note, the debug print in cache_v8.c is not usable for debugging
 373  * these early MMU tables because UART is not yet available.
 374  */
 375 static inline void early_mmu_setup(void)
 376 {
 377         unsigned int el = current_el();
 378
 379         /* global data is already setup, no allocation yet */
 380         if (el == 3)
 381                 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 382         else
 383                 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 384         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 385         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 386
 387         /* Create early page tables */
 388         setup_pgtables();
 389
 390         /* point TTBR to the new table */
 391         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 392                           get_tcr(el, NULL, NULL) &
 393                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 394                           MEMORY_ATTRIBUTES);
 395
 396         set_sctlr(get_sctlr() | CR_M);
 397 }
 398
 399 static void fix_pcie_mmu_map(void)
 400 {
 401 #ifdef CONFIG_ARCH_LS2080A
 402         unsigned int i;
 403         u32 svr, ver;
 404         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 405
 406         svr = gur_in32(&gur->svr);
 407         ver = SVR_SOC_VER(svr);
 408
 409         /* Fix PCIE base and size for LS2088A */
 410         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 411             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 412             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 413                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 414                         switch (final_map[i].phys) {
 415                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 416                                 final_map[i].phys = 0x2000000000ULL;
 417                                 final_map[i].virt = 0x2000000000ULL;
 418                                 final_map[i].size = 0x800000000ULL;
 419                                 break;
 420                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 421                                 final_map[i].phys = 0x2800000000ULL;
 422                                 final_map[i].virt = 0x2800000000ULL;
 423                                 final_map[i].size = 0x800000000ULL;
 424                                 break;
 425                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 426                                 final_map[i].phys = 0x3000000000ULL;
 427                                 final_map[i].virt = 0x3000000000ULL;
 428                                 final_map[i].size = 0x800000000ULL;
 429                                 break;
 430                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 431                                 final_map[i].phys = 0x3800000000ULL;
 432                                 final_map[i].virt = 0x3800000000ULL;
 433                                 final_map[i].size = 0x800000000ULL;
 434                                 break;
 435                         default:
 436                                 break;
 437                         }
 438                 }
 439         }
 440 #endif
 441 }
 442
 443 /*
 444  * The final tables look similar to early tables, but different in detail.
 445  * These tables are in DRAM. Sub tables are added to enable cache for
 446  * QBMan and OCRAM.
 447  *
 448  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 449  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 450  */
 451 static inline void final_mmu_setup(void)
 452 {
 453         u64 tlb_addr_save = gd->arch.tlb_addr;
 454         unsigned int el = current_el();
 455         int index;
 456
 457         /* fix the final_map before filling in the block entries */
 458         fix_pcie_mmu_map();
 459
 460         mem_map = final_map;
 461
 462         /* Update mapping for DDR to actual size */
 463         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 464                 /*
 465                  * Find the entry for DDR mapping and update the address and
 466                  * size. Zero-sized mapping will be skipped when creating MMU
 467                  * table.
 468                  */
 469                 switch (final_map[index].virt) {
 470                 case CONFIG_SYS_FSL_DRAM_BASE1:
 471                         final_map[index].virt = gd->bd->bi_dram[0].start;
 472                         final_map[index].phys = gd->bd->bi_dram[0].start;
 473                         final_map[index].size = gd->bd->bi_dram[0].size;
 474                         break;
 475 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 476                 case CONFIG_SYS_FSL_DRAM_BASE2:
 477 #if (CONFIG_NR_DRAM_BANKS >= 2)
 478                         final_map[index].virt = gd->bd->bi_dram[1].start;
 479                         final_map[index].phys = gd->bd->bi_dram[1].start;
 480                         final_map[index].size = gd->bd->bi_dram[1].size;
 481 #else
 482                         final_map[index].size = 0;
 483 #endif
 484                 break;
 485 #endif
 486 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 487                 case CONFIG_SYS_FSL_DRAM_BASE3:
 488 #if (CONFIG_NR_DRAM_BANKS >= 3)
 489                         final_map[index].virt = gd->bd->bi_dram[2].start;
 490                         final_map[index].phys = gd->bd->bi_dram[2].start;
 491                         final_map[index].size = gd->bd->bi_dram[2].size;
 492 #else
 493                         final_map[index].size = 0;
 494 #endif
 495                 break;
 496 #endif
 497                 default:
 498                         break;
 499                 }
 500         }
 501
 502 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 503         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 504                 if (el == 3) {
 505                         /*
 506                          * Only use gd->arch.secure_ram if the address is
 507                          * recalculated. Align to 4KB for MMU table.
 508                          */
 509                         /* put page tables in secure ram */
 510                         index = ARRAY_SIZE(final_map) - 2;
 511                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 512                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 513                         final_map[index].phys = final_map[index].virt;
 514                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 515                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 516                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 517                         tlb_addr_save = gd->arch.tlb_addr;
 518                 } else {
 519                         /* Use allocated (board_f.c) memory for TLB */
 520                         tlb_addr_save = gd->arch.tlb_allocated;
 521                         gd->arch.tlb_addr = tlb_addr_save;
 522                 }
 523         }
 524 #endif
 525
 526         /* Reset the fill ptr */
 527         gd->arch.tlb_fillptr = tlb_addr_save;
 528
 529         /* Create normal system page tables */
 530         setup_pgtables();
 531
 532         /* Create emergency page tables */
 533         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 534         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 535         setup_pgtables();
 536         gd->arch.tlb_addr = tlb_addr_save;
 537
 538         /* Disable cache and MMU */
 539         dcache_disable();       /* TLBs are invalidated */
 540         invalidate_icache_all();
 541
 542         /* point TTBR to the new table */
 543         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 544                           MEMORY_ATTRIBUTES);
 545
 546         set_sctlr(get_sctlr() | CR_M);
 547 }
 548
 549 u64 get_page_table_size(void)
 550 {
 551         return 0x10000;
 552 }
 553
 554 int arch_cpu_init(void)
 555 {
 556         /*
 557          * This function is called before U-Boot relocates itself to speed up
 558          * on system running. It is not necessary to run if performance is not
 559          * critical. Skip if MMU is already enabled by SPL or other means.
 560          */
 561         if (get_sctlr() & CR_M)
 562                 return 0;
 563
 564         icache_enable();
 565         __asm_invalidate_dcache_all();
 566         __asm_invalidate_tlb_all();
 567         early_mmu_setup();
 568         set_sctlr(get_sctlr() | CR_C);
 569         return 0;
 570 }
 571
 572 void mmu_setup(void)
 573 {
 574         final_mmu_setup();
 575 }
 576
 577 /*
 578  * This function is called from common/board_r.c.
 579  * It recreates MMU table in main memory.
 580  */
 581 void enable_caches(void)
 582 {
 583         mmu_setup();
 584         __asm_invalidate_tlb_all();
 585         icache_enable();
 586         dcache_enable();
 587 }
 588 #endif  /* CONFIG_SYS_DCACHE_OFF */
 589
 590 #ifdef CONFIG_TFABOOT
 591 enum boot_src __get_boot_src(u32 porsr1)
 592 {
 593         enum boot_src src = BOOT_SOURCE_RESERVED;
 594         u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
 595 #if !defined(CONFIG_FSL_LSCH3_2)
 596         u32 val;
 597 #endif
 598         debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
 599
 600 #if defined(CONFIG_FSL_LSCH3)
 601 #if defined(CONFIG_FSL_LSCH3_2)
 602         switch (rcw_src) {
 603         case RCW_SRC_SDHC1_VAL:
 604                 src = BOOT_SOURCE_SD_MMC;
 605         break;
 606         case RCW_SRC_SDHC2_VAL:
 607                 src = BOOT_SOURCE_SD_MMC2;
 608         break;
 609         case RCW_SRC_I2C1_VAL:
 610                 src = BOOT_SOURCE_I2C1_EXTENDED;
 611         break;
 612         case RCW_SRC_FLEXSPI_NAND2K_VAL:
 613                 src = BOOT_SOURCE_XSPI_NAND;
 614         break;
 615         case RCW_SRC_FLEXSPI_NAND4K_VAL:
 616                 src = BOOT_SOURCE_XSPI_NAND;
 617         break;
 618         case RCW_SRC_RESERVED_1_VAL:
 619                 src = BOOT_SOURCE_RESERVED;
 620         break;
 621         case RCW_SRC_FLEXSPI_NOR_24B:
 622                 src = BOOT_SOURCE_XSPI_NOR;
 623         break;
 624         default:
 625                 src = BOOT_SOURCE_RESERVED;
 626         }
 627 #else
 628         val = rcw_src & RCW_SRC_TYPE_MASK;
 629         if (val == RCW_SRC_NOR_VAL) {
 630                 val = rcw_src & NOR_TYPE_MASK;
 631
 632                 switch (val) {
 633                 case NOR_16B_VAL:
 634                 case NOR_32B_VAL:
 635                         src = BOOT_SOURCE_IFC_NOR;
 636                 break;
 637                 default:
 638                         src = BOOT_SOURCE_RESERVED;
 639                 }
 640         } else {
 641                 /* RCW SRC Serial Flash */
 642                 val = rcw_src & RCW_SRC_SERIAL_MASK;
 643                 switch (val) {
 644                 case RCW_SRC_QSPI_VAL:
 645                 /* RCW SRC Serial NOR (QSPI) */
 646                         src = BOOT_SOURCE_QSPI_NOR;
 647                         break;
 648                 case RCW_SRC_SD_CARD_VAL:
 649                 /* RCW SRC SD Card */
 650                         src = BOOT_SOURCE_SD_MMC;
 651                         break;
 652                 case RCW_SRC_EMMC_VAL:
 653                 /* RCW SRC EMMC */
 654                         src = BOOT_SOURCE_SD_MMC2;
 655                         break;
 656                 case RCW_SRC_I2C1_VAL:
 657                 /* RCW SRC I2C1 Extended */
 658                         src = BOOT_SOURCE_I2C1_EXTENDED;
 659                         break;
 660                 default:
 661                         src = BOOT_SOURCE_RESERVED;
 662                 }
 663         }
 664 #endif
 665 #elif defined(CONFIG_FSL_LSCH2)
 666         /* RCW SRC NAND */
 667         val = rcw_src & RCW_SRC_NAND_MASK;
 668         if (val == RCW_SRC_NAND_VAL) {
 669                 val = rcw_src & NAND_RESERVED_MASK;
 670                 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
 671                         src = BOOT_SOURCE_IFC_NAND;
 672
 673         } else {
 674                 /* RCW SRC NOR */
 675                 val = rcw_src & RCW_SRC_NOR_MASK;
 676                 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
 677                         src = BOOT_SOURCE_IFC_NOR;
 678                 } else {
 679                         switch (rcw_src) {
 680                         case QSPI_VAL1:
 681                         case QSPI_VAL2:
 682                                 src = BOOT_SOURCE_QSPI_NOR;
 683                                 break;
 684                         case SD_VAL:
 685                                 src = BOOT_SOURCE_SD_MMC;
 686                                 break;
 687                         default:
 688                                 src = BOOT_SOURCE_RESERVED;
 689                         }
 690                 }
 691         }
 692 #endif
 693         debug("%s: src 0x%x\n", __func__, src);
 694         return src;
 695 }
 696
 697 enum boot_src get_boot_src(void)
 698 {
 699         u32 porsr1;
 700
 701 #if defined(CONFIG_FSL_LSCH3)
 702         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 703
 704         porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 705 #elif defined(CONFIG_FSL_LSCH2)
 706         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 707
 708         porsr1 = in_be32(&gur->porsr1);
 709 #endif
 710         debug("%s: porsr1 0x%x\n", __func__, porsr1);
 711
 712         return __get_boot_src(porsr1);
 713 }
 714
 715 #ifdef CONFIG_ENV_IS_IN_MMC
 716 int mmc_get_env_dev(void)
 717 {
 718         enum boot_src src = get_boot_src();
 719         int dev = CONFIG_SYS_MMC_ENV_DEV;
 720
 721         switch (src) {
 722         case BOOT_SOURCE_SD_MMC:
 723                 dev = 0;
 724                 break;
 725         case BOOT_SOURCE_SD_MMC2:
 726                 dev = 1;
 727                 break;
 728         default:
 729                 break;
 730         }
 731
 732         return dev;
 733 }
 734 #endif
 735
 736 enum env_location env_get_location(enum env_operation op, int prio)
 737 {
 738         enum boot_src src = get_boot_src();
 739         enum env_location env_loc = ENVL_NOWHERE;
 740
 741         if (prio)
 742                 return ENVL_UNKNOWN;
 743
 744         switch (src) {
 745         case BOOT_SOURCE_IFC_NOR:
 746                 env_loc = ENVL_FLASH;
 747                 break;
 748         case BOOT_SOURCE_QSPI_NOR:
 749                 /* FALLTHROUGH */
 750         case BOOT_SOURCE_XSPI_NOR:
 751                 env_loc = ENVL_SPI_FLASH;
 752                 break;
 753         case BOOT_SOURCE_IFC_NAND:
 754                 /* FALLTHROUGH */
 755         case BOOT_SOURCE_QSPI_NAND:
 756                 /* FALLTHROUGH */
 757         case BOOT_SOURCE_XSPI_NAND:
 758                 env_loc = ENVL_NAND;
 759                 break;
 760         case BOOT_SOURCE_SD_MMC:
 761                 /* FALLTHROUGH */
 762         case BOOT_SOURCE_SD_MMC2:
 763                 env_loc =  ENVL_MMC;
 764                 break;
 765         case BOOT_SOURCE_I2C1_EXTENDED:
 766                 /* FALLTHROUGH */
 767         default:
 768                 break;
 769         }
 770
 771         return env_loc;
 772 }
 773 #endif  /* CONFIG_TFABOOT */
 774
 775 u32 initiator_type(u32 cluster, int init_id)
 776 {
 777         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 778         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 779         u32 type = 0;
 780
 781         type = gur_in32(&gur->tp_ityp[idx]);
 782         if (type & TP_ITYP_AV)
 783                 return type;
 784
 785         return 0;
 786 }
 787
 788 u32 cpu_pos_mask(void)
 789 {
 790         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 791         int i = 0;
 792         u32 cluster, type, mask = 0;
 793
 794         do {
 795                 int j;
 796
 797                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 798                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 799                         type = initiator_type(cluster, j);
 800                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 801                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 802                 }
 803                 i++;
 804         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 805
 806         return mask;
 807 }
 808
 809 u32 cpu_mask(void)
 810 {
 811         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 812         int i = 0, count = 0;
 813         u32 cluster, type, mask = 0;
 814
 815         do {
 816                 int j;
 817
 818                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 819                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 820                         type = initiator_type(cluster, j);
 821                         if (type) {
 822                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 823                                         mask |= 1 << count;
 824                                 count++;
 825                         }
 826                 }
 827                 i++;
 828         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 829
 830         return mask;
 831 }
 832
 833 /*
 834  * Return the number of cores on this SOC.
 835  */
 836 int cpu_numcores(void)
 837 {
 838         return hweight32(cpu_mask());
 839 }
 840
 841 int fsl_qoriq_core_to_cluster(unsigned int core)
 842 {
 843         struct ccsr_gur __iomem *gur =
 844                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 845         int i = 0, count = 0;
 846         u32 cluster;
 847
 848         do {
 849                 int j;
 850
 851                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 852                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 853                         if (initiator_type(cluster, j)) {
 854                                 if (count == core)
 855                                         return i;
 856                                 count++;
 857                         }
 858                 }
 859                 i++;
 860         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 861
 862         return -1;      /* cannot identify the cluster */
 863 }
 864
 865 u32 fsl_qoriq_core_to_type(unsigned int core)
 866 {
 867         struct ccsr_gur __iomem *gur =
 868                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 869         int i = 0, count = 0;
 870         u32 cluster, type;
 871
 872         do {
 873                 int j;
 874
 875                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 876                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 877                         type = initiator_type(cluster, j);
 878                         if (type) {
 879                                 if (count == core)
 880                                         return type;
 881                                 count++;
 882                         }
 883                 }
 884                 i++;
 885         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 886
 887         return -1;      /* cannot identify the cluster */
 888 }
 889
 890 #ifndef CONFIG_FSL_LSCH3
 891 uint get_svr(void)
 892 {
 893         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 894
 895         return gur_in32(&gur->svr);
 896 }
 897 #endif
 898
 899 #ifdef CONFIG_DISPLAY_CPUINFO
 900 int print_cpuinfo(void)
 901 {
 902         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 903         struct sys_info sysinfo;
 904         char buf[32];
 905         unsigned int i, core;
 906         u32 type, rcw, svr = gur_in32(&gur->svr);
 907
 908         puts("SoC: ");
 909
 910         cpu_name(buf);
 911         printf(" %s (0x%x)\n", buf, svr);
 912         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 913         get_sys_info(&sysinfo);
 914         puts("Clock Configuration:");
 915         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 916                 if (!(i % 3))
 917                         puts("\n       ");
 918                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
 919                 printf("CPU%d(%s):%-4s MHz  ", core,
 920                        type == TY_ITYP_VER_A7 ? "A7 " :
 921                        (type == TY_ITYP_VER_A53 ? "A53" :
 922                        (type == TY_ITYP_VER_A57 ? "A57" :
 923                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
 924                        strmhz(buf, sysinfo.freq_processor[core]));
 925         }
 926         /* Display platform clock as Bus frequency. */
 927         printf("\n       Bus:      %-4s MHz  ",
 928                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
 929         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
 930 #ifdef CONFIG_SYS_DPAA_FMAN
 931         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 932 #endif
 933 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 934         if (soc_has_dp_ddr()) {
 935                 printf("     DP-DDR:   %-4s MT/s",
 936                        strmhz(buf, sysinfo.freq_ddrbus2));
 937         }
 938 #endif
 939         puts("\n");
 940
 941         /*
 942          * Display the RCW, so that no one gets confused as to what RCW
 943          * we're actually using for this boot.
 944          */
 945         puts("Reset Configuration Word (RCW):");
 946         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
 947                 rcw = gur_in32(&gur->rcwsr[i]);
 948                 if ((i % 4) == 0)
 949                         printf("\n       %08x:", i * 4);
 950                 printf(" %08x", rcw);
 951         }
 952         puts("\n");
 953
 954         return 0;
 955 }
 956 #endif
 957
 958 #ifdef CONFIG_FSL_ESDHC
 959 int cpu_mmc_init(bd_t *bis)
 960 {
 961         return fsl_esdhc_mmc_init(bis);
 962 }
 963 #endif
 964
 965 int cpu_eth_init(bd_t *bis)
 966 {
 967         int error = 0;
 968
 969 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 970         error = fsl_mc_ldpaa_init(bis);
 971 #endif
 972 #ifdef CONFIG_FMAN_ENET
 973         fm_standard_init(bis);
 974 #endif
 975         return error;
 976 }
 977
 978 static inline int check_psci(void)
 979 {
 980         unsigned int psci_ver;
 981
 982         psci_ver = sec_firmware_support_psci_version();
 983         if (psci_ver == PSCI_INVALID_VER)
 984                 return 1;
 985
 986         return 0;
 987 }
 988
 989 static void config_core_prefetch(void)
 990 {
 991         char *buf = NULL;
 992         char buffer[HWCONFIG_BUFFER_SIZE];
 993         const char *prefetch_arg = NULL;
 994         size_t arglen;
 995         unsigned int mask;
 996         struct pt_regs regs;
 997
 998         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
 999                 buf = buffer;
1000
1001         prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1002                                          &arglen, buf);
1003
1004         if (prefetch_arg) {
1005                 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1006                 if (mask & 0x1) {
1007                         printf("Core0 prefetch can't be disabled\n");
1008                         return;
1009                 }
1010
1011 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1012                 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1013                 regs.regs[1] = mask;
1014                 smc_call(&regs);
1015
1016                 if (regs.regs[0])
1017                         printf("Prefetch disable config failed for mask ");
1018                 else
1019                         printf("Prefetch disable config passed for mask ");
1020                 printf("0x%x\n", mask);
1021         }
1022 }
1023
1024 int arch_early_init_r(void)
1025 {
1026 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1027         u32 svr_dev_id;
1028         /*
1029          * erratum A009635 is valid only for LS2080A SoC and
1030          * its personalitiesi
1031          */
1032         svr_dev_id = get_svr();
1033         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1034                 erratum_a009635();
1035 #endif
1036 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1037         erratum_a009942_check_cpo();
1038 #endif
1039         if (check_psci()) {
1040                 debug("PSCI: PSCI does not exist.\n");
1041
1042                 /* if PSCI does not exist, boot secondary cores here */
1043                 if (fsl_layerscape_wake_seconday_cores())
1044                         printf("Did not wake secondary cores\n");
1045         }
1046
1047 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1048         fsl_rgmii_init();
1049 #endif
1050
1051         config_core_prefetch();
1052
1053 #ifdef CONFIG_SYS_HAS_SERDES
1054         fsl_serdes_init();
1055 #endif
1056 #ifdef CONFIG_FMAN_ENET
1057         fman_enet_init();
1058 #endif
1059 #ifdef CONFIG_SYS_DPAA_QBMAN
1060         setup_qbman_portals();
1061 #endif
1062         return 0;
1063 }
1064
1065 int timer_init(void)
1066 {
1067         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1068 #ifdef CONFIG_FSL_LSCH3
1069         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1070 #endif
1071 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
1072         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1073         u32 svr_dev_id;
1074 #endif
1075 #ifdef COUNTER_FREQUENCY_REAL
1076         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1077
1078         /* Update with accurate clock frequency */
1079         if (current_el() == 3)
1080                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1081 #endif
1082
1083 #ifdef CONFIG_FSL_LSCH3
1084         /* Enable timebase for all clusters.
1085          * It is safe to do so even some clusters are not enabled.
1086          */
1087         out_le32(cltbenr, 0xf);
1088 #endif
1089
1090 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
1091         /*
1092          * In certain Layerscape SoCs, the clock for each core's
1093          * has an enable bit in the PMU Physical Core Time Base Enable
1094          * Register (PCTBENR), which allows the watchdog to operate.
1095          */
1096         setbits_le32(pctbenr, 0xff);
1097         /*
1098          * For LS2080A SoC and its personalities, timer controller
1099          * offset is different
1100          */
1101         svr_dev_id = get_svr();
1102         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1103                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1104
1105 #endif
1106
1107         /* Enable clock for timer
1108          * This is a global setting.
1109          */
1110         out_le32(cntcr, 0x1);
1111
1112         return 0;
1113 }
1114
1115 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1116
1117 void __efi_runtime reset_cpu(ulong addr)
1118 {
1119         u32 val;
1120
1121         /* Raise RESET_REQ_B */
1122         val = scfg_in32(rstcr);
1123         val |= 0x02;
1124         scfg_out32(rstcr, val);
1125 }
1126
1127 #ifdef CONFIG_EFI_LOADER
1128
1129 void __efi_runtime EFIAPI efi_reset_system(
1130                        enum efi_reset_type reset_type,
1131                        efi_status_t reset_status,
1132                        unsigned long data_size, void *reset_data)
1133 {
1134         switch (reset_type) {
1135         case EFI_RESET_COLD:
1136         case EFI_RESET_WARM:
1137         case EFI_RESET_PLATFORM_SPECIFIC:
1138                 reset_cpu(0);
1139                 break;
1140         case EFI_RESET_SHUTDOWN:
1141                 /* Nothing we can do */
1142                 break;
1143         }
1144
1145         while (1) { }
1146 }
1147
1148 efi_status_t efi_reset_system_init(void)
1149 {
1150         return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1151 }
1152
1153 #endif
1154
1155 /*
1156  * Calculate reserved memory with given memory bank
1157  * Return aligned memory size on success
1158  * Return (ram_size + needed size) for failure
1159  */
1160 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1161 {
1162         phys_size_t ram_top = ram_size;
1163
1164 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1165         ram_top = mc_get_dram_block_size();
1166         if (ram_top > ram_size)
1167                 return ram_size + ram_top;
1168
1169         ram_top = ram_size - ram_top;
1170         /* The start address of MC reserved memory needs to be aligned. */
1171         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1172 #endif
1173
1174         return ram_size - ram_top;
1175 }
1176
1177 phys_size_t get_effective_memsize(void)
1178 {
1179         phys_size_t ea_size, rem = 0;
1180
1181         /*
1182          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1183          * first region is 2GB space at 0x8000_0000. Secure memory needs to
1184          * allocated from first region. If the memory extends to  the second
1185          * region (or the third region if applicable), Management Complex (MC)
1186          * memory should be put into the highest region, i.e. the end of DDR
1187          * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1188          * U-Boot doesn't relocate itself into higher address. Should DDR be
1189          * configured to skip the first region, this function needs to be
1190          * adjusted.
1191          */
1192         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1193                 ea_size = CONFIG_MAX_MEM_MAPPED;
1194                 rem = gd->ram_size - ea_size;
1195         } else {
1196                 ea_size = gd->ram_size;
1197         }
1198
1199 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1200         /* Check if we have enough space for secure memory */
1201         if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1202                 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1203         else
1204                 printf("Error: No enough space for secure memory.\n");
1205 #endif
1206         /* Check if we have enough memory for MC */
1207         if (rem < board_reserve_ram_top(rem)) {
1208                 /* Not enough memory in high region to reserve */
1209                 if (ea_size > board_reserve_ram_top(ea_size))
1210                         ea_size -= board_reserve_ram_top(ea_size);
1211                 else
1212                         printf("Error: No enough space for reserved memory.\n");
1213         }
1214
1215         return ea_size;
1216 }
1217
1218 int dram_init_banksize(void)
1219 {
1220 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1221         phys_size_t dp_ddr_size;
1222 #endif
1223
1224         /*
1225          * gd->ram_size has the total size of DDR memory, less reserved secure
1226          * memory. The DDR extends from low region to high region(s) presuming
1227          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1228          * the location of secure memory. gd->arch.resv_ram tracks the location
1229          * of reserved memory for Management Complex (MC). Because gd->ram_size
1230          * is reduced by this function if secure memory is reserved, checking
1231          * gd->arch.secure_ram should be done to avoid running it repeatedly.
1232          */
1233
1234 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1235         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1236                 debug("No need to run again, skip %s\n", __func__);
1237
1238                 return 0;
1239         }
1240 #endif
1241
1242         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1243         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1244                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1245                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1246                 gd->bd->bi_dram[1].size = gd->ram_size -
1247                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
1248 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1249                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1250                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1251                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1252                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
1253                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1254                 }
1255 #endif
1256         } else {
1257                 gd->bd->bi_dram[0].size = gd->ram_size;
1258         }
1259 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1260         if (gd->bd->bi_dram[0].size >
1261                                 CONFIG_SYS_MEM_RESERVE_SECURE) {
1262                 gd->bd->bi_dram[0].size -=
1263                                 CONFIG_SYS_MEM_RESERVE_SECURE;
1264                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1265                                       gd->bd->bi_dram[0].size;
1266                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1267                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1268         }
1269 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
1270
1271 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1272         /* Assign memory for MC */
1273 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1274         if (gd->bd->bi_dram[2].size >=
1275             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1276                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1277                             gd->bd->bi_dram[2].size -
1278                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1279         } else
1280 #endif
1281         {
1282                 if (gd->bd->bi_dram[1].size >=
1283                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1284                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1285                                 gd->bd->bi_dram[1].size -
1286                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1287                 } else if (gd->bd->bi_dram[0].size >
1288                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1289                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1290                                 gd->bd->bi_dram[0].size -
1291                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1292                 }
1293         }
1294 #endif  /* CONFIG_FSL_MC_ENET */
1295
1296 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1297 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1298 #error "This SoC shouldn't have DP DDR"
1299 #endif
1300         if (soc_has_dp_ddr()) {
1301                 /* initialize DP-DDR here */
1302                 puts("DP-DDR:  ");
1303                 /*
1304                  * DDR controller use 0 as the base address for binding.
1305                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1306                  */
1307                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1308                                           CONFIG_DP_DDR_CTRL,
1309                                           CONFIG_DP_DDR_NUM_CTRLS,
1310                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1311                                           NULL, NULL, NULL);
1312                 if (dp_ddr_size) {
1313                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1314                         gd->bd->bi_dram[2].size = dp_ddr_size;
1315                 } else {
1316                         puts("Not detected");
1317                 }
1318         }
1319 #endif
1320
1321 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1322         debug("%s is called. gd->ram_size is reduced to %lu\n",
1323               __func__, (ulong)gd->ram_size);
1324 #endif
1325
1326         return 0;
1327 }
1328
1329 #if CONFIG_IS_ENABLED(EFI_LOADER)
1330 void efi_add_known_memory(void)
1331 {
1332         int i;
1333         phys_addr_t ram_start, start;
1334         phys_size_t ram_size;
1335         u64 pages;
1336
1337         /* Add RAM */
1338         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1339 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1340 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1341 #error "This SoC shouldn't have DP DDR"
1342 #endif
1343                 if (i == 2)
1344                         continue;       /* skip DP-DDR */
1345 #endif
1346                 ram_start = gd->bd->bi_dram[i].start;
1347                 ram_size = gd->bd->bi_dram[i].size;
1348 #ifdef CONFIG_RESV_RAM
1349                 if (gd->arch.resv_ram >= ram_start &&
1350                     gd->arch.resv_ram < ram_start + ram_size)
1351                         ram_size = gd->arch.resv_ram - ram_start;
1352 #endif
1353                 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1354                 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1355
1356                 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1357                                    false);
1358         }
1359 }
1360 #endif
1361
1362 /*
1363  * Before DDR size is known, early MMU table have DDR mapped as device memory
1364  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1365  * needs to be set for these mappings.
1366  * If a special case configures DDR with holes in the mapping, the holes need
1367  * to be marked as invalid. This is not implemented in this function.
1368  */
1369 void update_early_mmu_table(void)
1370 {
1371         if (!gd->arch.tlb_addr)
1372                 return;
1373
1374         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1375                 mmu_change_region_attr(
1376                                         CONFIG_SYS_SDRAM_BASE,
1377                                         gd->ram_size,
1378                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1379                                         PTE_BLOCK_OUTER_SHARE           |
1380                                         PTE_BLOCK_NS                    |
1381                                         PTE_TYPE_VALID);
1382         } else {
1383                 mmu_change_region_attr(
1384                                         CONFIG_SYS_SDRAM_BASE,
1385                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1386                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1387                                         PTE_BLOCK_OUTER_SHARE           |
1388                                         PTE_BLOCK_NS                    |
1389                                         PTE_TYPE_VALID);
1390 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1391 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1392 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1393 #endif
1394                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1395                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
1396                         mmu_change_region_attr(
1397                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1398                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1399                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1400                                         PTE_BLOCK_OUTER_SHARE           |
1401                                         PTE_BLOCK_NS                    |
1402                                         PTE_TYPE_VALID);
1403                         mmu_change_region_attr(
1404                                         CONFIG_SYS_DDR_BLOCK3_BASE,
1405                                         gd->ram_size -
1406                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
1407                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1408                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1409                                         PTE_BLOCK_OUTER_SHARE           |
1410                                         PTE_BLOCK_NS                    |
1411                                         PTE_TYPE_VALID);
1412                 } else
1413 #endif
1414                 {
1415                         mmu_change_region_attr(
1416                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1417                                         gd->ram_size -
1418                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1419                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1420                                         PTE_BLOCK_OUTER_SHARE           |
1421                                         PTE_BLOCK_NS                    |
1422                                         PTE_TYPE_VALID);
1423                 }
1424         }
1425 }
1426
1427 __weak int dram_init(void)
1428 {
1429         fsl_initdram();
1430 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1431         defined(CONFIG_SPL_BUILD)
1432         /* This will break-before-make MMU for DDR */
1433         update_early_mmu_table();
1434 #endif
1435
1436         return 0;
1437 }