arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2021 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <clock_legacy.h>
   9 #include <cpu_func.h>
  10 #include <env.h>
  11 #include <init.h>
  12 #include <hang.h>
  13 #include <log.h>
  14 #include <net.h>
  15 #include <vsprintf.h>
  16 #include <asm/cache.h>
  17 #include <asm/global_data.h>
  18 #include <asm/io.h>
  19 #include <asm/ptrace.h>
  20 #include <linux/errno.h>
  21 #include <asm/system.h>
  22 #include <fm_eth.h>
  23 #include <asm/armv8/mmu.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/fsl_serdes.h>
  26 #include <asm/arch/soc.h>
  27 #include <asm/arch/cpu.h>
  28 #include <asm/arch/speed.h>
  29 #include <fsl_immap.h>
  30 #include <asm/arch/mp.h>
  31 #include <efi_loader.h>
  32 #include <fsl-mc/fsl_mc.h>
  33 #ifdef CONFIG_FSL_ESDHC
  34 #include <fsl_esdhc.h>
  35 #endif
  36 #include <asm/armv8/sec_firmware.h>
  37 #ifdef CONFIG_SYS_FSL_DDR
  38 #include <fsl_ddr_sdram.h>
  39 #include <fsl_ddr.h>
  40 #endif
  41 #include <asm/arch/clock.h>
  42 #include <hwconfig.h>
  43 #include <fsl_qbman.h>
  44
  45 #ifdef CONFIG_TFABOOT
  46 #include <env_internal.h>
  47 #ifdef CONFIG_CHAIN_OF_TRUST
  48 #include <fsl_validate.h>
  49 #endif
  50 #endif
  51 #include <linux/mii.h>
  52 #include <dm.h>
  53
  54 DECLARE_GLOBAL_DATA_PTR;
  55
  56 static struct cpu_type cpu_type_list[] = {
  57         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  58         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  59         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  60         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  61         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  62         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  63         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  64         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  65         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  66         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  67         CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
  68         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  69         CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
  70         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  71         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  72         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  73         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  74         CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
  75         CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
  76         CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
  77         CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
  78         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  79         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  80         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  81         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  82         CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
  83         CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
  84         CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
  85         CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
  86         CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
  87         CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
  88 };
  89
  90 #define EARLY_PGTABLE_SIZE 0x5000
  91 static struct mm_region early_map[] = {
  92 #ifdef CONFIG_FSL_LSCH3
  93         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  94           CONFIG_SYS_FSL_CCSR_SIZE,
  95           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  96           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  97         },
  98         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  99           SYS_FSL_OCRAM_SPACE_SIZE,
 100           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 101         },
 102         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 103           CONFIG_SYS_FSL_QSPI_SIZE1,
 104           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
 105 #ifdef CONFIG_FSL_IFC
 106         /* For IFC Region #1, only the first 4MB is cache-enabled */
 107         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
 108           CONFIG_SYS_FSL_IFC_SIZE1_1,
 109           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 110         },
 111         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 112           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 113           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 114           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 115         },
 116         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 117           CONFIG_SYS_FSL_IFC_SIZE1,
 118           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 119         },
 120 #endif
 121         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 122           CONFIG_SYS_FSL_DRAM_SIZE1,
 123 #if defined(CONFIG_TFABOOT) || \
 124         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 125           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 126 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 127           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 128 #endif
 129           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 130         },
 131 #ifdef CONFIG_FSL_IFC
 132         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 133         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 134           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 135           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 136         },
 137 #endif
 138         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 139           CONFIG_SYS_FSL_DCSR_SIZE,
 140           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 141           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 142         },
 143         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 144           CONFIG_SYS_FSL_DRAM_SIZE2,
 145           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 146           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 147         },
 148 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 149         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 150           CONFIG_SYS_FSL_DRAM_SIZE3,
 151           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 152           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 153         },
 154 #endif
 155 #elif defined(CONFIG_FSL_LSCH2)
 156         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 157           CONFIG_SYS_FSL_CCSR_SIZE,
 158           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 159           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 160         },
 161         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 162           SYS_FSL_OCRAM_SPACE_SIZE,
 163           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 164         },
 165         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 166           CONFIG_SYS_FSL_DCSR_SIZE,
 167           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 168           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 169         },
 170         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 171           CONFIG_SYS_FSL_QSPI_SIZE,
 172           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 173         },
 174 #ifdef CONFIG_FSL_IFC
 175         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 176           CONFIG_SYS_FSL_IFC_SIZE,
 177           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 178         },
 179 #endif
 180         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 181           CONFIG_SYS_FSL_DRAM_SIZE1,
 182 #if defined(CONFIG_TFABOOT) || \
 183         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 184           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 185 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 186           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 187 #endif
 188           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 189         },
 190         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 191           CONFIG_SYS_FSL_DRAM_SIZE2,
 192           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 193           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 194         },
 195 #endif
 196         {},     /* list terminator */
 197 };
 198
 199 static struct mm_region final_map[] = {
 200 #ifdef CONFIG_FSL_LSCH3
 201         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 202           CONFIG_SYS_FSL_CCSR_SIZE,
 203           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 204           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 205         },
 206         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 207           SYS_FSL_OCRAM_SPACE_SIZE,
 208           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 209         },
 210         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 211           CONFIG_SYS_FSL_DRAM_SIZE1,
 212           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 213           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 214         },
 215         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 216           CONFIG_SYS_FSL_QSPI_SIZE1,
 217           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 218           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 219         },
 220         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 221           CONFIG_SYS_FSL_QSPI_SIZE2,
 222           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 223           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 224         },
 225 #ifdef CONFIG_FSL_IFC
 226         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 227           CONFIG_SYS_FSL_IFC_SIZE2,
 228           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 229           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 230         },
 231 #endif
 232         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 233           CONFIG_SYS_FSL_DCSR_SIZE,
 234           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 235           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 236         },
 237         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 238           CONFIG_SYS_FSL_MC_SIZE,
 239           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 240           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 241         },
 242         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 243           CONFIG_SYS_FSL_NI_SIZE,
 244           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 245           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 246         },
 247         /* For QBMAN portal, only the first 64MB is cache-enabled */
 248         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 249           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 250           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 251           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 252         },
 253         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 254           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 255           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 256           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 257           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 258         },
 259         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 260           CONFIG_SYS_PCIE1_PHYS_SIZE,
 261           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 262           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 263         },
 264         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 265           CONFIG_SYS_PCIE2_PHYS_SIZE,
 266           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 267           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 268         },
 269 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 270         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 271           CONFIG_SYS_PCIE3_PHYS_SIZE,
 272           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 273           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 274         },
 275 #endif
 276 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 277         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 278           CONFIG_SYS_PCIE4_PHYS_SIZE,
 279           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 280           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 281         },
 282 #endif
 283 #ifdef SYS_PCIE5_PHYS_ADDR
 284         { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
 285           SYS_PCIE5_PHYS_SIZE,
 286           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 287           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 288         },
 289 #endif
 290 #ifdef SYS_PCIE6_PHYS_ADDR
 291         { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
 292           SYS_PCIE6_PHYS_SIZE,
 293           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 294           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 295         },
 296 #endif
 297         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 298           CONFIG_SYS_FSL_WRIOP1_SIZE,
 299           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 300           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 301         },
 302         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 303           CONFIG_SYS_FSL_AIOP1_SIZE,
 304           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 305           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 306         },
 307         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 308           CONFIG_SYS_FSL_PEBUF_SIZE,
 309           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 310           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 311         },
 312         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 313           CONFIG_SYS_FSL_DRAM_SIZE2,
 314           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 315           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 316         },
 317 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 318         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 319           CONFIG_SYS_FSL_DRAM_SIZE3,
 320           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 321           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 322         },
 323 #endif
 324 #elif defined(CONFIG_FSL_LSCH2)
 325         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 326           CONFIG_SYS_FSL_BOOTROM_SIZE,
 327           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 328           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 329         },
 330         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 331           CONFIG_SYS_FSL_CCSR_SIZE,
 332           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 333           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 334         },
 335         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 336           SYS_FSL_OCRAM_SPACE_SIZE,
 337           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 338         },
 339         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 340           CONFIG_SYS_FSL_DCSR_SIZE,
 341           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 342           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 343         },
 344         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 345           CONFIG_SYS_FSL_QSPI_SIZE,
 346           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 347           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 348         },
 349 #ifdef CONFIG_FSL_IFC
 350         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 351           CONFIG_SYS_FSL_IFC_SIZE,
 352           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 353         },
 354 #endif
 355         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 356           CONFIG_SYS_FSL_DRAM_SIZE1,
 357           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 358           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 359         },
 360         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 361           CONFIG_SYS_FSL_QBMAN_SIZE,
 362           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 363           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 364         },
 365         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 366           CONFIG_SYS_FSL_DRAM_SIZE2,
 367           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 368           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 369         },
 370         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 371           CONFIG_SYS_PCIE1_PHYS_SIZE,
 372           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 373           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 374         },
 375         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 376           CONFIG_SYS_PCIE2_PHYS_SIZE,
 377           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 378           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 379         },
 380 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 381         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 382           CONFIG_SYS_PCIE3_PHYS_SIZE,
 383           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 384           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 385         },
 386 #endif
 387         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 388           CONFIG_SYS_FSL_DRAM_SIZE3,
 389           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 390           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 391         },
 392 #endif
 393 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 394         {},     /* space holder for secure mem */
 395 #endif
 396         {},
 397 };
 398
 399 struct mm_region *mem_map = early_map;
 400
 401 void cpu_name(char *name)
 402 {
 403         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 404         unsigned int i, svr, ver;
 405
 406         svr = gur_in32(&gur->svr);
 407         ver = SVR_SOC_VER(svr);
 408
 409         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 410                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 411                         strcpy(name, cpu_type_list[i].name);
 412 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 413                         if (IS_C_PROCESSOR(svr))
 414                                 strcat(name, "C");
 415 #endif
 416
 417                         if (IS_E_PROCESSOR(svr))
 418                                 strcat(name, "E");
 419
 420                         sprintf(name + strlen(name), " Rev%d.%d",
 421                                 SVR_MAJ(svr), SVR_MIN(svr));
 422                         break;
 423                 }
 424
 425         if (i == ARRAY_SIZE(cpu_type_list))
 426                 strcpy(name, "unknown");
 427 }
 428
 429 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 430 /*
 431  * To start MMU before DDR is available, we create MMU table in SRAM.
 432  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 433  * levels of translation tables here to cover 40-bit address space.
 434  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 435  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 436  * Note, the debug print in cache_v8.c is not usable for debugging
 437  * these early MMU tables because UART is not yet available.
 438  */
 439 static inline void early_mmu_setup(void)
 440 {
 441         unsigned int el = current_el();
 442
 443         /* global data is already setup, no allocation yet */
 444         if (el == 3)
 445                 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 446         else
 447                 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 448         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 449         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 450
 451         /* Create early page tables */
 452         setup_pgtables();
 453
 454         /* point TTBR to the new table */
 455         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 456                           get_tcr(el, NULL, NULL) &
 457                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 458                           MEMORY_ATTRIBUTES);
 459
 460         set_sctlr(get_sctlr() | CR_M);
 461 }
 462
 463 static void fix_pcie_mmu_map(void)
 464 {
 465 #ifdef CONFIG_ARCH_LS2080A
 466         unsigned int i;
 467         u32 svr, ver;
 468         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 469
 470         svr = gur_in32(&gur->svr);
 471         ver = SVR_SOC_VER(svr);
 472
 473         /* Fix PCIE base and size for LS2088A */
 474         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 475             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 476             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 477                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 478                         switch (final_map[i].phys) {
 479                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 480                                 final_map[i].phys = 0x2000000000ULL;
 481                                 final_map[i].virt = 0x2000000000ULL;
 482                                 final_map[i].size = 0x800000000ULL;
 483                                 break;
 484                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 485                                 final_map[i].phys = 0x2800000000ULL;
 486                                 final_map[i].virt = 0x2800000000ULL;
 487                                 final_map[i].size = 0x800000000ULL;
 488                                 break;
 489 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 490                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 491                                 final_map[i].phys = 0x3000000000ULL;
 492                                 final_map[i].virt = 0x3000000000ULL;
 493                                 final_map[i].size = 0x800000000ULL;
 494                                 break;
 495 #endif
 496 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 497                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 498                                 final_map[i].phys = 0x3800000000ULL;
 499                                 final_map[i].virt = 0x3800000000ULL;
 500                                 final_map[i].size = 0x800000000ULL;
 501                                 break;
 502 #endif
 503                         default:
 504                                 break;
 505                         }
 506                 }
 507         }
 508 #endif
 509 }
 510
 511 /*
 512  * The final tables look similar to early tables, but different in detail.
 513  * These tables are in DRAM. Sub tables are added to enable cache for
 514  * QBMan and OCRAM.
 515  *
 516  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 517  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 518  */
 519 static inline void final_mmu_setup(void)
 520 {
 521         u64 tlb_addr_save = gd->arch.tlb_addr;
 522         unsigned int el = current_el();
 523         int index;
 524
 525         /* fix the final_map before filling in the block entries */
 526         fix_pcie_mmu_map();
 527
 528         mem_map = final_map;
 529
 530         /* Update mapping for DDR to actual size */
 531         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 532                 /*
 533                  * Find the entry for DDR mapping and update the address and
 534                  * size. Zero-sized mapping will be skipped when creating MMU
 535                  * table.
 536                  */
 537                 switch (final_map[index].virt) {
 538                 case CONFIG_SYS_FSL_DRAM_BASE1:
 539                         final_map[index].virt = gd->bd->bi_dram[0].start;
 540                         final_map[index].phys = gd->bd->bi_dram[0].start;
 541                         final_map[index].size = gd->bd->bi_dram[0].size;
 542                         break;
 543 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 544                 case CONFIG_SYS_FSL_DRAM_BASE2:
 545 #if (CONFIG_NR_DRAM_BANKS >= 2)
 546                         final_map[index].virt = gd->bd->bi_dram[1].start;
 547                         final_map[index].phys = gd->bd->bi_dram[1].start;
 548                         final_map[index].size = gd->bd->bi_dram[1].size;
 549 #else
 550                         final_map[index].size = 0;
 551 #endif
 552                 break;
 553 #endif
 554 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 555                 case CONFIG_SYS_FSL_DRAM_BASE3:
 556 #if (CONFIG_NR_DRAM_BANKS >= 3)
 557                         final_map[index].virt = gd->bd->bi_dram[2].start;
 558                         final_map[index].phys = gd->bd->bi_dram[2].start;
 559                         final_map[index].size = gd->bd->bi_dram[2].size;
 560 #else
 561                         final_map[index].size = 0;
 562 #endif
 563                 break;
 564 #endif
 565                 default:
 566                         break;
 567                 }
 568         }
 569
 570 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 571         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 572                 if (el == 3) {
 573                         /*
 574                          * Only use gd->arch.secure_ram if the address is
 575                          * recalculated. Align to 4KB for MMU table.
 576                          */
 577                         /* put page tables in secure ram */
 578                         index = ARRAY_SIZE(final_map) - 2;
 579                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 580                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 581                         final_map[index].phys = final_map[index].virt;
 582                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 583                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 584                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 585                         tlb_addr_save = gd->arch.tlb_addr;
 586                 } else {
 587                         /* Use allocated (board_f.c) memory for TLB */
 588                         tlb_addr_save = gd->arch.tlb_allocated;
 589                         gd->arch.tlb_addr = tlb_addr_save;
 590                 }
 591         }
 592 #endif
 593
 594         /* Reset the fill ptr */
 595         gd->arch.tlb_fillptr = tlb_addr_save;
 596
 597         /* Create normal system page tables */
 598         setup_pgtables();
 599
 600         /* Create emergency page tables */
 601         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 602         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 603         setup_pgtables();
 604         gd->arch.tlb_addr = tlb_addr_save;
 605
 606         /* Disable cache and MMU */
 607         dcache_disable();       /* TLBs are invalidated */
 608         invalidate_icache_all();
 609
 610         /* point TTBR to the new table */
 611         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 612                           MEMORY_ATTRIBUTES);
 613
 614         set_sctlr(get_sctlr() | CR_M);
 615 }
 616
 617 u64 get_page_table_size(void)
 618 {
 619         return 0x10000;
 620 }
 621
 622 int arch_cpu_init(void)
 623 {
 624         /*
 625          * This function is called before U-Boot relocates itself to speed up
 626          * on system running. It is not necessary to run if performance is not
 627          * critical. Skip if MMU is already enabled by SPL or other means.
 628          */
 629         if (get_sctlr() & CR_M)
 630                 return 0;
 631
 632         icache_enable();
 633         __asm_invalidate_dcache_all();
 634         __asm_invalidate_tlb_all();
 635         early_mmu_setup();
 636         set_sctlr(get_sctlr() | CR_C);
 637         return 0;
 638 }
 639
 640 void mmu_setup(void)
 641 {
 642         final_mmu_setup();
 643 }
 644
 645 /*
 646  * This function is called from common/board_r.c.
 647  * It recreates MMU table in main memory.
 648  */
 649 void enable_caches(void)
 650 {
 651         mmu_setup();
 652         __asm_invalidate_tlb_all();
 653         icache_enable();
 654         dcache_enable();
 655 }
 656 #endif  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 657
 658 #ifdef CONFIG_TFABOOT
 659 enum boot_src __get_boot_src(u32 porsr1)
 660 {
 661         enum boot_src src = BOOT_SOURCE_RESERVED;
 662         u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
 663 #if !defined(CONFIG_NXP_LSCH3_2)
 664         u32 val;
 665 #endif
 666         debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
 667
 668 #if defined(CONFIG_FSL_LSCH3)
 669 #if defined(CONFIG_NXP_LSCH3_2)
 670         switch (rcw_src) {
 671         case RCW_SRC_SDHC1_VAL:
 672                 src = BOOT_SOURCE_SD_MMC;
 673         break;
 674         case RCW_SRC_SDHC2_VAL:
 675                 src = BOOT_SOURCE_SD_MMC2;
 676         break;
 677         case RCW_SRC_I2C1_VAL:
 678                 src = BOOT_SOURCE_I2C1_EXTENDED;
 679         break;
 680         case RCW_SRC_FLEXSPI_NAND2K_VAL:
 681                 src = BOOT_SOURCE_XSPI_NAND;
 682         break;
 683         case RCW_SRC_FLEXSPI_NAND4K_VAL:
 684                 src = BOOT_SOURCE_XSPI_NAND;
 685         break;
 686         case RCW_SRC_RESERVED_1_VAL:
 687                 src = BOOT_SOURCE_RESERVED;
 688         break;
 689         case RCW_SRC_FLEXSPI_NOR_24B:
 690                 src = BOOT_SOURCE_XSPI_NOR;
 691         break;
 692         default:
 693                 src = BOOT_SOURCE_RESERVED;
 694         }
 695 #else
 696         val = rcw_src & RCW_SRC_TYPE_MASK;
 697         if (val == RCW_SRC_NOR_VAL) {
 698                 val = rcw_src & NOR_TYPE_MASK;
 699
 700                 switch (val) {
 701                 case NOR_16B_VAL:
 702                 case NOR_32B_VAL:
 703                         src = BOOT_SOURCE_IFC_NOR;
 704                 break;
 705                 default:
 706                         src = BOOT_SOURCE_RESERVED;
 707                 }
 708         } else {
 709                 /* RCW SRC Serial Flash */
 710                 val = rcw_src & RCW_SRC_SERIAL_MASK;
 711                 switch (val) {
 712                 case RCW_SRC_QSPI_VAL:
 713                 /* RCW SRC Serial NOR (QSPI) */
 714                         src = BOOT_SOURCE_QSPI_NOR;
 715                         break;
 716                 case RCW_SRC_SD_CARD_VAL:
 717                 /* RCW SRC SD Card */
 718                         src = BOOT_SOURCE_SD_MMC;
 719                         break;
 720                 case RCW_SRC_EMMC_VAL:
 721                 /* RCW SRC EMMC */
 722                         src = BOOT_SOURCE_SD_MMC;
 723                         break;
 724                 case RCW_SRC_I2C1_VAL:
 725                 /* RCW SRC I2C1 Extended */
 726                         src = BOOT_SOURCE_I2C1_EXTENDED;
 727                         break;
 728                 default:
 729                         src = BOOT_SOURCE_RESERVED;
 730                 }
 731         }
 732 #endif
 733 #elif defined(CONFIG_FSL_LSCH2)
 734         /* RCW SRC NAND */
 735         val = rcw_src & RCW_SRC_NAND_MASK;
 736         if (val == RCW_SRC_NAND_VAL) {
 737                 val = rcw_src & NAND_RESERVED_MASK;
 738                 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
 739                         src = BOOT_SOURCE_IFC_NAND;
 740
 741         } else {
 742                 /* RCW SRC NOR */
 743                 val = rcw_src & RCW_SRC_NOR_MASK;
 744                 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
 745                         src = BOOT_SOURCE_IFC_NOR;
 746                 } else {
 747                         switch (rcw_src) {
 748                         case QSPI_VAL1:
 749                         case QSPI_VAL2:
 750                                 src = BOOT_SOURCE_QSPI_NOR;
 751                                 break;
 752                         case SD_VAL:
 753                                 src = BOOT_SOURCE_SD_MMC;
 754                                 break;
 755                         default:
 756                                 src = BOOT_SOURCE_RESERVED;
 757                         }
 758                 }
 759         }
 760 #endif
 761
 762         if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
 763                 src = BOOT_SOURCE_QSPI_NOR;
 764
 765         debug("%s: src 0x%x\n", __func__, src);
 766         return src;
 767 }
 768
 769 enum boot_src get_boot_src(void)
 770 {
 771         struct pt_regs regs;
 772         u32 porsr1 = 0;
 773
 774 #if defined(CONFIG_FSL_LSCH3)
 775         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 776 #elif defined(CONFIG_FSL_LSCH2)
 777         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 778 #endif
 779
 780         if (current_el() == 2) {
 781                 regs.regs[0] = SIP_SVC_RCW;
 782
 783                 smc_call(&regs);
 784                 if (!regs.regs[0])
 785                         porsr1 = regs.regs[1];
 786         }
 787
 788         if (current_el() == 3 || !porsr1) {
 789 #ifdef CONFIG_FSL_LSCH3
 790                 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 791 #elif defined(CONFIG_FSL_LSCH2)
 792                 porsr1 = in_be32(&gur->porsr1);
 793 #endif
 794         }
 795
 796         debug("%s: porsr1 0x%x\n", __func__, porsr1);
 797
 798         return __get_boot_src(porsr1);
 799 }
 800
 801 #ifdef CONFIG_ENV_IS_IN_MMC
 802 int mmc_get_env_dev(void)
 803 {
 804         enum boot_src src = get_boot_src();
 805         int dev = CONFIG_SYS_MMC_ENV_DEV;
 806
 807         switch (src) {
 808         case BOOT_SOURCE_SD_MMC:
 809                 dev = 0;
 810                 break;
 811         case BOOT_SOURCE_SD_MMC2:
 812                 dev = 1;
 813                 break;
 814         default:
 815                 break;
 816         }
 817
 818         return dev;
 819 }
 820 #endif
 821
 822 enum env_location env_get_location(enum env_operation op, int prio)
 823 {
 824         enum boot_src src = get_boot_src();
 825         enum env_location env_loc = ENVL_NOWHERE;
 826
 827         if (prio)
 828                 return ENVL_UNKNOWN;
 829
 830 #ifdef  CONFIG_ENV_IS_NOWHERE
 831         return env_loc;
 832 #endif
 833
 834         switch (src) {
 835         case BOOT_SOURCE_IFC_NOR:
 836                 env_loc = ENVL_FLASH;
 837                 break;
 838         case BOOT_SOURCE_QSPI_NOR:
 839                 /* FALLTHROUGH */
 840         case BOOT_SOURCE_XSPI_NOR:
 841                 env_loc = ENVL_SPI_FLASH;
 842                 break;
 843         case BOOT_SOURCE_IFC_NAND:
 844                 /* FALLTHROUGH */
 845         case BOOT_SOURCE_QSPI_NAND:
 846                 /* FALLTHROUGH */
 847         case BOOT_SOURCE_XSPI_NAND:
 848                 env_loc = ENVL_NAND;
 849                 break;
 850         case BOOT_SOURCE_SD_MMC:
 851                 /* FALLTHROUGH */
 852         case BOOT_SOURCE_SD_MMC2:
 853                 env_loc =  ENVL_MMC;
 854                 break;
 855         case BOOT_SOURCE_I2C1_EXTENDED:
 856                 /* FALLTHROUGH */
 857         default:
 858                 break;
 859         }
 860
 861         return env_loc;
 862 }
 863 #endif  /* CONFIG_TFABOOT */
 864
 865 u32 initiator_type(u32 cluster, int init_id)
 866 {
 867         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 868         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 869         u32 type = 0;
 870
 871         type = gur_in32(&gur->tp_ityp[idx]);
 872         if (type & TP_ITYP_AV)
 873                 return type;
 874
 875         return 0;
 876 }
 877
 878 u32 cpu_pos_mask(void)
 879 {
 880         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 881         int i = 0;
 882         u32 cluster, type, mask = 0;
 883
 884         do {
 885                 int j;
 886
 887                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 888                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 889                         type = initiator_type(cluster, j);
 890                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 891                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 892                 }
 893                 i++;
 894         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 895
 896         return mask;
 897 }
 898
 899 u32 cpu_mask(void)
 900 {
 901         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 902         int i = 0, count = 0;
 903         u32 cluster, type, mask = 0;
 904
 905         do {
 906                 int j;
 907
 908                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 909                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 910                         type = initiator_type(cluster, j);
 911                         if (type) {
 912                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 913                                         mask |= 1 << count;
 914                                 count++;
 915                         }
 916                 }
 917                 i++;
 918         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 919
 920         return mask;
 921 }
 922
 923 /*
 924  * Return the number of cores on this SOC.
 925  */
 926 int cpu_numcores(void)
 927 {
 928         return hweight32(cpu_mask());
 929 }
 930
 931 int fsl_qoriq_core_to_cluster(unsigned int core)
 932 {
 933         struct ccsr_gur __iomem *gur =
 934                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 935         int i = 0, count = 0;
 936         u32 cluster;
 937
 938         do {
 939                 int j;
 940
 941                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 942                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 943                         if (initiator_type(cluster, j)) {
 944                                 if (count == core)
 945                                         return i;
 946                                 count++;
 947                         }
 948                 }
 949                 i++;
 950         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 951
 952         return -1;      /* cannot identify the cluster */
 953 }
 954
 955 u32 fsl_qoriq_core_to_type(unsigned int core)
 956 {
 957         struct ccsr_gur __iomem *gur =
 958                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 959         int i = 0, count = 0;
 960         u32 cluster, type;
 961
 962         do {
 963                 int j;
 964
 965                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 966                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 967                         type = initiator_type(cluster, j);
 968                         if (type) {
 969                                 if (count == core)
 970                                         return type;
 971                                 count++;
 972                         }
 973                 }
 974                 i++;
 975         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 976
 977         return -1;      /* cannot identify the cluster */
 978 }
 979
 980 #ifndef CONFIG_FSL_LSCH3
 981 uint get_svr(void)
 982 {
 983         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 984
 985         return gur_in32(&gur->svr);
 986 }
 987 #endif
 988
 989 #ifdef CONFIG_DISPLAY_CPUINFO
 990 int print_cpuinfo(void)
 991 {
 992         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 993         struct sys_info sysinfo;
 994         char buf[32];
 995         unsigned int i, core;
 996         u32 type, rcw, svr = gur_in32(&gur->svr);
 997
 998         puts("SoC: ");
 999
1000         cpu_name(buf);
1001         printf(" %s (0x%x)\n", buf, svr);
1002         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
1003         get_sys_info(&sysinfo);
1004         puts("Clock Configuration:");
1005         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
1006                 if (!(i % 3))
1007                         puts("\n       ");
1008                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
1009                 printf("CPU%d(%s):%-4s MHz  ", core,
1010                        type == TY_ITYP_VER_A7 ? "A7 " :
1011                        (type == TY_ITYP_VER_A53 ? "A53" :
1012                        (type == TY_ITYP_VER_A57 ? "A57" :
1013                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
1014                        strmhz(buf, sysinfo.freq_processor[core]));
1015         }
1016         /* Display platform clock as Bus frequency. */
1017         printf("\n       Bus:      %-4s MHz  ",
1018                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1019         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1020 #ifdef CONFIG_SYS_DPAA_FMAN
1021         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1022 #endif
1023 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1024         if (soc_has_dp_ddr()) {
1025                 printf("     DP-DDR:   %-4s MT/s",
1026                        strmhz(buf, sysinfo.freq_ddrbus2));
1027         }
1028 #endif
1029         puts("\n");
1030
1031         /*
1032          * Display the RCW, so that no one gets confused as to what RCW
1033          * we're actually using for this boot.
1034          */
1035         puts("Reset Configuration Word (RCW):");
1036         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1037                 rcw = gur_in32(&gur->rcwsr[i]);
1038                 if ((i % 4) == 0)
1039                         printf("\n       %08x:", i * 4);
1040                 printf(" %08x", rcw);
1041         }
1042         puts("\n");
1043
1044         return 0;
1045 }
1046 #endif
1047
1048 #ifdef CONFIG_FSL_ESDHC
1049 int cpu_mmc_init(struct bd_info *bis)
1050 {
1051         return fsl_esdhc_mmc_init(bis);
1052 }
1053 #endif
1054
1055 int cpu_eth_init(struct bd_info *bis)
1056 {
1057         int error = 0;
1058
1059 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1060         error = fsl_mc_ldpaa_init(bis);
1061 #endif
1062 #ifdef CONFIG_FMAN_ENET
1063         fm_standard_init(bis);
1064 #endif
1065         return error;
1066 }
1067
1068 int check_psci(void)
1069 {
1070         unsigned int psci_ver;
1071
1072         psci_ver = sec_firmware_support_psci_version();
1073         if (psci_ver == PSCI_INVALID_VER)
1074                 return 1;
1075
1076         return 0;
1077 }
1078
1079 static void config_core_prefetch(void)
1080 {
1081         char *buf = NULL;
1082         char buffer[HWCONFIG_BUFFER_SIZE];
1083         const char *prefetch_arg = NULL;
1084         size_t arglen;
1085         unsigned int mask;
1086         struct pt_regs regs;
1087
1088         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1089                 buf = buffer;
1090         else
1091                 return;
1092
1093         prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1094                                          &arglen, buf);
1095
1096         if (prefetch_arg) {
1097                 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1098                 if (mask & 0x1) {
1099                         printf("Core0 prefetch can't be disabled\n");
1100                         return;
1101                 }
1102
1103 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1104                 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1105                 regs.regs[1] = mask;
1106                 smc_call(&regs);
1107
1108                 if (regs.regs[0])
1109                         printf("Prefetch disable config failed for mask ");
1110                 else
1111                         printf("Prefetch disable config passed for mask ");
1112                 printf("0x%x\n", mask);
1113         }
1114 }
1115
1116 #ifdef CONFIG_PCIE_ECAM_GENERIC
1117 __weak void set_ecam_icids(void)
1118 {
1119 }
1120 #endif
1121
1122 int arch_early_init_r(void)
1123 {
1124 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1125         u32 svr_dev_id;
1126         /*
1127          * erratum A009635 is valid only for LS2080A SoC and
1128          * its personalitiesi
1129          */
1130         svr_dev_id = get_svr();
1131         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1132                 erratum_a009635();
1133 #endif
1134 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1135         erratum_a009942_check_cpo();
1136 #endif
1137         if (check_psci()) {
1138                 debug("PSCI: PSCI does not exist.\n");
1139
1140                 /* if PSCI does not exist, boot secondary cores here */
1141                 if (fsl_layerscape_wake_seconday_cores())
1142                         printf("Did not wake secondary cores\n");
1143         }
1144
1145         config_core_prefetch();
1146
1147 #ifdef CONFIG_SYS_HAS_SERDES
1148         fsl_serdes_init();
1149 #endif
1150 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1151         /* some dpmacs in armv8a based freescale layerscape SOCs can be
1152          * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
1153          * EC*_PMUX(rgmii) bits in RCW.
1154          * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1155          * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1156          * Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes
1157          * precedence over SerDes protocol. i.e. in LX2160A if we select serdes
1158          * protocol that configures dpmac17 as SGMII and set the EC1_PMUX as
1159          * RGMII, then the dpmac is RGMII and not SGMII.
1160          *
1161          * Therefore, even thought fsl_rgmii_init is after fsl_serdes_init
1162          * function of SOC, the dpmac will be enabled as RGMII even if it was
1163          * also enabled before as SGMII. If ECx_PMUX is not configured for
1164          * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
1165          */
1166         fsl_rgmii_init();
1167 #endif
1168 #ifdef CONFIG_FMAN_ENET
1169 #ifndef CONFIG_DM_ETH
1170         fman_enet_init();
1171 #endif
1172 #endif
1173 #ifdef CONFIG_SYS_DPAA_QBMAN
1174         setup_qbman_portals();
1175 #endif
1176 #ifdef CONFIG_PCIE_ECAM_GENERIC
1177         set_ecam_icids();
1178 #endif
1179         return 0;
1180 }
1181
1182 int timer_init(void)
1183 {
1184         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1185 #ifdef CONFIG_FSL_LSCH3
1186         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1187 #endif
1188 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1189         defined(CONFIG_ARCH_LS1028A)
1190         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1191         u32 svr_dev_id;
1192 #endif
1193 #ifdef COUNTER_FREQUENCY_REAL
1194         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1195
1196         /* Update with accurate clock frequency */
1197         if (current_el() == 3)
1198                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1199 #endif
1200
1201 #ifdef CONFIG_FSL_LSCH3
1202         /* Enable timebase for all clusters.
1203          * It is safe to do so even some clusters are not enabled.
1204          */
1205         out_le32(cltbenr, 0xf);
1206 #endif
1207
1208 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1209         defined(CONFIG_ARCH_LS1028A)
1210         /*
1211          * In certain Layerscape SoCs, the clock for each core's
1212          * has an enable bit in the PMU Physical Core Time Base Enable
1213          * Register (PCTBENR), which allows the watchdog to operate.
1214          */
1215         setbits_le32(pctbenr, 0xff);
1216         /*
1217          * For LS2080A SoC and its personalities, timer controller
1218          * offset is different
1219          */
1220         svr_dev_id = get_svr();
1221         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1222                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1223
1224 #endif
1225
1226         /* Enable clock for timer
1227          * This is a global setting.
1228          */
1229         out_le32(cntcr, 0x1);
1230
1231         return 0;
1232 }
1233
1234 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1235
1236 void __efi_runtime reset_cpu(void)
1237 {
1238 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
1239         /* clear the RST_REQ_MSK and SW_RST_REQ */
1240         out_le32(rstcr, 0x0);
1241
1242         /* initiate the sw reset request */
1243         out_le32(rstcr, 0x1);
1244 #else
1245         u32 val;
1246
1247         /* Raise RESET_REQ_B */
1248         val = scfg_in32(rstcr);
1249         val |= 0x02;
1250         scfg_out32(rstcr, val);
1251 #endif
1252 }
1253
1254 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1255
1256 void __efi_runtime EFIAPI efi_reset_system(
1257                        enum efi_reset_type reset_type,
1258                        efi_status_t reset_status,
1259                        unsigned long data_size, void *reset_data)
1260 {
1261         switch (reset_type) {
1262         case EFI_RESET_COLD:
1263         case EFI_RESET_WARM:
1264         case EFI_RESET_PLATFORM_SPECIFIC:
1265                 reset_cpu();
1266                 break;
1267         case EFI_RESET_SHUTDOWN:
1268                 /* Nothing we can do */
1269                 break;
1270         }
1271
1272         while (1) { }
1273 }
1274
1275 efi_status_t efi_reset_system_init(void)
1276 {
1277         return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1278 }
1279
1280 #endif
1281
1282 /*
1283  * Calculate reserved memory with given memory bank
1284  * Return aligned memory size on success
1285  * Return (ram_size + needed size) for failure
1286  */
1287 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1288 {
1289         phys_size_t ram_top = ram_size;
1290
1291 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1292         ram_top = mc_get_dram_block_size();
1293         if (ram_top > ram_size)
1294                 return ram_size + ram_top;
1295
1296         ram_top = ram_size - ram_top;
1297         /* The start address of MC reserved memory needs to be aligned. */
1298         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1299 #endif
1300
1301         return ram_size - ram_top;
1302 }
1303
1304 phys_size_t get_effective_memsize(void)
1305 {
1306         phys_size_t ea_size, rem = 0;
1307
1308         /*
1309          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1310          * first region is 2GB space at 0x8000_0000. Secure memory needs to
1311          * allocated from first region. If the memory extends to  the second
1312          * region (or the third region if applicable), Management Complex (MC)
1313          * memory should be put into the highest region, i.e. the end of DDR
1314          * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1315          * U-Boot doesn't relocate itself into higher address. Should DDR be
1316          * configured to skip the first region, this function needs to be
1317          * adjusted.
1318          */
1319         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1320                 ea_size = CONFIG_MAX_MEM_MAPPED;
1321                 rem = gd->ram_size - ea_size;
1322         } else {
1323                 ea_size = gd->ram_size;
1324         }
1325
1326 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1327         /* Check if we have enough space for secure memory */
1328         if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1329                 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1330         else
1331                 printf("Error: No enough space for secure memory.\n");
1332 #endif
1333         /* Check if we have enough memory for MC */
1334         if (rem < board_reserve_ram_top(rem)) {
1335                 /* Not enough memory in high region to reserve */
1336                 if (ea_size > board_reserve_ram_top(ea_size))
1337                         ea_size -= board_reserve_ram_top(ea_size);
1338                 else
1339                         printf("Error: No enough space for reserved memory.\n");
1340         }
1341
1342         return ea_size;
1343 }
1344
1345 #ifdef CONFIG_TFABOOT
1346 phys_size_t tfa_get_dram_size(void)
1347 {
1348         struct pt_regs regs;
1349         phys_size_t dram_size = 0;
1350
1351         regs.regs[0] = SMC_DRAM_BANK_INFO;
1352         regs.regs[1] = -1;
1353
1354         smc_call(&regs);
1355         if (regs.regs[0])
1356                 return 0;
1357
1358         dram_size = regs.regs[1];
1359         return dram_size;
1360 }
1361
1362 static int tfa_dram_init_banksize(void)
1363 {
1364         int i = 0, ret = 0;
1365         struct pt_regs regs;
1366         phys_size_t dram_size = tfa_get_dram_size();
1367
1368         debug("dram_size %llx\n", dram_size);
1369
1370         if (!dram_size)
1371                 return -EINVAL;
1372
1373         do {
1374                 regs.regs[0] = SMC_DRAM_BANK_INFO;
1375                 regs.regs[1] = i;
1376
1377                 smc_call(&regs);
1378                 if (regs.regs[0]) {
1379                         ret = -EINVAL;
1380                         break;
1381                 }
1382
1383                 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1384                       regs.regs[2]);
1385                 gd->bd->bi_dram[i].start = regs.regs[1];
1386                 gd->bd->bi_dram[i].size = regs.regs[2];
1387
1388                 dram_size -= gd->bd->bi_dram[i].size;
1389
1390                 i++;
1391         } while (dram_size);
1392
1393         if (i > 0)
1394                 ret = 0;
1395
1396 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1397         /* Assign memory for MC */
1398 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1399         if (gd->bd->bi_dram[2].size >=
1400             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1401                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1402                             gd->bd->bi_dram[2].size -
1403                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1404         } else
1405 #endif
1406         {
1407                 if (gd->bd->bi_dram[1].size >=
1408                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1409                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1410                                 gd->bd->bi_dram[1].size -
1411                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1412                 } else if (gd->bd->bi_dram[0].size >
1413                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1414                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1415                                 gd->bd->bi_dram[0].size -
1416                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1417                 }
1418         }
1419 #endif  /* CONFIG_RESV_RAM */
1420
1421         return ret;
1422 }
1423 #endif
1424
1425 int dram_init_banksize(void)
1426 {
1427 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1428         phys_size_t dp_ddr_size;
1429 #endif
1430
1431 #ifdef CONFIG_TFABOOT
1432         if (!tfa_dram_init_banksize())
1433                 return 0;
1434 #endif
1435         /*
1436          * gd->ram_size has the total size of DDR memory, less reserved secure
1437          * memory. The DDR extends from low region to high region(s) presuming
1438          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1439          * the location of secure memory. gd->arch.resv_ram tracks the location
1440          * of reserved memory for Management Complex (MC). Because gd->ram_size
1441          * is reduced by this function if secure memory is reserved, checking
1442          * gd->arch.secure_ram should be done to avoid running it repeatedly.
1443          */
1444
1445 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1446         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1447                 debug("No need to run again, skip %s\n", __func__);
1448
1449                 return 0;
1450         }
1451 #endif
1452
1453         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1454         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1455                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1456                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1457                 gd->bd->bi_dram[1].size = gd->ram_size -
1458                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
1459 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1460                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1461                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1462                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1463                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
1464                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1465                 }
1466 #endif
1467         } else {
1468                 gd->bd->bi_dram[0].size = gd->ram_size;
1469         }
1470 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1471         if (gd->bd->bi_dram[0].size >
1472                                 CONFIG_SYS_MEM_RESERVE_SECURE) {
1473                 gd->bd->bi_dram[0].size -=
1474                                 CONFIG_SYS_MEM_RESERVE_SECURE;
1475                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1476                                       gd->bd->bi_dram[0].size;
1477                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1478                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1479         }
1480 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
1481
1482 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1483         /* Assign memory for MC */
1484 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1485         if (gd->bd->bi_dram[2].size >=
1486             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1487                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1488                             gd->bd->bi_dram[2].size -
1489                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1490         } else
1491 #endif
1492         {
1493                 if (gd->bd->bi_dram[1].size >=
1494                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1495                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1496                                 gd->bd->bi_dram[1].size -
1497                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1498                 } else if (gd->bd->bi_dram[0].size >
1499                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1500                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1501                                 gd->bd->bi_dram[0].size -
1502                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1503                 }
1504         }
1505 #endif  /* CONFIG_RESV_RAM */
1506
1507 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1508 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1509 #error "This SoC shouldn't have DP DDR"
1510 #endif
1511         if (soc_has_dp_ddr()) {
1512                 /* initialize DP-DDR here */
1513                 puts("DP-DDR:  ");
1514                 /*
1515                  * DDR controller use 0 as the base address for binding.
1516                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1517                  */
1518                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1519                                           CONFIG_DP_DDR_CTRL,
1520                                           CONFIG_DP_DDR_NUM_CTRLS,
1521                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1522                                           NULL, NULL, NULL);
1523                 if (dp_ddr_size) {
1524                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1525                         gd->bd->bi_dram[2].size = dp_ddr_size;
1526                 } else {
1527                         puts("Not detected");
1528                 }
1529         }
1530 #endif
1531
1532 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1533         debug("%s is called. gd->ram_size is reduced to %lu\n",
1534               __func__, (ulong)gd->ram_size);
1535 #endif
1536
1537         return 0;
1538 }
1539
1540 #if CONFIG_IS_ENABLED(EFI_LOADER)
1541 void efi_add_known_memory(void)
1542 {
1543         int i;
1544         phys_addr_t ram_start;
1545         phys_size_t ram_size;
1546
1547         /* Add RAM */
1548         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1549 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1550 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1551 #error "This SoC shouldn't have DP DDR"
1552 #endif
1553                 if (i == 2)
1554                         continue;       /* skip DP-DDR */
1555 #endif
1556                 ram_start = gd->bd->bi_dram[i].start;
1557                 ram_size = gd->bd->bi_dram[i].size;
1558 #ifdef CONFIG_RESV_RAM
1559                 if (gd->arch.resv_ram >= ram_start &&
1560                     gd->arch.resv_ram < ram_start + ram_size)
1561                         ram_size = gd->arch.resv_ram - ram_start;
1562 #endif
1563                 efi_add_memory_map(ram_start, ram_size,
1564                                    EFI_CONVENTIONAL_MEMORY);
1565         }
1566 }
1567 #endif
1568
1569 /*
1570  * Before DDR size is known, early MMU table have DDR mapped as device memory
1571  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1572  * needs to be set for these mappings.
1573  * If a special case configures DDR with holes in the mapping, the holes need
1574  * to be marked as invalid. This is not implemented in this function.
1575  */
1576 void update_early_mmu_table(void)
1577 {
1578         if (!gd->arch.tlb_addr)
1579                 return;
1580
1581         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1582                 mmu_change_region_attr(
1583                                         CONFIG_SYS_SDRAM_BASE,
1584                                         gd->ram_size,
1585                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1586                                         PTE_BLOCK_OUTER_SHARE           |
1587                                         PTE_BLOCK_NS                    |
1588                                         PTE_TYPE_VALID);
1589         } else {
1590                 mmu_change_region_attr(
1591                                         CONFIG_SYS_SDRAM_BASE,
1592                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1593                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1594                                         PTE_BLOCK_OUTER_SHARE           |
1595                                         PTE_BLOCK_NS                    |
1596                                         PTE_TYPE_VALID);
1597 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1598 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1599 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1600 #endif
1601                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1602                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
1603                         mmu_change_region_attr(
1604                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1605                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1606                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1607                                         PTE_BLOCK_OUTER_SHARE           |
1608                                         PTE_BLOCK_NS                    |
1609                                         PTE_TYPE_VALID);
1610                         mmu_change_region_attr(
1611                                         CONFIG_SYS_DDR_BLOCK3_BASE,
1612                                         gd->ram_size -
1613                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
1614                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1615                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1616                                         PTE_BLOCK_OUTER_SHARE           |
1617                                         PTE_BLOCK_NS                    |
1618                                         PTE_TYPE_VALID);
1619                 } else
1620 #endif
1621                 {
1622                         mmu_change_region_attr(
1623                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1624                                         gd->ram_size -
1625                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1626                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1627                                         PTE_BLOCK_OUTER_SHARE           |
1628                                         PTE_BLOCK_NS                    |
1629                                         PTE_TYPE_VALID);
1630                 }
1631         }
1632 }
1633
1634 __weak int dram_init(void)
1635 {
1636 #ifdef CONFIG_SYS_FSL_DDR
1637         fsl_initdram();
1638 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1639         defined(CONFIG_SPL_BUILD)
1640         /* This will break-before-make MMU for DDR */
1641         update_early_mmu_table();
1642 #endif
1643 #endif
1644
1645         return 0;
1646 }
1647
1648 #ifdef CONFIG_ARCH_MISC_INIT
1649 __weak int serdes_misc_init(void)
1650 {
1651         return 0;
1652 }
1653
1654 int arch_misc_init(void)
1655 {
1656         if (IS_ENABLED(CONFIG_FSL_CAAM)) {
1657                 struct udevice *dev;
1658                 int ret;
1659
1660                 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
1661                 if (ret)
1662                         printf("Failed to initialize %s: %d\n", dev->name, ret);
1663         }
1664         serdes_misc_init();
1665
1666         return 0;
1667 }
1668 #endif