arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2020 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <clock_legacy.h>
   9 #include <cpu_func.h>
  10 #include <env.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <init.h>
  13 #include <hang.h>
  14 #include <log.h>
  15 #include <net.h>
  16 #include <vsprintf.h>
  17 #include <asm/cache.h>
  18 #include <asm/global_data.h>
  19 #include <asm/io.h>
  20 #include <asm/ptrace.h>
  21 #include <linux/errno.h>
  22 #include <asm/system.h>
  23 #include <fm_eth.h>
  24 #include <asm/armv8/mmu.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/fsl_serdes.h>
  27 #include <asm/arch/soc.h>
  28 #include <asm/arch/cpu.h>
  29 #include <asm/arch/speed.h>
  30 #include <fsl_immap.h>
  31 #include <asm/arch/mp.h>
  32 #include <efi_loader.h>
  33 #include <fsl-mc/fsl_mc.h>
  34 #ifdef CONFIG_FSL_ESDHC
  35 #include <fsl_esdhc.h>
  36 #endif
  37 #include <asm/armv8/sec_firmware.h>
  38 #ifdef CONFIG_SYS_FSL_DDR
  39 #include <fsl_ddr.h>
  40 #endif
  41 #include <asm/arch/clock.h>
  42 #include <hwconfig.h>
  43 #include <fsl_qbman.h>
  44
  45 #ifdef CONFIG_TFABOOT
  46 #include <env_internal.h>
  47 #ifdef CONFIG_CHAIN_OF_TRUST
  48 #include <fsl_validate.h>
  49 #endif
  50 #endif
  51 #include <linux/mii.h>
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 static struct cpu_type cpu_type_list[] = {
  56         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  57         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  58         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  59         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  60         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  61         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  62         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  63         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  64         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  65         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  66         CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
  67         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  68         CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
  69         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  70         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  71         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  72         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  73         CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
  74         CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
  75         CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
  76         CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
  77         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  78         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  79         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  80         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  81         CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
  82         CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
  83         CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
  84         CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
  85         CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
  86         CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
  87 };
  88
  89 #define EARLY_PGTABLE_SIZE 0x5000
  90 static struct mm_region early_map[] = {
  91 #ifdef CONFIG_FSL_LSCH3
  92         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  93           CONFIG_SYS_FSL_CCSR_SIZE,
  94           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  95           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  96         },
  97         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  98           SYS_FSL_OCRAM_SPACE_SIZE,
  99           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 100         },
 101         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 102           CONFIG_SYS_FSL_QSPI_SIZE1,
 103           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
 104 #ifdef CONFIG_FSL_IFC
 105         /* For IFC Region #1, only the first 4MB is cache-enabled */
 106         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
 107           CONFIG_SYS_FSL_IFC_SIZE1_1,
 108           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 109         },
 110         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 111           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 112           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 113           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 114         },
 115         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 116           CONFIG_SYS_FSL_IFC_SIZE1,
 117           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 118         },
 119 #endif
 120         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 121           CONFIG_SYS_FSL_DRAM_SIZE1,
 122 #if defined(CONFIG_TFABOOT) || \
 123         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 124           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 125 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 126           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 127 #endif
 128           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 129         },
 130 #ifdef CONFIG_FSL_IFC
 131         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 132         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 133           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 134           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 135         },
 136 #endif
 137         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 138           CONFIG_SYS_FSL_DCSR_SIZE,
 139           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 140           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 141         },
 142         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 143           CONFIG_SYS_FSL_DRAM_SIZE2,
 144           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 145           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 146         },
 147 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 148         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 149           CONFIG_SYS_FSL_DRAM_SIZE3,
 150           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 151           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 152         },
 153 #endif
 154 #elif defined(CONFIG_FSL_LSCH2)
 155         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 156           CONFIG_SYS_FSL_CCSR_SIZE,
 157           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 158           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 159         },
 160         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 161           SYS_FSL_OCRAM_SPACE_SIZE,
 162           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 163         },
 164         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 165           CONFIG_SYS_FSL_DCSR_SIZE,
 166           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 167           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 168         },
 169         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 170           CONFIG_SYS_FSL_QSPI_SIZE,
 171           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 172         },
 173 #ifdef CONFIG_FSL_IFC
 174         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 175           CONFIG_SYS_FSL_IFC_SIZE,
 176           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 177         },
 178 #endif
 179         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 180           CONFIG_SYS_FSL_DRAM_SIZE1,
 181 #if defined(CONFIG_TFABOOT) || \
 182         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 183           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 184 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 185           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 186 #endif
 187           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 188         },
 189         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 190           CONFIG_SYS_FSL_DRAM_SIZE2,
 191           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 192           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 193         },
 194 #endif
 195         {},     /* list terminator */
 196 };
 197
 198 static struct mm_region final_map[] = {
 199 #ifdef CONFIG_FSL_LSCH3
 200         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 201           CONFIG_SYS_FSL_CCSR_SIZE,
 202           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 203           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 204         },
 205         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 206           SYS_FSL_OCRAM_SPACE_SIZE,
 207           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 208         },
 209         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 210           CONFIG_SYS_FSL_DRAM_SIZE1,
 211           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 212           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 213         },
 214         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 215           CONFIG_SYS_FSL_QSPI_SIZE1,
 216           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 217           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 218         },
 219         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 220           CONFIG_SYS_FSL_QSPI_SIZE2,
 221           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 222           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 223         },
 224 #ifdef CONFIG_FSL_IFC
 225         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 226           CONFIG_SYS_FSL_IFC_SIZE2,
 227           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 228           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 229         },
 230 #endif
 231         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 232           CONFIG_SYS_FSL_DCSR_SIZE,
 233           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 234           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 235         },
 236         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 237           CONFIG_SYS_FSL_MC_SIZE,
 238           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 239           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 240         },
 241         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 242           CONFIG_SYS_FSL_NI_SIZE,
 243           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 244           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 245         },
 246         /* For QBMAN portal, only the first 64MB is cache-enabled */
 247         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 248           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 249           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 250           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 251         },
 252         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 253           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 254           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 255           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 256           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 257         },
 258         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 259           CONFIG_SYS_PCIE1_PHYS_SIZE,
 260           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 261           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 262         },
 263         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 264           CONFIG_SYS_PCIE2_PHYS_SIZE,
 265           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 266           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 267         },
 268 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 269         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 270           CONFIG_SYS_PCIE3_PHYS_SIZE,
 271           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 272           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 273         },
 274 #endif
 275 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 276         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 277           CONFIG_SYS_PCIE4_PHYS_SIZE,
 278           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 279           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 280         },
 281 #endif
 282 #ifdef SYS_PCIE5_PHYS_ADDR
 283         { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
 284           SYS_PCIE5_PHYS_SIZE,
 285           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 286           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 287         },
 288 #endif
 289 #ifdef SYS_PCIE6_PHYS_ADDR
 290         { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
 291           SYS_PCIE6_PHYS_SIZE,
 292           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 293           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 294         },
 295 #endif
 296         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 297           CONFIG_SYS_FSL_WRIOP1_SIZE,
 298           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 299           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 300         },
 301         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 302           CONFIG_SYS_FSL_AIOP1_SIZE,
 303           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 304           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 305         },
 306         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 307           CONFIG_SYS_FSL_PEBUF_SIZE,
 308           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 309           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 310         },
 311         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 312           CONFIG_SYS_FSL_DRAM_SIZE2,
 313           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 314           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 315         },
 316 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 317         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 318           CONFIG_SYS_FSL_DRAM_SIZE3,
 319           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 320           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 321         },
 322 #endif
 323 #elif defined(CONFIG_FSL_LSCH2)
 324         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 325           CONFIG_SYS_FSL_BOOTROM_SIZE,
 326           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 327           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 328         },
 329         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 330           CONFIG_SYS_FSL_CCSR_SIZE,
 331           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 332           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 333         },
 334         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 335           SYS_FSL_OCRAM_SPACE_SIZE,
 336           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 337         },
 338         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 339           CONFIG_SYS_FSL_DCSR_SIZE,
 340           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 341           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 342         },
 343         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 344           CONFIG_SYS_FSL_QSPI_SIZE,
 345           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 346           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 347         },
 348 #ifdef CONFIG_FSL_IFC
 349         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 350           CONFIG_SYS_FSL_IFC_SIZE,
 351           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 352         },
 353 #endif
 354         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 355           CONFIG_SYS_FSL_DRAM_SIZE1,
 356           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 357           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 358         },
 359         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 360           CONFIG_SYS_FSL_QBMAN_SIZE,
 361           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 362           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 363         },
 364         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 365           CONFIG_SYS_FSL_DRAM_SIZE2,
 366           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 367           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 368         },
 369         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 370           CONFIG_SYS_PCIE1_PHYS_SIZE,
 371           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 372           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 373         },
 374         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 375           CONFIG_SYS_PCIE2_PHYS_SIZE,
 376           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 377           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 378         },
 379 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 380         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 381           CONFIG_SYS_PCIE3_PHYS_SIZE,
 382           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 383           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 384         },
 385 #endif
 386         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 387           CONFIG_SYS_FSL_DRAM_SIZE3,
 388           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 389           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 390         },
 391 #endif
 392 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 393         {},     /* space holder for secure mem */
 394 #endif
 395         {},
 396 };
 397
 398 struct mm_region *mem_map = early_map;
 399
 400 void cpu_name(char *name)
 401 {
 402         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 403         unsigned int i, svr, ver;
 404
 405         svr = gur_in32(&gur->svr);
 406         ver = SVR_SOC_VER(svr);
 407
 408         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 409                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 410                         strcpy(name, cpu_type_list[i].name);
 411 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 412                         if (IS_C_PROCESSOR(svr))
 413                                 strcat(name, "C");
 414 #endif
 415
 416                         if (IS_E_PROCESSOR(svr))
 417                                 strcat(name, "E");
 418
 419                         sprintf(name + strlen(name), " Rev%d.%d",
 420                                 SVR_MAJ(svr), SVR_MIN(svr));
 421                         break;
 422                 }
 423
 424         if (i == ARRAY_SIZE(cpu_type_list))
 425                 strcpy(name, "unknown");
 426 }
 427
 428 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 429 /*
 430  * To start MMU before DDR is available, we create MMU table in SRAM.
 431  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 432  * levels of translation tables here to cover 40-bit address space.
 433  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 434  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 435  * Note, the debug print in cache_v8.c is not usable for debugging
 436  * these early MMU tables because UART is not yet available.
 437  */
 438 static inline void early_mmu_setup(void)
 439 {
 440         unsigned int el = current_el();
 441
 442         /* global data is already setup, no allocation yet */
 443         if (el == 3)
 444                 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 445         else
 446                 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 447         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 448         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 449
 450         /* Create early page tables */
 451         setup_pgtables();
 452
 453         /* point TTBR to the new table */
 454         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 455                           get_tcr(el, NULL, NULL) &
 456                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 457                           MEMORY_ATTRIBUTES);
 458
 459         set_sctlr(get_sctlr() | CR_M);
 460 }
 461
 462 static void fix_pcie_mmu_map(void)
 463 {
 464 #ifdef CONFIG_ARCH_LS2080A
 465         unsigned int i;
 466         u32 svr, ver;
 467         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 468
 469         svr = gur_in32(&gur->svr);
 470         ver = SVR_SOC_VER(svr);
 471
 472         /* Fix PCIE base and size for LS2088A */
 473         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 474             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 475             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 476                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 477                         switch (final_map[i].phys) {
 478                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 479                                 final_map[i].phys = 0x2000000000ULL;
 480                                 final_map[i].virt = 0x2000000000ULL;
 481                                 final_map[i].size = 0x800000000ULL;
 482                                 break;
 483                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 484                                 final_map[i].phys = 0x2800000000ULL;
 485                                 final_map[i].virt = 0x2800000000ULL;
 486                                 final_map[i].size = 0x800000000ULL;
 487                                 break;
 488 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 489                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 490                                 final_map[i].phys = 0x3000000000ULL;
 491                                 final_map[i].virt = 0x3000000000ULL;
 492                                 final_map[i].size = 0x800000000ULL;
 493                                 break;
 494 #endif
 495 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 496                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 497                                 final_map[i].phys = 0x3800000000ULL;
 498                                 final_map[i].virt = 0x3800000000ULL;
 499                                 final_map[i].size = 0x800000000ULL;
 500                                 break;
 501 #endif
 502                         default:
 503                                 break;
 504                         }
 505                 }
 506         }
 507 #endif
 508 }
 509
 510 /*
 511  * The final tables look similar to early tables, but different in detail.
 512  * These tables are in DRAM. Sub tables are added to enable cache for
 513  * QBMan and OCRAM.
 514  *
 515  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 516  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 517  */
 518 static inline void final_mmu_setup(void)
 519 {
 520         u64 tlb_addr_save = gd->arch.tlb_addr;
 521         unsigned int el = current_el();
 522         int index;
 523
 524         /* fix the final_map before filling in the block entries */
 525         fix_pcie_mmu_map();
 526
 527         mem_map = final_map;
 528
 529         /* Update mapping for DDR to actual size */
 530         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 531                 /*
 532                  * Find the entry for DDR mapping and update the address and
 533                  * size. Zero-sized mapping will be skipped when creating MMU
 534                  * table.
 535                  */
 536                 switch (final_map[index].virt) {
 537                 case CONFIG_SYS_FSL_DRAM_BASE1:
 538                         final_map[index].virt = gd->bd->bi_dram[0].start;
 539                         final_map[index].phys = gd->bd->bi_dram[0].start;
 540                         final_map[index].size = gd->bd->bi_dram[0].size;
 541                         break;
 542 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 543                 case CONFIG_SYS_FSL_DRAM_BASE2:
 544 #if (CONFIG_NR_DRAM_BANKS >= 2)
 545                         final_map[index].virt = gd->bd->bi_dram[1].start;
 546                         final_map[index].phys = gd->bd->bi_dram[1].start;
 547                         final_map[index].size = gd->bd->bi_dram[1].size;
 548 #else
 549                         final_map[index].size = 0;
 550 #endif
 551                 break;
 552 #endif
 553 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 554                 case CONFIG_SYS_FSL_DRAM_BASE3:
 555 #if (CONFIG_NR_DRAM_BANKS >= 3)
 556                         final_map[index].virt = gd->bd->bi_dram[2].start;
 557                         final_map[index].phys = gd->bd->bi_dram[2].start;
 558                         final_map[index].size = gd->bd->bi_dram[2].size;
 559 #else
 560                         final_map[index].size = 0;
 561 #endif
 562                 break;
 563 #endif
 564                 default:
 565                         break;
 566                 }
 567         }
 568
 569 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 570         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 571                 if (el == 3) {
 572                         /*
 573                          * Only use gd->arch.secure_ram if the address is
 574                          * recalculated. Align to 4KB for MMU table.
 575                          */
 576                         /* put page tables in secure ram */
 577                         index = ARRAY_SIZE(final_map) - 2;
 578                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 579                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 580                         final_map[index].phys = final_map[index].virt;
 581                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 582                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 583                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 584                         tlb_addr_save = gd->arch.tlb_addr;
 585                 } else {
 586                         /* Use allocated (board_f.c) memory for TLB */
 587                         tlb_addr_save = gd->arch.tlb_allocated;
 588                         gd->arch.tlb_addr = tlb_addr_save;
 589                 }
 590         }
 591 #endif
 592
 593         /* Reset the fill ptr */
 594         gd->arch.tlb_fillptr = tlb_addr_save;
 595
 596         /* Create normal system page tables */
 597         setup_pgtables();
 598
 599         /* Create emergency page tables */
 600         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 601         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 602         setup_pgtables();
 603         gd->arch.tlb_addr = tlb_addr_save;
 604
 605         /* Disable cache and MMU */
 606         dcache_disable();       /* TLBs are invalidated */
 607         invalidate_icache_all();
 608
 609         /* point TTBR to the new table */
 610         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 611                           MEMORY_ATTRIBUTES);
 612
 613         set_sctlr(get_sctlr() | CR_M);
 614 }
 615
 616 u64 get_page_table_size(void)
 617 {
 618         return 0x10000;
 619 }
 620
 621 int arch_cpu_init(void)
 622 {
 623         /*
 624          * This function is called before U-Boot relocates itself to speed up
 625          * on system running. It is not necessary to run if performance is not
 626          * critical. Skip if MMU is already enabled by SPL or other means.
 627          */
 628         if (get_sctlr() & CR_M)
 629                 return 0;
 630
 631         icache_enable();
 632         __asm_invalidate_dcache_all();
 633         __asm_invalidate_tlb_all();
 634         early_mmu_setup();
 635         set_sctlr(get_sctlr() | CR_C);
 636         return 0;
 637 }
 638
 639 void mmu_setup(void)
 640 {
 641         final_mmu_setup();
 642 }
 643
 644 /*
 645  * This function is called from common/board_r.c.
 646  * It recreates MMU table in main memory.
 647  */
 648 void enable_caches(void)
 649 {
 650         mmu_setup();
 651         __asm_invalidate_tlb_all();
 652         icache_enable();
 653         dcache_enable();
 654 }
 655 #endif  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 656
 657 #ifdef CONFIG_TFABOOT
 658 enum boot_src __get_boot_src(u32 porsr1)
 659 {
 660         enum boot_src src = BOOT_SOURCE_RESERVED;
 661         u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
 662 #if !defined(CONFIG_NXP_LSCH3_2)
 663         u32 val;
 664 #endif
 665         debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
 666
 667 #if defined(CONFIG_FSL_LSCH3)
 668 #if defined(CONFIG_NXP_LSCH3_2)
 669         switch (rcw_src) {
 670         case RCW_SRC_SDHC1_VAL:
 671                 src = BOOT_SOURCE_SD_MMC;
 672         break;
 673         case RCW_SRC_SDHC2_VAL:
 674                 src = BOOT_SOURCE_SD_MMC2;
 675         break;
 676         case RCW_SRC_I2C1_VAL:
 677                 src = BOOT_SOURCE_I2C1_EXTENDED;
 678         break;
 679         case RCW_SRC_FLEXSPI_NAND2K_VAL:
 680                 src = BOOT_SOURCE_XSPI_NAND;
 681         break;
 682         case RCW_SRC_FLEXSPI_NAND4K_VAL:
 683                 src = BOOT_SOURCE_XSPI_NAND;
 684         break;
 685         case RCW_SRC_RESERVED_1_VAL:
 686                 src = BOOT_SOURCE_RESERVED;
 687         break;
 688         case RCW_SRC_FLEXSPI_NOR_24B:
 689                 src = BOOT_SOURCE_XSPI_NOR;
 690         break;
 691         default:
 692                 src = BOOT_SOURCE_RESERVED;
 693         }
 694 #else
 695         val = rcw_src & RCW_SRC_TYPE_MASK;
 696         if (val == RCW_SRC_NOR_VAL) {
 697                 val = rcw_src & NOR_TYPE_MASK;
 698
 699                 switch (val) {
 700                 case NOR_16B_VAL:
 701                 case NOR_32B_VAL:
 702                         src = BOOT_SOURCE_IFC_NOR;
 703                 break;
 704                 default:
 705                         src = BOOT_SOURCE_RESERVED;
 706                 }
 707         } else {
 708                 /* RCW SRC Serial Flash */
 709                 val = rcw_src & RCW_SRC_SERIAL_MASK;
 710                 switch (val) {
 711                 case RCW_SRC_QSPI_VAL:
 712                 /* RCW SRC Serial NOR (QSPI) */
 713                         src = BOOT_SOURCE_QSPI_NOR;
 714                         break;
 715                 case RCW_SRC_SD_CARD_VAL:
 716                 /* RCW SRC SD Card */
 717                         src = BOOT_SOURCE_SD_MMC;
 718                         break;
 719                 case RCW_SRC_EMMC_VAL:
 720                 /* RCW SRC EMMC */
 721                         src = BOOT_SOURCE_SD_MMC;
 722                         break;
 723                 case RCW_SRC_I2C1_VAL:
 724                 /* RCW SRC I2C1 Extended */
 725                         src = BOOT_SOURCE_I2C1_EXTENDED;
 726                         break;
 727                 default:
 728                         src = BOOT_SOURCE_RESERVED;
 729                 }
 730         }
 731 #endif
 732 #elif defined(CONFIG_FSL_LSCH2)
 733         /* RCW SRC NAND */
 734         val = rcw_src & RCW_SRC_NAND_MASK;
 735         if (val == RCW_SRC_NAND_VAL) {
 736                 val = rcw_src & NAND_RESERVED_MASK;
 737                 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
 738                         src = BOOT_SOURCE_IFC_NAND;
 739
 740         } else {
 741                 /* RCW SRC NOR */
 742                 val = rcw_src & RCW_SRC_NOR_MASK;
 743                 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
 744                         src = BOOT_SOURCE_IFC_NOR;
 745                 } else {
 746                         switch (rcw_src) {
 747                         case QSPI_VAL1:
 748                         case QSPI_VAL2:
 749                                 src = BOOT_SOURCE_QSPI_NOR;
 750                                 break;
 751                         case SD_VAL:
 752                                 src = BOOT_SOURCE_SD_MMC;
 753                                 break;
 754                         default:
 755                                 src = BOOT_SOURCE_RESERVED;
 756                         }
 757                 }
 758         }
 759 #endif
 760
 761         if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
 762                 src = BOOT_SOURCE_QSPI_NOR;
 763
 764         debug("%s: src 0x%x\n", __func__, src);
 765         return src;
 766 }
 767
 768 enum boot_src get_boot_src(void)
 769 {
 770         struct pt_regs regs;
 771         u32 porsr1 = 0;
 772
 773 #if defined(CONFIG_FSL_LSCH3)
 774         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 775 #elif defined(CONFIG_FSL_LSCH2)
 776         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 777 #endif
 778
 779         if (current_el() == 2) {
 780                 regs.regs[0] = SIP_SVC_RCW;
 781
 782                 smc_call(&regs);
 783                 if (!regs.regs[0])
 784                         porsr1 = regs.regs[1];
 785         }
 786
 787         if (current_el() == 3 || !porsr1) {
 788 #ifdef CONFIG_FSL_LSCH3
 789                 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 790 #elif defined(CONFIG_FSL_LSCH2)
 791                 porsr1 = in_be32(&gur->porsr1);
 792 #endif
 793         }
 794
 795         debug("%s: porsr1 0x%x\n", __func__, porsr1);
 796
 797         return __get_boot_src(porsr1);
 798 }
 799
 800 #ifdef CONFIG_ENV_IS_IN_MMC
 801 int mmc_get_env_dev(void)
 802 {
 803         enum boot_src src = get_boot_src();
 804         int dev = CONFIG_SYS_MMC_ENV_DEV;
 805
 806         switch (src) {
 807         case BOOT_SOURCE_SD_MMC:
 808                 dev = 0;
 809                 break;
 810         case BOOT_SOURCE_SD_MMC2:
 811                 dev = 1;
 812                 break;
 813         default:
 814                 break;
 815         }
 816
 817         return dev;
 818 }
 819 #endif
 820
 821 enum env_location env_get_location(enum env_operation op, int prio)
 822 {
 823         enum boot_src src = get_boot_src();
 824         enum env_location env_loc = ENVL_NOWHERE;
 825
 826         if (prio)
 827                 return ENVL_UNKNOWN;
 828
 829 #ifdef  CONFIG_ENV_IS_NOWHERE
 830         return env_loc;
 831 #endif
 832
 833         switch (src) {
 834         case BOOT_SOURCE_IFC_NOR:
 835                 env_loc = ENVL_FLASH;
 836                 break;
 837         case BOOT_SOURCE_QSPI_NOR:
 838                 /* FALLTHROUGH */
 839         case BOOT_SOURCE_XSPI_NOR:
 840                 env_loc = ENVL_SPI_FLASH;
 841                 break;
 842         case BOOT_SOURCE_IFC_NAND:
 843                 /* FALLTHROUGH */
 844         case BOOT_SOURCE_QSPI_NAND:
 845                 /* FALLTHROUGH */
 846         case BOOT_SOURCE_XSPI_NAND:
 847                 env_loc = ENVL_NAND;
 848                 break;
 849         case BOOT_SOURCE_SD_MMC:
 850                 /* FALLTHROUGH */
 851         case BOOT_SOURCE_SD_MMC2:
 852                 env_loc =  ENVL_MMC;
 853                 break;
 854         case BOOT_SOURCE_I2C1_EXTENDED:
 855                 /* FALLTHROUGH */
 856         default:
 857                 break;
 858         }
 859
 860         return env_loc;
 861 }
 862 #endif  /* CONFIG_TFABOOT */
 863
 864 u32 initiator_type(u32 cluster, int init_id)
 865 {
 866         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 867         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 868         u32 type = 0;
 869
 870         type = gur_in32(&gur->tp_ityp[idx]);
 871         if (type & TP_ITYP_AV)
 872                 return type;
 873
 874         return 0;
 875 }
 876
 877 u32 cpu_pos_mask(void)
 878 {
 879         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 880         int i = 0;
 881         u32 cluster, type, mask = 0;
 882
 883         do {
 884                 int j;
 885
 886                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 887                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 888                         type = initiator_type(cluster, j);
 889                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 890                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 891                 }
 892                 i++;
 893         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 894
 895         return mask;
 896 }
 897
 898 u32 cpu_mask(void)
 899 {
 900         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 901         int i = 0, count = 0;
 902         u32 cluster, type, mask = 0;
 903
 904         do {
 905                 int j;
 906
 907                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 908                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 909                         type = initiator_type(cluster, j);
 910                         if (type) {
 911                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 912                                         mask |= 1 << count;
 913                                 count++;
 914                         }
 915                 }
 916                 i++;
 917         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 918
 919         return mask;
 920 }
 921
 922 /*
 923  * Return the number of cores on this SOC.
 924  */
 925 int cpu_numcores(void)
 926 {
 927         return hweight32(cpu_mask());
 928 }
 929
 930 int fsl_qoriq_core_to_cluster(unsigned int core)
 931 {
 932         struct ccsr_gur __iomem *gur =
 933                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 934         int i = 0, count = 0;
 935         u32 cluster;
 936
 937         do {
 938                 int j;
 939
 940                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 941                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 942                         if (initiator_type(cluster, j)) {
 943                                 if (count == core)
 944                                         return i;
 945                                 count++;
 946                         }
 947                 }
 948                 i++;
 949         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 950
 951         return -1;      /* cannot identify the cluster */
 952 }
 953
 954 u32 fsl_qoriq_core_to_type(unsigned int core)
 955 {
 956         struct ccsr_gur __iomem *gur =
 957                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 958         int i = 0, count = 0;
 959         u32 cluster, type;
 960
 961         do {
 962                 int j;
 963
 964                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 965                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 966                         type = initiator_type(cluster, j);
 967                         if (type) {
 968                                 if (count == core)
 969                                         return type;
 970                                 count++;
 971                         }
 972                 }
 973                 i++;
 974         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 975
 976         return -1;      /* cannot identify the cluster */
 977 }
 978
 979 #ifndef CONFIG_FSL_LSCH3
 980 uint get_svr(void)
 981 {
 982         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 983
 984         return gur_in32(&gur->svr);
 985 }
 986 #endif
 987
 988 #ifdef CONFIG_DISPLAY_CPUINFO
 989 int print_cpuinfo(void)
 990 {
 991         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 992         struct sys_info sysinfo;
 993         char buf[32];
 994         unsigned int i, core;
 995         u32 type, rcw, svr = gur_in32(&gur->svr);
 996
 997         puts("SoC: ");
 998
 999         cpu_name(buf);
1000         printf(" %s (0x%x)\n", buf, svr);
1001         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
1002         get_sys_info(&sysinfo);
1003         puts("Clock Configuration:");
1004         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
1005                 if (!(i % 3))
1006                         puts("\n       ");
1007                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
1008                 printf("CPU%d(%s):%-4s MHz  ", core,
1009                        type == TY_ITYP_VER_A7 ? "A7 " :
1010                        (type == TY_ITYP_VER_A53 ? "A53" :
1011                        (type == TY_ITYP_VER_A57 ? "A57" :
1012                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
1013                        strmhz(buf, sysinfo.freq_processor[core]));
1014         }
1015         /* Display platform clock as Bus frequency. */
1016         printf("\n       Bus:      %-4s MHz  ",
1017                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1018         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1019 #ifdef CONFIG_SYS_DPAA_FMAN
1020         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1021 #endif
1022 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1023         if (soc_has_dp_ddr()) {
1024                 printf("     DP-DDR:   %-4s MT/s",
1025                        strmhz(buf, sysinfo.freq_ddrbus2));
1026         }
1027 #endif
1028         puts("\n");
1029
1030         /*
1031          * Display the RCW, so that no one gets confused as to what RCW
1032          * we're actually using for this boot.
1033          */
1034         puts("Reset Configuration Word (RCW):");
1035         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1036                 rcw = gur_in32(&gur->rcwsr[i]);
1037                 if ((i % 4) == 0)
1038                         printf("\n       %08x:", i * 4);
1039                 printf(" %08x", rcw);
1040         }
1041         puts("\n");
1042
1043         return 0;
1044 }
1045 #endif
1046
1047 #ifdef CONFIG_FSL_ESDHC
1048 int cpu_mmc_init(struct bd_info *bis)
1049 {
1050         return fsl_esdhc_mmc_init(bis);
1051 }
1052 #endif
1053
1054 int cpu_eth_init(struct bd_info *bis)
1055 {
1056         int error = 0;
1057
1058 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1059         error = fsl_mc_ldpaa_init(bis);
1060 #endif
1061 #ifdef CONFIG_FMAN_ENET
1062         fm_standard_init(bis);
1063 #endif
1064         return error;
1065 }
1066
1067 int check_psci(void)
1068 {
1069         unsigned int psci_ver;
1070
1071         psci_ver = sec_firmware_support_psci_version();
1072         if (psci_ver == PSCI_INVALID_VER)
1073                 return 1;
1074
1075         return 0;
1076 }
1077
1078 static void config_core_prefetch(void)
1079 {
1080         char *buf = NULL;
1081         char buffer[HWCONFIG_BUFFER_SIZE];
1082         const char *prefetch_arg = NULL;
1083         size_t arglen;
1084         unsigned int mask;
1085         struct pt_regs regs;
1086
1087         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1088                 buf = buffer;
1089         else
1090                 return;
1091
1092         prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1093                                          &arglen, buf);
1094
1095         if (prefetch_arg) {
1096                 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1097                 if (mask & 0x1) {
1098                         printf("Core0 prefetch can't be disabled\n");
1099                         return;
1100                 }
1101
1102 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1103                 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1104                 regs.regs[1] = mask;
1105                 smc_call(&regs);
1106
1107                 if (regs.regs[0])
1108                         printf("Prefetch disable config failed for mask ");
1109                 else
1110                         printf("Prefetch disable config passed for mask ");
1111                 printf("0x%x\n", mask);
1112         }
1113 }
1114
1115 #ifdef CONFIG_PCIE_ECAM_GENERIC
1116 __weak void set_ecam_icids(void)
1117 {
1118 }
1119 #endif
1120
1121 int arch_early_init_r(void)
1122 {
1123 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1124         u32 svr_dev_id;
1125         /*
1126          * erratum A009635 is valid only for LS2080A SoC and
1127          * its personalitiesi
1128          */
1129         svr_dev_id = get_svr();
1130         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1131                 erratum_a009635();
1132 #endif
1133 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1134         erratum_a009942_check_cpo();
1135 #endif
1136         if (check_psci()) {
1137                 debug("PSCI: PSCI does not exist.\n");
1138
1139                 /* if PSCI does not exist, boot secondary cores here */
1140                 if (fsl_layerscape_wake_seconday_cores())
1141                         printf("Did not wake secondary cores\n");
1142         }
1143
1144         config_core_prefetch();
1145
1146 #ifdef CONFIG_SYS_HAS_SERDES
1147         fsl_serdes_init();
1148 #endif
1149 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1150         /* some dpmacs in armv8a based freescale layerscape SOCs can be
1151          * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
1152          * EC*_PMUX(rgmii) bits in RCW.
1153          * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1154          * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1155          * Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes
1156          * precedence over SerDes protocol. i.e. in LX2160A if we select serdes
1157          * protocol that configures dpmac17 as SGMII and set the EC1_PMUX as
1158          * RGMII, then the dpmac is RGMII and not SGMII.
1159          *
1160          * Therefore, even thought fsl_rgmii_init is after fsl_serdes_init
1161          * function of SOC, the dpmac will be enabled as RGMII even if it was
1162          * also enabled before as SGMII. If ECx_PMUX is not configured for
1163          * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
1164          */
1165         fsl_rgmii_init();
1166 #endif
1167 #ifdef CONFIG_FMAN_ENET
1168 #ifndef CONFIG_DM_ETH
1169         fman_enet_init();
1170 #endif
1171 #endif
1172 #ifdef CONFIG_SYS_DPAA_QBMAN
1173         setup_qbman_portals();
1174 #endif
1175 #ifdef CONFIG_PCIE_ECAM_GENERIC
1176         set_ecam_icids();
1177 #endif
1178         return 0;
1179 }
1180
1181 int timer_init(void)
1182 {
1183         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1184 #ifdef CONFIG_FSL_LSCH3
1185         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1186 #endif
1187 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1188         defined(CONFIG_ARCH_LS1028A)
1189         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1190         u32 svr_dev_id;
1191 #endif
1192 #ifdef COUNTER_FREQUENCY_REAL
1193         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1194
1195         /* Update with accurate clock frequency */
1196         if (current_el() == 3)
1197                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1198 #endif
1199
1200 #ifdef CONFIG_FSL_LSCH3
1201         /* Enable timebase for all clusters.
1202          * It is safe to do so even some clusters are not enabled.
1203          */
1204         out_le32(cltbenr, 0xf);
1205 #endif
1206
1207 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1208         defined(CONFIG_ARCH_LS1028A)
1209         /*
1210          * In certain Layerscape SoCs, the clock for each core's
1211          * has an enable bit in the PMU Physical Core Time Base Enable
1212          * Register (PCTBENR), which allows the watchdog to operate.
1213          */
1214         setbits_le32(pctbenr, 0xff);
1215         /*
1216          * For LS2080A SoC and its personalities, timer controller
1217          * offset is different
1218          */
1219         svr_dev_id = get_svr();
1220         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1221                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1222
1223 #endif
1224
1225         /* Enable clock for timer
1226          * This is a global setting.
1227          */
1228         out_le32(cntcr, 0x1);
1229
1230         return 0;
1231 }
1232
1233 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1234
1235 void __efi_runtime reset_cpu(void)
1236 {
1237 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
1238         /* clear the RST_REQ_MSK and SW_RST_REQ */
1239         out_le32(rstcr, 0x0);
1240
1241         /* initiate the sw reset request */
1242         out_le32(rstcr, 0x1);
1243 #else
1244         u32 val;
1245
1246         /* Raise RESET_REQ_B */
1247         val = scfg_in32(rstcr);
1248         val |= 0x02;
1249         scfg_out32(rstcr, val);
1250 #endif
1251 }
1252
1253 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1254
1255 void __efi_runtime EFIAPI efi_reset_system(
1256                        enum efi_reset_type reset_type,
1257                        efi_status_t reset_status,
1258                        unsigned long data_size, void *reset_data)
1259 {
1260         switch (reset_type) {
1261         case EFI_RESET_COLD:
1262         case EFI_RESET_WARM:
1263         case EFI_RESET_PLATFORM_SPECIFIC:
1264                 reset_cpu();
1265                 break;
1266         case EFI_RESET_SHUTDOWN:
1267                 /* Nothing we can do */
1268                 break;
1269         }
1270
1271         while (1) { }
1272 }
1273
1274 efi_status_t efi_reset_system_init(void)
1275 {
1276         return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1277 }
1278
1279 #endif
1280
1281 /*
1282  * Calculate reserved memory with given memory bank
1283  * Return aligned memory size on success
1284  * Return (ram_size + needed size) for failure
1285  */
1286 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1287 {
1288         phys_size_t ram_top = ram_size;
1289
1290 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1291         ram_top = mc_get_dram_block_size();
1292         if (ram_top > ram_size)
1293                 return ram_size + ram_top;
1294
1295         ram_top = ram_size - ram_top;
1296         /* The start address of MC reserved memory needs to be aligned. */
1297         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1298 #endif
1299
1300         return ram_size - ram_top;
1301 }
1302
1303 phys_size_t get_effective_memsize(void)
1304 {
1305         phys_size_t ea_size, rem = 0;
1306
1307         /*
1308          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1309          * first region is 2GB space at 0x8000_0000. Secure memory needs to
1310          * allocated from first region. If the memory extends to  the second
1311          * region (or the third region if applicable), Management Complex (MC)
1312          * memory should be put into the highest region, i.e. the end of DDR
1313          * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1314          * U-Boot doesn't relocate itself into higher address. Should DDR be
1315          * configured to skip the first region, this function needs to be
1316          * adjusted.
1317          */
1318         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1319                 ea_size = CONFIG_MAX_MEM_MAPPED;
1320                 rem = gd->ram_size - ea_size;
1321         } else {
1322                 ea_size = gd->ram_size;
1323         }
1324
1325 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1326         /* Check if we have enough space for secure memory */
1327         if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1328                 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1329         else
1330                 printf("Error: No enough space for secure memory.\n");
1331 #endif
1332         /* Check if we have enough memory for MC */
1333         if (rem < board_reserve_ram_top(rem)) {
1334                 /* Not enough memory in high region to reserve */
1335                 if (ea_size > board_reserve_ram_top(ea_size))
1336                         ea_size -= board_reserve_ram_top(ea_size);
1337                 else
1338                         printf("Error: No enough space for reserved memory.\n");
1339         }
1340
1341         return ea_size;
1342 }
1343
1344 #ifdef CONFIG_TFABOOT
1345 phys_size_t tfa_get_dram_size(void)
1346 {
1347         struct pt_regs regs;
1348         phys_size_t dram_size = 0;
1349
1350         regs.regs[0] = SMC_DRAM_BANK_INFO;
1351         regs.regs[1] = -1;
1352
1353         smc_call(&regs);
1354         if (regs.regs[0])
1355                 return 0;
1356
1357         dram_size = regs.regs[1];
1358         return dram_size;
1359 }
1360
1361 static int tfa_dram_init_banksize(void)
1362 {
1363         int i = 0, ret = 0;
1364         struct pt_regs regs;
1365         phys_size_t dram_size = tfa_get_dram_size();
1366
1367         debug("dram_size %llx\n", dram_size);
1368
1369         if (!dram_size)
1370                 return -EINVAL;
1371
1372         do {
1373                 regs.regs[0] = SMC_DRAM_BANK_INFO;
1374                 regs.regs[1] = i;
1375
1376                 smc_call(&regs);
1377                 if (regs.regs[0]) {
1378                         ret = -EINVAL;
1379                         break;
1380                 }
1381
1382                 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1383                       regs.regs[2]);
1384                 gd->bd->bi_dram[i].start = regs.regs[1];
1385                 gd->bd->bi_dram[i].size = regs.regs[2];
1386
1387                 dram_size -= gd->bd->bi_dram[i].size;
1388
1389                 i++;
1390         } while (dram_size);
1391
1392         if (i > 0)
1393                 ret = 0;
1394
1395 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1396         /* Assign memory for MC */
1397 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1398         if (gd->bd->bi_dram[2].size >=
1399             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1400                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1401                             gd->bd->bi_dram[2].size -
1402                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1403         } else
1404 #endif
1405         {
1406                 if (gd->bd->bi_dram[1].size >=
1407                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1408                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1409                                 gd->bd->bi_dram[1].size -
1410                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1411                 } else if (gd->bd->bi_dram[0].size >
1412                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1413                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1414                                 gd->bd->bi_dram[0].size -
1415                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1416                 }
1417         }
1418 #endif  /* CONFIG_RESV_RAM */
1419
1420         return ret;
1421 }
1422 #endif
1423
1424 int dram_init_banksize(void)
1425 {
1426 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1427         phys_size_t dp_ddr_size;
1428 #endif
1429
1430 #ifdef CONFIG_TFABOOT
1431         if (!tfa_dram_init_banksize())
1432                 return 0;
1433 #endif
1434         /*
1435          * gd->ram_size has the total size of DDR memory, less reserved secure
1436          * memory. The DDR extends from low region to high region(s) presuming
1437          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1438          * the location of secure memory. gd->arch.resv_ram tracks the location
1439          * of reserved memory for Management Complex (MC). Because gd->ram_size
1440          * is reduced by this function if secure memory is reserved, checking
1441          * gd->arch.secure_ram should be done to avoid running it repeatedly.
1442          */
1443
1444 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1445         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1446                 debug("No need to run again, skip %s\n", __func__);
1447
1448                 return 0;
1449         }
1450 #endif
1451
1452         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1453         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1454                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1455                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1456                 gd->bd->bi_dram[1].size = gd->ram_size -
1457                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
1458 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1459                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1460                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1461                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1462                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
1463                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1464                 }
1465 #endif
1466         } else {
1467                 gd->bd->bi_dram[0].size = gd->ram_size;
1468         }
1469 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1470         if (gd->bd->bi_dram[0].size >
1471                                 CONFIG_SYS_MEM_RESERVE_SECURE) {
1472                 gd->bd->bi_dram[0].size -=
1473                                 CONFIG_SYS_MEM_RESERVE_SECURE;
1474                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1475                                       gd->bd->bi_dram[0].size;
1476                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1477                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1478         }
1479 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
1480
1481 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1482         /* Assign memory for MC */
1483 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1484         if (gd->bd->bi_dram[2].size >=
1485             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1486                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1487                             gd->bd->bi_dram[2].size -
1488                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1489         } else
1490 #endif
1491         {
1492                 if (gd->bd->bi_dram[1].size >=
1493                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1494                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1495                                 gd->bd->bi_dram[1].size -
1496                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1497                 } else if (gd->bd->bi_dram[0].size >
1498                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1499                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1500                                 gd->bd->bi_dram[0].size -
1501                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1502                 }
1503         }
1504 #endif  /* CONFIG_RESV_RAM */
1505
1506 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1507 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1508 #error "This SoC shouldn't have DP DDR"
1509 #endif
1510         if (soc_has_dp_ddr()) {
1511                 /* initialize DP-DDR here */
1512                 puts("DP-DDR:  ");
1513                 /*
1514                  * DDR controller use 0 as the base address for binding.
1515                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1516                  */
1517                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1518                                           CONFIG_DP_DDR_CTRL,
1519                                           CONFIG_DP_DDR_NUM_CTRLS,
1520                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1521                                           NULL, NULL, NULL);
1522                 if (dp_ddr_size) {
1523                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1524                         gd->bd->bi_dram[2].size = dp_ddr_size;
1525                 } else {
1526                         puts("Not detected");
1527                 }
1528         }
1529 #endif
1530
1531 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1532         debug("%s is called. gd->ram_size is reduced to %lu\n",
1533               __func__, (ulong)gd->ram_size);
1534 #endif
1535
1536         return 0;
1537 }
1538
1539 #if CONFIG_IS_ENABLED(EFI_LOADER)
1540 void efi_add_known_memory(void)
1541 {
1542         int i;
1543         phys_addr_t ram_start;
1544         phys_size_t ram_size;
1545
1546         /* Add RAM */
1547         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1548 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1549 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1550 #error "This SoC shouldn't have DP DDR"
1551 #endif
1552                 if (i == 2)
1553                         continue;       /* skip DP-DDR */
1554 #endif
1555                 ram_start = gd->bd->bi_dram[i].start;
1556                 ram_size = gd->bd->bi_dram[i].size;
1557 #ifdef CONFIG_RESV_RAM
1558                 if (gd->arch.resv_ram >= ram_start &&
1559                     gd->arch.resv_ram < ram_start + ram_size)
1560                         ram_size = gd->arch.resv_ram - ram_start;
1561 #endif
1562                 efi_add_memory_map(ram_start, ram_size,
1563                                    EFI_CONVENTIONAL_MEMORY);
1564         }
1565 }
1566 #endif
1567
1568 /*
1569  * Before DDR size is known, early MMU table have DDR mapped as device memory
1570  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1571  * needs to be set for these mappings.
1572  * If a special case configures DDR with holes in the mapping, the holes need
1573  * to be marked as invalid. This is not implemented in this function.
1574  */
1575 void update_early_mmu_table(void)
1576 {
1577         if (!gd->arch.tlb_addr)
1578                 return;
1579
1580         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1581                 mmu_change_region_attr(
1582                                         CONFIG_SYS_SDRAM_BASE,
1583                                         gd->ram_size,
1584                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1585                                         PTE_BLOCK_OUTER_SHARE           |
1586                                         PTE_BLOCK_NS                    |
1587                                         PTE_TYPE_VALID);
1588         } else {
1589                 mmu_change_region_attr(
1590                                         CONFIG_SYS_SDRAM_BASE,
1591                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1592                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1593                                         PTE_BLOCK_OUTER_SHARE           |
1594                                         PTE_BLOCK_NS                    |
1595                                         PTE_TYPE_VALID);
1596 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1597 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1598 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1599 #endif
1600                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1601                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
1602                         mmu_change_region_attr(
1603                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1604                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1605                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1606                                         PTE_BLOCK_OUTER_SHARE           |
1607                                         PTE_BLOCK_NS                    |
1608                                         PTE_TYPE_VALID);
1609                         mmu_change_region_attr(
1610                                         CONFIG_SYS_DDR_BLOCK3_BASE,
1611                                         gd->ram_size -
1612                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
1613                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1614                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1615                                         PTE_BLOCK_OUTER_SHARE           |
1616                                         PTE_BLOCK_NS                    |
1617                                         PTE_TYPE_VALID);
1618                 } else
1619 #endif
1620                 {
1621                         mmu_change_region_attr(
1622                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1623                                         gd->ram_size -
1624                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1625                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1626                                         PTE_BLOCK_OUTER_SHARE           |
1627                                         PTE_BLOCK_NS                    |
1628                                         PTE_TYPE_VALID);
1629                 }
1630         }
1631 }
1632
1633 __weak int dram_init(void)
1634 {
1635         fsl_initdram();
1636 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1637         defined(CONFIG_SPL_BUILD)
1638         /* This will break-before-make MMU for DDR */
1639         update_early_mmu_table();
1640 #endif
1641
1642         return 0;
1643 }
1644
1645 #ifdef CONFIG_ARCH_MISC_INIT
1646 __weak int serdes_misc_init(void)
1647 {
1648         return 0;
1649 }
1650
1651 int arch_misc_init(void)
1652 {
1653         serdes_misc_init();
1654
1655         return 0;
1656 }
1657 #endif