arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 /*
   2  * Copyright 2017 NXP
   3  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/io.h>
  11 #include <linux/errno.h>
  12 #include <asm/system.h>
  13 #include <asm/armv8/mmu.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/fsl_serdes.h>
  16 #include <asm/arch/soc.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/speed.h>
  19 #include <asm/arch/mp.h>
  20 #include <efi_loader.h>
  21 #include <fm_eth.h>
  22 #include <fsl-mc/fsl_mc.h>
  23 #ifdef CONFIG_FSL_ESDHC
  24 #include <fsl_esdhc.h>
  25 #endif
  26 #include <asm/armv8/sec_firmware.h>
  27 #ifdef CONFIG_SYS_FSL_DDR
  28 #include <fsl_ddr.h>
  29 #endif
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 struct mm_region *mem_map = early_map;
  34
  35 void cpu_name(char *name)
  36 {
  37         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  38         unsigned int i, svr, ver;
  39
  40         svr = gur_in32(&gur->svr);
  41         ver = SVR_SOC_VER(svr);
  42
  43         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  44                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
  45                         strcpy(name, cpu_type_list[i].name);
  46
  47                         if (IS_E_PROCESSOR(svr))
  48                                 strcat(name, "E");
  49
  50                         sprintf(name + strlen(name), " Rev%d.%d",
  51                                 SVR_MAJ(svr), SVR_MIN(svr));
  52                         break;
  53                 }
  54
  55         if (i == ARRAY_SIZE(cpu_type_list))
  56                 strcpy(name, "unknown");
  57 }
  58
  59 #ifndef CONFIG_SYS_DCACHE_OFF
  60 /*
  61  * To start MMU before DDR is available, we create MMU table in SRAM.
  62  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
  63  * levels of translation tables here to cover 40-bit address space.
  64  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
  65  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
  66  * Note, the debug print in cache_v8.c is not usable for debugging
  67  * these early MMU tables because UART is not yet available.
  68  */
  69 static inline void early_mmu_setup(void)
  70 {
  71         unsigned int el = current_el();
  72
  73         /* global data is already setup, no allocation yet */
  74         gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
  75         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
  76         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
  77
  78         /* Create early page tables */
  79         setup_pgtables();
  80
  81         /* point TTBR to the new table */
  82         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
  83                           get_tcr(el, NULL, NULL) &
  84                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
  85                           MEMORY_ATTRIBUTES);
  86
  87         set_sctlr(get_sctlr() | CR_M);
  88 }
  89
  90 static void fix_pcie_mmu_map(void)
  91 {
  92 #ifdef CONFIG_ARCH_LS2080A
  93         unsigned int i;
  94         u32 svr, ver;
  95         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  96
  97         svr = gur_in32(&gur->svr);
  98         ver = SVR_SOC_VER(svr);
  99
 100         /* Fix PCIE base and size for LS2088A */
 101         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 102             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 103             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 104                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 105                         switch (final_map[i].phys) {
 106                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 107                                 final_map[i].phys = 0x2000000000ULL;
 108                                 final_map[i].virt = 0x2000000000ULL;
 109                                 final_map[i].size = 0x800000000ULL;
 110                                 break;
 111                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 112                                 final_map[i].phys = 0x2800000000ULL;
 113                                 final_map[i].virt = 0x2800000000ULL;
 114                                 final_map[i].size = 0x800000000ULL;
 115                                 break;
 116                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 117                                 final_map[i].phys = 0x3000000000ULL;
 118                                 final_map[i].virt = 0x3000000000ULL;
 119                                 final_map[i].size = 0x800000000ULL;
 120                                 break;
 121                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 122                                 final_map[i].phys = 0x3800000000ULL;
 123                                 final_map[i].virt = 0x3800000000ULL;
 124                                 final_map[i].size = 0x800000000ULL;
 125                                 break;
 126                         default:
 127                                 break;
 128                         }
 129                 }
 130         }
 131 #endif
 132 }
 133
 134 /*
 135  * The final tables look similar to early tables, but different in detail.
 136  * These tables are in DRAM. Sub tables are added to enable cache for
 137  * QBMan and OCRAM.
 138  *
 139  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 140  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 141  */
 142 static inline void final_mmu_setup(void)
 143 {
 144         u64 tlb_addr_save = gd->arch.tlb_addr;
 145         unsigned int el = current_el();
 146         int index;
 147
 148         /* fix the final_map before filling in the block entries */
 149         fix_pcie_mmu_map();
 150
 151         mem_map = final_map;
 152
 153         /* Update mapping for DDR to actual size */
 154         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 155                 /*
 156                  * Find the entry for DDR mapping and update the address and
 157                  * size. Zero-sized mapping will be skipped when creating MMU
 158                  * table.
 159                  */
 160                 switch (final_map[index].virt) {
 161                 case CONFIG_SYS_FSL_DRAM_BASE1:
 162                         final_map[index].virt = gd->bd->bi_dram[0].start;
 163                         final_map[index].phys = gd->bd->bi_dram[0].start;
 164                         final_map[index].size = gd->bd->bi_dram[0].size;
 165                         break;
 166 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 167                 case CONFIG_SYS_FSL_DRAM_BASE2:
 168 #if (CONFIG_NR_DRAM_BANKS >= 2)
 169                         final_map[index].virt = gd->bd->bi_dram[1].start;
 170                         final_map[index].phys = gd->bd->bi_dram[1].start;
 171                         final_map[index].size = gd->bd->bi_dram[1].size;
 172 #else
 173                         final_map[index].size = 0;
 174 #endif
 175                 break;
 176 #endif
 177 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 178                 case CONFIG_SYS_FSL_DRAM_BASE3:
 179 #if (CONFIG_NR_DRAM_BANKS >= 3)
 180                         final_map[index].virt = gd->bd->bi_dram[2].start;
 181                         final_map[index].phys = gd->bd->bi_dram[2].start;
 182                         final_map[index].size = gd->bd->bi_dram[2].size;
 183 #else
 184                         final_map[index].size = 0;
 185 #endif
 186                 break;
 187 #endif
 188                 default:
 189                         break;
 190                 }
 191         }
 192
 193 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 194         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 195                 if (el == 3) {
 196                         /*
 197                          * Only use gd->arch.secure_ram if the address is
 198                          * recalculated. Align to 4KB for MMU table.
 199                          */
 200                         /* put page tables in secure ram */
 201                         index = ARRAY_SIZE(final_map) - 2;
 202                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 203                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 204                         final_map[index].phys = final_map[index].virt;
 205                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 206                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 207                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 208                         tlb_addr_save = gd->arch.tlb_addr;
 209                 } else {
 210                         /* Use allocated (board_f.c) memory for TLB */
 211                         tlb_addr_save = gd->arch.tlb_allocated;
 212                         gd->arch.tlb_addr = tlb_addr_save;
 213                 }
 214         }
 215 #endif
 216
 217         /* Reset the fill ptr */
 218         gd->arch.tlb_fillptr = tlb_addr_save;
 219
 220         /* Create normal system page tables */
 221         setup_pgtables();
 222
 223         /* Create emergency page tables */
 224         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 225         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 226         setup_pgtables();
 227         gd->arch.tlb_addr = tlb_addr_save;
 228
 229         /* Disable cache and MMU */
 230         dcache_disable();       /* TLBs are invalidated */
 231         invalidate_icache_all();
 232
 233         /* point TTBR to the new table */
 234         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 235                           MEMORY_ATTRIBUTES);
 236
 237         set_sctlr(get_sctlr() | CR_M);
 238 }
 239
 240 u64 get_page_table_size(void)
 241 {
 242         return 0x10000;
 243 }
 244
 245 int arch_cpu_init(void)
 246 {
 247         /*
 248          * This function is called before U-Boot relocates itself to speed up
 249          * on system running. It is not necessary to run if performance is not
 250          * critical. Skip if MMU is already enabled by SPL or other means.
 251          */
 252         if (get_sctlr() & CR_M)
 253                 return 0;
 254
 255         icache_enable();
 256         __asm_invalidate_dcache_all();
 257         __asm_invalidate_tlb_all();
 258         early_mmu_setup();
 259         set_sctlr(get_sctlr() | CR_C);
 260         return 0;
 261 }
 262
 263 void mmu_setup(void)
 264 {
 265         final_mmu_setup();
 266 }
 267
 268 /*
 269  * This function is called from common/board_r.c.
 270  * It recreates MMU table in main memory.
 271  */
 272 void enable_caches(void)
 273 {
 274         mmu_setup();
 275         __asm_invalidate_tlb_all();
 276         icache_enable();
 277         dcache_enable();
 278 }
 279 #endif
 280
 281 u32 initiator_type(u32 cluster, int init_id)
 282 {
 283         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 284         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 285         u32 type = 0;
 286
 287         type = gur_in32(&gur->tp_ityp[idx]);
 288         if (type & TP_ITYP_AV)
 289                 return type;
 290
 291         return 0;
 292 }
 293
 294 u32 cpu_pos_mask(void)
 295 {
 296         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 297         int i = 0;
 298         u32 cluster, type, mask = 0;
 299
 300         do {
 301                 int j;
 302
 303                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 304                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 305                         type = initiator_type(cluster, j);
 306                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 307                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 308                 }
 309                 i++;
 310         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 311
 312         return mask;
 313 }
 314
 315 u32 cpu_mask(void)
 316 {
 317         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 318         int i = 0, count = 0;
 319         u32 cluster, type, mask = 0;
 320
 321         do {
 322                 int j;
 323
 324                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 325                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 326                         type = initiator_type(cluster, j);
 327                         if (type) {
 328                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 329                                         mask |= 1 << count;
 330                                 count++;
 331                         }
 332                 }
 333                 i++;
 334         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 335
 336         return mask;
 337 }
 338
 339 /*
 340  * Return the number of cores on this SOC.
 341  */
 342 int cpu_numcores(void)
 343 {
 344         return hweight32(cpu_mask());
 345 }
 346
 347 int fsl_qoriq_core_to_cluster(unsigned int core)
 348 {
 349         struct ccsr_gur __iomem *gur =
 350                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 351         int i = 0, count = 0;
 352         u32 cluster;
 353
 354         do {
 355                 int j;
 356
 357                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 358                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 359                         if (initiator_type(cluster, j)) {
 360                                 if (count == core)
 361                                         return i;
 362                                 count++;
 363                         }
 364                 }
 365                 i++;
 366         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 367
 368         return -1;      /* cannot identify the cluster */
 369 }
 370
 371 u32 fsl_qoriq_core_to_type(unsigned int core)
 372 {
 373         struct ccsr_gur __iomem *gur =
 374                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 375         int i = 0, count = 0;
 376         u32 cluster, type;
 377
 378         do {
 379                 int j;
 380
 381                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 382                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 383                         type = initiator_type(cluster, j);
 384                         if (type) {
 385                                 if (count == core)
 386                                         return type;
 387                                 count++;
 388                         }
 389                 }
 390                 i++;
 391         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 392
 393         return -1;      /* cannot identify the cluster */
 394 }
 395
 396 #ifndef CONFIG_FSL_LSCH3
 397 uint get_svr(void)
 398 {
 399         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 400
 401         return gur_in32(&gur->svr);
 402 }
 403 #endif
 404
 405 #ifdef CONFIG_DISPLAY_CPUINFO
 406 int print_cpuinfo(void)
 407 {
 408         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 409         struct sys_info sysinfo;
 410         char buf[32];
 411         unsigned int i, core;
 412         u32 type, rcw, svr = gur_in32(&gur->svr);
 413
 414         puts("SoC: ");
 415
 416         cpu_name(buf);
 417         printf(" %s (0x%x)\n", buf, svr);
 418         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 419         get_sys_info(&sysinfo);
 420         puts("Clock Configuration:");
 421         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 422                 if (!(i % 3))
 423                         puts("\n       ");
 424                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
 425                 printf("CPU%d(%s):%-4s MHz  ", core,
 426                        type == TY_ITYP_VER_A7 ? "A7 " :
 427                        (type == TY_ITYP_VER_A53 ? "A53" :
 428                        (type == TY_ITYP_VER_A57 ? "A57" :
 429                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
 430                        strmhz(buf, sysinfo.freq_processor[core]));
 431         }
 432         /* Display platform clock as Bus frequency. */
 433         printf("\n       Bus:      %-4s MHz  ",
 434                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
 435         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
 436 #ifdef CONFIG_SYS_DPAA_FMAN
 437         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 438 #endif
 439 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 440         if (soc_has_dp_ddr()) {
 441                 printf("     DP-DDR:   %-4s MT/s",
 442                        strmhz(buf, sysinfo.freq_ddrbus2));
 443         }
 444 #endif
 445         puts("\n");
 446
 447         /*
 448          * Display the RCW, so that no one gets confused as to what RCW
 449          * we're actually using for this boot.
 450          */
 451         puts("Reset Configuration Word (RCW):");
 452         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
 453                 rcw = gur_in32(&gur->rcwsr[i]);
 454                 if ((i % 4) == 0)
 455                         printf("\n       %08x:", i * 4);
 456                 printf(" %08x", rcw);
 457         }
 458         puts("\n");
 459
 460         return 0;
 461 }
 462 #endif
 463
 464 #ifdef CONFIG_FSL_ESDHC
 465 int cpu_mmc_init(bd_t *bis)
 466 {
 467         return fsl_esdhc_mmc_init(bis);
 468 }
 469 #endif
 470
 471 int cpu_eth_init(bd_t *bis)
 472 {
 473         int error = 0;
 474
 475 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 476         error = fsl_mc_ldpaa_init(bis);
 477 #endif
 478 #ifdef CONFIG_FMAN_ENET
 479         fm_standard_init(bis);
 480 #endif
 481         return error;
 482 }
 483
 484 static inline int check_psci(void)
 485 {
 486         unsigned int psci_ver;
 487
 488         psci_ver = sec_firmware_support_psci_version();
 489         if (psci_ver == PSCI_INVALID_VER)
 490                 return 1;
 491
 492         return 0;
 493 }
 494
 495 int arch_early_init_r(void)
 496 {
 497 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 498         u32 svr_dev_id;
 499         /*
 500          * erratum A009635 is valid only for LS2080A SoC and
 501          * its personalitiesi
 502          */
 503         svr_dev_id = get_svr() >> 16;
 504         if (svr_dev_id == SVR_DEV_LS2080A)
 505                 erratum_a009635();
 506 #endif
 507 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
 508         erratum_a009942_check_cpo();
 509 #endif
 510         if (check_psci()) {
 511                 debug("PSCI: PSCI does not exist.\n");
 512
 513                 /* if PSCI does not exist, boot secondary cores here */
 514                 if (fsl_layerscape_wake_seconday_cores())
 515                         printf("Did not wake secondary cores\n");
 516         }
 517
 518 #ifdef CONFIG_SYS_HAS_SERDES
 519         fsl_serdes_init();
 520 #endif
 521 #ifdef CONFIG_FMAN_ENET
 522         fman_enet_init();
 523 #endif
 524         return 0;
 525 }
 526
 527 int timer_init(void)
 528 {
 529         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 530 #ifdef CONFIG_FSL_LSCH3
 531         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 532 #endif
 533 #ifdef CONFIG_ARCH_LS2080A
 534         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
 535         u32 svr_dev_id;
 536 #endif
 537 #ifdef COUNTER_FREQUENCY_REAL
 538         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 539
 540         /* Update with accurate clock frequency */
 541         if (current_el() == 3)
 542                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
 543 #endif
 544
 545 #ifdef CONFIG_FSL_LSCH3
 546         /* Enable timebase for all clusters.
 547          * It is safe to do so even some clusters are not enabled.
 548          */
 549         out_le32(cltbenr, 0xf);
 550 #endif
 551
 552 #ifdef CONFIG_ARCH_LS2080A
 553         /*
 554          * In certain Layerscape SoCs, the clock for each core's
 555          * has an enable bit in the PMU Physical Core Time Base Enable
 556          * Register (PCTBENR), which allows the watchdog to operate.
 557          */
 558         setbits_le32(pctbenr, 0xff);
 559         /*
 560          * For LS2080A SoC and its personalities, timer controller
 561          * offset is different
 562          */
 563         svr_dev_id = get_svr() >> 16;
 564         if (svr_dev_id == SVR_DEV_LS2080A)
 565                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
 566
 567 #endif
 568
 569         /* Enable clock for timer
 570          * This is a global setting.
 571          */
 572         out_le32(cntcr, 0x1);
 573
 574         return 0;
 575 }
 576
 577 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
 578
 579 void __efi_runtime reset_cpu(ulong addr)
 580 {
 581         u32 val;
 582
 583         /* Raise RESET_REQ_B */
 584         val = scfg_in32(rstcr);
 585         val |= 0x02;
 586         scfg_out32(rstcr, val);
 587 }
 588
 589 #ifdef CONFIG_EFI_LOADER
 590
 591 void __efi_runtime EFIAPI efi_reset_system(
 592                        enum efi_reset_type reset_type,
 593                        efi_status_t reset_status,
 594                        unsigned long data_size, void *reset_data)
 595 {
 596         switch (reset_type) {
 597         case EFI_RESET_COLD:
 598         case EFI_RESET_WARM:
 599                 reset_cpu(0);
 600                 break;
 601         case EFI_RESET_SHUTDOWN:
 602                 /* Nothing we can do */
 603                 break;
 604         }
 605
 606         while (1) { }
 607 }
 608
 609 void efi_reset_system_init(void)
 610 {
 611        efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
 612 }
 613
 614 #endif
 615
 616 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
 617 {
 618         phys_size_t ram_top = ram_size;
 619
 620 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 621         /* The start address of MC reserved memory needs to be aligned. */
 622         ram_top -= mc_get_dram_block_size();
 623         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
 624 #endif
 625
 626         return ram_size - ram_top;
 627 }
 628
 629 phys_size_t get_effective_memsize(void)
 630 {
 631         phys_size_t ea_size, rem = 0;
 632
 633         /*
 634          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
 635          * first region is 2GB space at 0x8000_0000. If the memory extends to
 636          * the second region (or the third region if applicable), the secure
 637          * memory and Management Complex (MC) memory should be put into the
 638          * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED
 639          * is set to the size of first region so U-Boot doesn't relocate itself
 640          * into higher address. Should DDR be configured to skip the first
 641          * region, this function needs to be adjusted.
 642          */
 643         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
 644                 ea_size = CONFIG_MAX_MEM_MAPPED;
 645                 rem = gd->ram_size - ea_size;
 646         } else {
 647                 ea_size = gd->ram_size;
 648         }
 649
 650 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 651         /* Check if we have enough space for secure memory */
 652         if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) {
 653                 rem -= CONFIG_SYS_MEM_RESERVE_SECURE;
 654         } else {
 655                 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) {
 656                         ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 657                         rem = 0;        /* Presume MC requires more memory */
 658                 } else {
 659                         printf("Error: No enough space for secure memory.\n");
 660                 }
 661         }
 662 #endif
 663         /* Check if we have enough memory for MC */
 664         if (rem < board_reserve_ram_top(rem)) {
 665                 /* Not enough memory in high region to reserve */
 666                 if (ea_size > board_reserve_ram_top(rem))
 667                         ea_size -= board_reserve_ram_top(rem);
 668                 else
 669                         printf("Error: No enough space for reserved memory.\n");
 670         }
 671
 672         return ea_size;
 673 }
 674
 675 int dram_init_banksize(void)
 676 {
 677 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 678         phys_size_t dp_ddr_size;
 679 #endif
 680
 681         /*
 682          * gd->ram_size has the total size of DDR memory, less reserved secure
 683          * memory. The DDR extends from low region to high region(s) presuming
 684          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
 685          * the location of secure memory. gd->arch.resv_ram tracks the location
 686          * of reserved memory for Management Complex (MC).
 687          */
 688         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 689         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
 690                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
 691                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 692                 gd->bd->bi_dram[1].size = gd->ram_size -
 693                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
 694 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 695                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
 696                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
 697                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
 698                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
 699                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
 700                 }
 701 #endif
 702         } else {
 703                 gd->bd->bi_dram[0].size = gd->ram_size;
 704         }
 705 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 706 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 707         if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
 708                 gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 709                 gd->arch.secure_ram = gd->bd->bi_dram[2].start +
 710                                       gd->bd->bi_dram[2].size;
 711                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 712                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 713         } else
 714 #endif
 715         {
 716                 if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
 717                         gd->bd->bi_dram[1].size -=
 718                                         CONFIG_SYS_MEM_RESERVE_SECURE;
 719                         gd->arch.secure_ram = gd->bd->bi_dram[1].start +
 720                                               gd->bd->bi_dram[1].size;
 721                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 722                         gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 723                 } else if (gd->bd->bi_dram[0].size >
 724                                         CONFIG_SYS_MEM_RESERVE_SECURE) {
 725                         gd->bd->bi_dram[0].size -=
 726                                         CONFIG_SYS_MEM_RESERVE_SECURE;
 727                         gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 728                                               gd->bd->bi_dram[0].size;
 729                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 730                         gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 731                 }
 732         }
 733 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
 734
 735 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 736         /* Assign memory for MC */
 737 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 738         if (gd->bd->bi_dram[2].size >=
 739             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
 740                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
 741                             gd->bd->bi_dram[2].size -
 742                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
 743         } else
 744 #endif
 745         {
 746                 if (gd->bd->bi_dram[1].size >=
 747                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
 748                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
 749                                 gd->bd->bi_dram[1].size -
 750                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
 751                 } else if (gd->bd->bi_dram[0].size >
 752                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
 753                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
 754                                 gd->bd->bi_dram[0].size -
 755                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
 756                 }
 757         }
 758 #endif  /* CONFIG_FSL_MC_ENET */
 759
 760 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 761 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 762 #error "This SoC shouldn't have DP DDR"
 763 #endif
 764         if (soc_has_dp_ddr()) {
 765                 /* initialize DP-DDR here */
 766                 puts("DP-DDR:  ");
 767                 /*
 768                  * DDR controller use 0 as the base address for binding.
 769                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 770                  */
 771                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
 772                                           CONFIG_DP_DDR_CTRL,
 773                                           CONFIG_DP_DDR_NUM_CTRLS,
 774                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
 775                                           NULL, NULL, NULL);
 776                 if (dp_ddr_size) {
 777                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
 778                         gd->bd->bi_dram[2].size = dp_ddr_size;
 779                 } else {
 780                         puts("Not detected");
 781                 }
 782         }
 783 #endif
 784
 785         return 0;
 786 }
 787
 788 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
 789 void efi_add_known_memory(void)
 790 {
 791         int i;
 792         phys_addr_t ram_start, start;
 793         phys_size_t ram_size;
 794         u64 pages;
 795
 796         /* Add RAM */
 797         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 798 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 799 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 800 #error "This SoC shouldn't have DP DDR"
 801 #endif
 802                 if (i == 2)
 803                         continue;       /* skip DP-DDR */
 804 #endif
 805                 ram_start = gd->bd->bi_dram[i].start;
 806                 ram_size = gd->bd->bi_dram[i].size;
 807 #ifdef CONFIG_RESV_RAM
 808                 if (gd->arch.resv_ram >= ram_start &&
 809                     gd->arch.resv_ram < ram_start + ram_size)
 810                         ram_size = gd->arch.resv_ram - ram_start;
 811 #endif
 812                 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
 813                 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
 814
 815                 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
 816                                    false);
 817         }
 818 }
 819 #endif
 820
 821 /*
 822  * Before DDR size is known, early MMU table have DDR mapped as device memory
 823  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
 824  * needs to be set for these mappings.
 825  * If a special case configures DDR with holes in the mapping, the holes need
 826  * to be marked as invalid. This is not implemented in this function.
 827  */
 828 void update_early_mmu_table(void)
 829 {
 830         if (!gd->arch.tlb_addr)
 831                 return;
 832
 833         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
 834                 mmu_change_region_attr(
 835                                         CONFIG_SYS_SDRAM_BASE,
 836                                         gd->ram_size,
 837                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
 838                                         PTE_BLOCK_OUTER_SHARE           |
 839                                         PTE_BLOCK_NS                    |
 840                                         PTE_TYPE_VALID);
 841         } else {
 842                 mmu_change_region_attr(
 843                                         CONFIG_SYS_SDRAM_BASE,
 844                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
 845                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
 846                                         PTE_BLOCK_OUTER_SHARE           |
 847                                         PTE_BLOCK_NS                    |
 848                                         PTE_TYPE_VALID);
 849 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 850 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
 851 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
 852 #endif
 853                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
 854                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
 855                         mmu_change_region_attr(
 856                                         CONFIG_SYS_DDR_BLOCK2_BASE,
 857                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
 858                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
 859                                         PTE_BLOCK_OUTER_SHARE           |
 860                                         PTE_BLOCK_NS                    |
 861                                         PTE_TYPE_VALID);
 862                         mmu_change_region_attr(
 863                                         CONFIG_SYS_DDR_BLOCK3_BASE,
 864                                         gd->ram_size -
 865                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
 866                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
 867                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
 868                                         PTE_BLOCK_OUTER_SHARE           |
 869                                         PTE_BLOCK_NS                    |
 870                                         PTE_TYPE_VALID);
 871                 } else
 872 #endif
 873                 {
 874                         mmu_change_region_attr(
 875                                         CONFIG_SYS_DDR_BLOCK2_BASE,
 876                                         gd->ram_size -
 877                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
 878                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
 879                                         PTE_BLOCK_OUTER_SHARE           |
 880                                         PTE_BLOCK_NS                    |
 881                                         PTE_TYPE_VALID);
 882                 }
 883         }
 884 }
 885
 886 __weak int dram_init(void)
 887 {
 888         fsl_initdram();
 889 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 890         /* This will break-before-make MMU for DDR */
 891         update_early_mmu_table();
 892 #endif
 893
 894         return 0;
 895 }