arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 /*
   2  * Copyright 2017 NXP
   3  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/io.h>
  11 #include <linux/errno.h>
  12 #include <asm/system.h>
  13 #include <asm/armv8/mmu.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/fsl_serdes.h>
  16 #include <asm/arch/soc.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/speed.h>
  19 #include <asm/arch/mp.h>
  20 #include <efi_loader.h>
  21 #include <fm_eth.h>
  22 #include <fsl-mc/fsl_mc.h>
  23 #ifdef CONFIG_FSL_ESDHC
  24 #include <fsl_esdhc.h>
  25 #endif
  26 #include <asm/armv8/sec_firmware.h>
  27 #ifdef CONFIG_SYS_FSL_DDR
  28 #include <fsl_ddr.h>
  29 #endif
  30 #include <asm/arch/clock.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 struct mm_region *mem_map = early_map;
  35
  36 void cpu_name(char *name)
  37 {
  38         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  39         unsigned int i, svr, ver;
  40
  41         svr = gur_in32(&gur->svr);
  42         ver = SVR_SOC_VER(svr);
  43
  44         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  45                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
  46                         strcpy(name, cpu_type_list[i].name);
  47
  48                         if (IS_E_PROCESSOR(svr))
  49                                 strcat(name, "E");
  50
  51                         sprintf(name + strlen(name), " Rev%d.%d",
  52                                 SVR_MAJ(svr), SVR_MIN(svr));
  53                         break;
  54                 }
  55
  56         if (i == ARRAY_SIZE(cpu_type_list))
  57                 strcpy(name, "unknown");
  58 }
  59
  60 #ifndef CONFIG_SYS_DCACHE_OFF
  61 /*
  62  * To start MMU before DDR is available, we create MMU table in SRAM.
  63  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
  64  * levels of translation tables here to cover 40-bit address space.
  65  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
  66  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
  67  * Note, the debug print in cache_v8.c is not usable for debugging
  68  * these early MMU tables because UART is not yet available.
  69  */
  70 static inline void early_mmu_setup(void)
  71 {
  72         unsigned int el = current_el();
  73
  74         /* global data is already setup, no allocation yet */
  75         gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
  76         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
  77         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
  78
  79         /* Create early page tables */
  80         setup_pgtables();
  81
  82         /* point TTBR to the new table */
  83         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
  84                           get_tcr(el, NULL, NULL) &
  85                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
  86                           MEMORY_ATTRIBUTES);
  87
  88         set_sctlr(get_sctlr() | CR_M);
  89 }
  90
  91 static void fix_pcie_mmu_map(void)
  92 {
  93 #ifdef CONFIG_ARCH_LS2080A
  94         unsigned int i;
  95         u32 svr, ver;
  96         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  97
  98         svr = gur_in32(&gur->svr);
  99         ver = SVR_SOC_VER(svr);
 100
 101         /* Fix PCIE base and size for LS2088A */
 102         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 103             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 104             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 105                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 106                         switch (final_map[i].phys) {
 107                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 108                                 final_map[i].phys = 0x2000000000ULL;
 109                                 final_map[i].virt = 0x2000000000ULL;
 110                                 final_map[i].size = 0x800000000ULL;
 111                                 break;
 112                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 113                                 final_map[i].phys = 0x2800000000ULL;
 114                                 final_map[i].virt = 0x2800000000ULL;
 115                                 final_map[i].size = 0x800000000ULL;
 116                                 break;
 117                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 118                                 final_map[i].phys = 0x3000000000ULL;
 119                                 final_map[i].virt = 0x3000000000ULL;
 120                                 final_map[i].size = 0x800000000ULL;
 121                                 break;
 122                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 123                                 final_map[i].phys = 0x3800000000ULL;
 124                                 final_map[i].virt = 0x3800000000ULL;
 125                                 final_map[i].size = 0x800000000ULL;
 126                                 break;
 127                         default:
 128                                 break;
 129                         }
 130                 }
 131         }
 132 #endif
 133 }
 134
 135 /*
 136  * The final tables look similar to early tables, but different in detail.
 137  * These tables are in DRAM. Sub tables are added to enable cache for
 138  * QBMan and OCRAM.
 139  *
 140  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 141  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 142  */
 143 static inline void final_mmu_setup(void)
 144 {
 145         u64 tlb_addr_save = gd->arch.tlb_addr;
 146         unsigned int el = current_el();
 147         int index;
 148
 149         /* fix the final_map before filling in the block entries */
 150         fix_pcie_mmu_map();
 151
 152         mem_map = final_map;
 153
 154         /* Update mapping for DDR to actual size */
 155         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 156                 /*
 157                  * Find the entry for DDR mapping and update the address and
 158                  * size. Zero-sized mapping will be skipped when creating MMU
 159                  * table.
 160                  */
 161                 switch (final_map[index].virt) {
 162                 case CONFIG_SYS_FSL_DRAM_BASE1:
 163                         final_map[index].virt = gd->bd->bi_dram[0].start;
 164                         final_map[index].phys = gd->bd->bi_dram[0].start;
 165                         final_map[index].size = gd->bd->bi_dram[0].size;
 166                         break;
 167 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 168                 case CONFIG_SYS_FSL_DRAM_BASE2:
 169 #if (CONFIG_NR_DRAM_BANKS >= 2)
 170                         final_map[index].virt = gd->bd->bi_dram[1].start;
 171                         final_map[index].phys = gd->bd->bi_dram[1].start;
 172                         final_map[index].size = gd->bd->bi_dram[1].size;
 173 #else
 174                         final_map[index].size = 0;
 175 #endif
 176                 break;
 177 #endif
 178 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 179                 case CONFIG_SYS_FSL_DRAM_BASE3:
 180 #if (CONFIG_NR_DRAM_BANKS >= 3)
 181                         final_map[index].virt = gd->bd->bi_dram[2].start;
 182                         final_map[index].phys = gd->bd->bi_dram[2].start;
 183                         final_map[index].size = gd->bd->bi_dram[2].size;
 184 #else
 185                         final_map[index].size = 0;
 186 #endif
 187                 break;
 188 #endif
 189                 default:
 190                         break;
 191                 }
 192         }
 193
 194 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 195         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 196                 if (el == 3) {
 197                         /*
 198                          * Only use gd->arch.secure_ram if the address is
 199                          * recalculated. Align to 4KB for MMU table.
 200                          */
 201                         /* put page tables in secure ram */
 202                         index = ARRAY_SIZE(final_map) - 2;
 203                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 204                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 205                         final_map[index].phys = final_map[index].virt;
 206                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 207                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 208                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 209                         tlb_addr_save = gd->arch.tlb_addr;
 210                 } else {
 211                         /* Use allocated (board_f.c) memory for TLB */
 212                         tlb_addr_save = gd->arch.tlb_allocated;
 213                         gd->arch.tlb_addr = tlb_addr_save;
 214                 }
 215         }
 216 #endif
 217
 218         /* Reset the fill ptr */
 219         gd->arch.tlb_fillptr = tlb_addr_save;
 220
 221         /* Create normal system page tables */
 222         setup_pgtables();
 223
 224         /* Create emergency page tables */
 225         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 226         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 227         setup_pgtables();
 228         gd->arch.tlb_addr = tlb_addr_save;
 229
 230         /* Disable cache and MMU */
 231         dcache_disable();       /* TLBs are invalidated */
 232         invalidate_icache_all();
 233
 234         /* point TTBR to the new table */
 235         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 236                           MEMORY_ATTRIBUTES);
 237
 238         set_sctlr(get_sctlr() | CR_M);
 239 }
 240
 241 u64 get_page_table_size(void)
 242 {
 243         return 0x10000;
 244 }
 245
 246 int arch_cpu_init(void)
 247 {
 248         /*
 249          * This function is called before U-Boot relocates itself to speed up
 250          * on system running. It is not necessary to run if performance is not
 251          * critical. Skip if MMU is already enabled by SPL or other means.
 252          */
 253         if (get_sctlr() & CR_M)
 254                 return 0;
 255
 256         icache_enable();
 257         __asm_invalidate_dcache_all();
 258         __asm_invalidate_tlb_all();
 259         early_mmu_setup();
 260         set_sctlr(get_sctlr() | CR_C);
 261         return 0;
 262 }
 263
 264 void mmu_setup(void)
 265 {
 266         final_mmu_setup();
 267 }
 268
 269 /*
 270  * This function is called from common/board_r.c.
 271  * It recreates MMU table in main memory.
 272  */
 273 void enable_caches(void)
 274 {
 275         mmu_setup();
 276         __asm_invalidate_tlb_all();
 277         icache_enable();
 278         dcache_enable();
 279 }
 280 #endif
 281
 282 u32 initiator_type(u32 cluster, int init_id)
 283 {
 284         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 285         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 286         u32 type = 0;
 287
 288         type = gur_in32(&gur->tp_ityp[idx]);
 289         if (type & TP_ITYP_AV)
 290                 return type;
 291
 292         return 0;
 293 }
 294
 295 u32 cpu_pos_mask(void)
 296 {
 297         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 298         int i = 0;
 299         u32 cluster, type, mask = 0;
 300
 301         do {
 302                 int j;
 303
 304                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 305                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 306                         type = initiator_type(cluster, j);
 307                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 308                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 309                 }
 310                 i++;
 311         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 312
 313         return mask;
 314 }
 315
 316 u32 cpu_mask(void)
 317 {
 318         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 319         int i = 0, count = 0;
 320         u32 cluster, type, mask = 0;
 321
 322         do {
 323                 int j;
 324
 325                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 326                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 327                         type = initiator_type(cluster, j);
 328                         if (type) {
 329                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 330                                         mask |= 1 << count;
 331                                 count++;
 332                         }
 333                 }
 334                 i++;
 335         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 336
 337         return mask;
 338 }
 339
 340 /*
 341  * Return the number of cores on this SOC.
 342  */
 343 int cpu_numcores(void)
 344 {
 345         return hweight32(cpu_mask());
 346 }
 347
 348 int fsl_qoriq_core_to_cluster(unsigned int core)
 349 {
 350         struct ccsr_gur __iomem *gur =
 351                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 352         int i = 0, count = 0;
 353         u32 cluster;
 354
 355         do {
 356                 int j;
 357
 358                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 359                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 360                         if (initiator_type(cluster, j)) {
 361                                 if (count == core)
 362                                         return i;
 363                                 count++;
 364                         }
 365                 }
 366                 i++;
 367         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 368
 369         return -1;      /* cannot identify the cluster */
 370 }
 371
 372 u32 fsl_qoriq_core_to_type(unsigned int core)
 373 {
 374         struct ccsr_gur __iomem *gur =
 375                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 376         int i = 0, count = 0;
 377         u32 cluster, type;
 378
 379         do {
 380                 int j;
 381
 382                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 383                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 384                         type = initiator_type(cluster, j);
 385                         if (type) {
 386                                 if (count == core)
 387                                         return type;
 388                                 count++;
 389                         }
 390                 }
 391                 i++;
 392         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 393
 394         return -1;      /* cannot identify the cluster */
 395 }
 396
 397 #ifndef CONFIG_FSL_LSCH3
 398 uint get_svr(void)
 399 {
 400         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 401
 402         return gur_in32(&gur->svr);
 403 }
 404 #endif
 405
 406 #ifdef CONFIG_DISPLAY_CPUINFO
 407 int print_cpuinfo(void)
 408 {
 409         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 410         struct sys_info sysinfo;
 411         char buf[32];
 412         unsigned int i, core;
 413         u32 type, rcw, svr = gur_in32(&gur->svr);
 414
 415         puts("SoC: ");
 416
 417         cpu_name(buf);
 418         printf(" %s (0x%x)\n", buf, svr);
 419         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 420         get_sys_info(&sysinfo);
 421         puts("Clock Configuration:");
 422         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 423                 if (!(i % 3))
 424                         puts("\n       ");
 425                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
 426                 printf("CPU%d(%s):%-4s MHz  ", core,
 427                        type == TY_ITYP_VER_A7 ? "A7 " :
 428                        (type == TY_ITYP_VER_A53 ? "A53" :
 429                        (type == TY_ITYP_VER_A57 ? "A57" :
 430                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
 431                        strmhz(buf, sysinfo.freq_processor[core]));
 432         }
 433         /* Display platform clock as Bus frequency. */
 434         printf("\n       Bus:      %-4s MHz  ",
 435                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
 436         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
 437 #ifdef CONFIG_SYS_DPAA_FMAN
 438         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 439 #endif
 440 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 441         if (soc_has_dp_ddr()) {
 442                 printf("     DP-DDR:   %-4s MT/s",
 443                        strmhz(buf, sysinfo.freq_ddrbus2));
 444         }
 445 #endif
 446         puts("\n");
 447
 448         /*
 449          * Display the RCW, so that no one gets confused as to what RCW
 450          * we're actually using for this boot.
 451          */
 452         puts("Reset Configuration Word (RCW):");
 453         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
 454                 rcw = gur_in32(&gur->rcwsr[i]);
 455                 if ((i % 4) == 0)
 456                         printf("\n       %08x:", i * 4);
 457                 printf(" %08x", rcw);
 458         }
 459         puts("\n");
 460
 461         return 0;
 462 }
 463 #endif
 464
 465 #ifdef CONFIG_FSL_ESDHC
 466 int cpu_mmc_init(bd_t *bis)
 467 {
 468         return fsl_esdhc_mmc_init(bis);
 469 }
 470 #endif
 471
 472 int cpu_eth_init(bd_t *bis)
 473 {
 474         int error = 0;
 475
 476 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 477         error = fsl_mc_ldpaa_init(bis);
 478 #endif
 479 #ifdef CONFIG_FMAN_ENET
 480         fm_standard_init(bis);
 481 #endif
 482         return error;
 483 }
 484
 485 static inline int check_psci(void)
 486 {
 487         unsigned int psci_ver;
 488
 489         psci_ver = sec_firmware_support_psci_version();
 490         if (psci_ver == PSCI_INVALID_VER)
 491                 return 1;
 492
 493         return 0;
 494 }
 495
 496 int arch_early_init_r(void)
 497 {
 498 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 499         u32 svr_dev_id;
 500         /*
 501          * erratum A009635 is valid only for LS2080A SoC and
 502          * its personalitiesi
 503          */
 504         svr_dev_id = get_svr() >> 16;
 505         if (svr_dev_id == SVR_DEV_LS2080A)
 506                 erratum_a009635();
 507 #endif
 508 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
 509         erratum_a009942_check_cpo();
 510 #endif
 511         if (check_psci()) {
 512                 debug("PSCI: PSCI does not exist.\n");
 513
 514                 /* if PSCI does not exist, boot secondary cores here */
 515                 if (fsl_layerscape_wake_seconday_cores())
 516                         printf("Did not wake secondary cores\n");
 517         }
 518
 519 #ifdef CONFIG_SYS_HAS_SERDES
 520         fsl_serdes_init();
 521 #endif
 522 #ifdef CONFIG_FMAN_ENET
 523         fman_enet_init();
 524 #endif
 525         return 0;
 526 }
 527
 528 int timer_init(void)
 529 {
 530         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 531 #ifdef CONFIG_FSL_LSCH3
 532         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 533 #endif
 534 #ifdef CONFIG_ARCH_LS2080A
 535         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
 536         u32 svr_dev_id;
 537 #endif
 538 #ifdef COUNTER_FREQUENCY_REAL
 539         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 540
 541         /* Update with accurate clock frequency */
 542         if (current_el() == 3)
 543                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
 544 #endif
 545
 546 #ifdef CONFIG_FSL_LSCH3
 547         /* Enable timebase for all clusters.
 548          * It is safe to do so even some clusters are not enabled.
 549          */
 550         out_le32(cltbenr, 0xf);
 551 #endif
 552
 553 #ifdef CONFIG_ARCH_LS2080A
 554         /*
 555          * In certain Layerscape SoCs, the clock for each core's
 556          * has an enable bit in the PMU Physical Core Time Base Enable
 557          * Register (PCTBENR), which allows the watchdog to operate.
 558          */
 559         setbits_le32(pctbenr, 0xff);
 560         /*
 561          * For LS2080A SoC and its personalities, timer controller
 562          * offset is different
 563          */
 564         svr_dev_id = get_svr() >> 16;
 565         if (svr_dev_id == SVR_DEV_LS2080A)
 566                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
 567
 568 #endif
 569
 570         /* Enable clock for timer
 571          * This is a global setting.
 572          */
 573         out_le32(cntcr, 0x1);
 574
 575         return 0;
 576 }
 577
 578 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
 579
 580 void __efi_runtime reset_cpu(ulong addr)
 581 {
 582         u32 val;
 583
 584         /* Raise RESET_REQ_B */
 585         val = scfg_in32(rstcr);
 586         val |= 0x02;
 587         scfg_out32(rstcr, val);
 588 }
 589
 590 #ifdef CONFIG_EFI_LOADER
 591
 592 void __efi_runtime EFIAPI efi_reset_system(
 593                        enum efi_reset_type reset_type,
 594                        efi_status_t reset_status,
 595                        unsigned long data_size, void *reset_data)
 596 {
 597         switch (reset_type) {
 598         case EFI_RESET_COLD:
 599         case EFI_RESET_WARM:
 600                 reset_cpu(0);
 601                 break;
 602         case EFI_RESET_SHUTDOWN:
 603                 /* Nothing we can do */
 604                 break;
 605         }
 606
 607         while (1) { }
 608 }
 609
 610 void efi_reset_system_init(void)
 611 {
 612        efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
 613 }
 614
 615 #endif
 616
 617 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
 618 {
 619         phys_size_t ram_top = ram_size;
 620
 621 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 622         /* The start address of MC reserved memory needs to be aligned. */
 623         ram_top -= mc_get_dram_block_size();
 624         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
 625 #endif
 626
 627         return ram_size - ram_top;
 628 }
 629
 630 phys_size_t get_effective_memsize(void)
 631 {
 632         phys_size_t ea_size, rem = 0;
 633
 634         /*
 635          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
 636          * first region is 2GB space at 0x8000_0000. If the memory extends to
 637          * the second region (or the third region if applicable), the secure
 638          * memory and Management Complex (MC) memory should be put into the
 639          * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED
 640          * is set to the size of first region so U-Boot doesn't relocate itself
 641          * into higher address. Should DDR be configured to skip the first
 642          * region, this function needs to be adjusted.
 643          */
 644         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
 645                 ea_size = CONFIG_MAX_MEM_MAPPED;
 646                 rem = gd->ram_size - ea_size;
 647         } else {
 648                 ea_size = gd->ram_size;
 649         }
 650
 651 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 652         /* Check if we have enough space for secure memory */
 653         if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) {
 654                 rem -= CONFIG_SYS_MEM_RESERVE_SECURE;
 655         } else {
 656                 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) {
 657                         ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 658                         rem = 0;        /* Presume MC requires more memory */
 659                 } else {
 660                         printf("Error: No enough space for secure memory.\n");
 661                 }
 662         }
 663 #endif
 664         /* Check if we have enough memory for MC */
 665         if (rem < board_reserve_ram_top(rem)) {
 666                 /* Not enough memory in high region to reserve */
 667                 if (ea_size > board_reserve_ram_top(rem))
 668                         ea_size -= board_reserve_ram_top(rem);
 669                 else
 670                         printf("Error: No enough space for reserved memory.\n");
 671         }
 672
 673         return ea_size;
 674 }
 675
 676 int dram_init_banksize(void)
 677 {
 678 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 679         phys_size_t dp_ddr_size;
 680 #endif
 681
 682         /*
 683          * gd->ram_size has the total size of DDR memory, less reserved secure
 684          * memory. The DDR extends from low region to high region(s) presuming
 685          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
 686          * the location of secure memory. gd->arch.resv_ram tracks the location
 687          * of reserved memory for Management Complex (MC).
 688          */
 689         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 690         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
 691                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
 692                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 693                 gd->bd->bi_dram[1].size = gd->ram_size -
 694                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
 695 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 696                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
 697                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
 698                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
 699                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
 700                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
 701                 }
 702 #endif
 703         } else {
 704                 gd->bd->bi_dram[0].size = gd->ram_size;
 705         }
 706 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 707 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 708         if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
 709                 gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 710                 gd->arch.secure_ram = gd->bd->bi_dram[2].start +
 711                                       gd->bd->bi_dram[2].size;
 712                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 713                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 714         } else
 715 #endif
 716         {
 717                 if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
 718                         gd->bd->bi_dram[1].size -=
 719                                         CONFIG_SYS_MEM_RESERVE_SECURE;
 720                         gd->arch.secure_ram = gd->bd->bi_dram[1].start +
 721                                               gd->bd->bi_dram[1].size;
 722                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 723                         gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 724                 } else if (gd->bd->bi_dram[0].size >
 725                                         CONFIG_SYS_MEM_RESERVE_SECURE) {
 726                         gd->bd->bi_dram[0].size -=
 727                                         CONFIG_SYS_MEM_RESERVE_SECURE;
 728                         gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 729                                               gd->bd->bi_dram[0].size;
 730                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 731                         gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 732                 }
 733         }
 734 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
 735
 736 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 737         /* Assign memory for MC */
 738 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 739         if (gd->bd->bi_dram[2].size >=
 740             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
 741                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
 742                             gd->bd->bi_dram[2].size -
 743                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
 744         } else
 745 #endif
 746         {
 747                 if (gd->bd->bi_dram[1].size >=
 748                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
 749                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
 750                                 gd->bd->bi_dram[1].size -
 751                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
 752                 } else if (gd->bd->bi_dram[0].size >
 753                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
 754                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
 755                                 gd->bd->bi_dram[0].size -
 756                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
 757                 }
 758         }
 759 #endif  /* CONFIG_FSL_MC_ENET */
 760
 761 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 762 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 763 #error "This SoC shouldn't have DP DDR"
 764 #endif
 765         if (soc_has_dp_ddr()) {
 766                 /* initialize DP-DDR here */
 767                 puts("DP-DDR:  ");
 768                 /*
 769                  * DDR controller use 0 as the base address for binding.
 770                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 771                  */
 772                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
 773                                           CONFIG_DP_DDR_CTRL,
 774                                           CONFIG_DP_DDR_NUM_CTRLS,
 775                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
 776                                           NULL, NULL, NULL);
 777                 if (dp_ddr_size) {
 778                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
 779                         gd->bd->bi_dram[2].size = dp_ddr_size;
 780                 } else {
 781                         puts("Not detected");
 782                 }
 783         }
 784 #endif
 785
 786         return 0;
 787 }
 788
 789 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
 790 void efi_add_known_memory(void)
 791 {
 792         int i;
 793         phys_addr_t ram_start, start;
 794         phys_size_t ram_size;
 795         u64 pages;
 796
 797         /* Add RAM */
 798         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 799 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 800 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 801 #error "This SoC shouldn't have DP DDR"
 802 #endif
 803                 if (i == 2)
 804                         continue;       /* skip DP-DDR */
 805 #endif
 806                 ram_start = gd->bd->bi_dram[i].start;
 807                 ram_size = gd->bd->bi_dram[i].size;
 808 #ifdef CONFIG_RESV_RAM
 809                 if (gd->arch.resv_ram >= ram_start &&
 810                     gd->arch.resv_ram < ram_start + ram_size)
 811                         ram_size = gd->arch.resv_ram - ram_start;
 812 #endif
 813                 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
 814                 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
 815
 816                 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
 817                                    false);
 818         }
 819 }
 820 #endif
 821
 822 /*
 823  * Before DDR size is known, early MMU table have DDR mapped as device memory
 824  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
 825  * needs to be set for these mappings.
 826  * If a special case configures DDR with holes in the mapping, the holes need
 827  * to be marked as invalid. This is not implemented in this function.
 828  */
 829 void update_early_mmu_table(void)
 830 {
 831         if (!gd->arch.tlb_addr)
 832                 return;
 833
 834         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
 835                 mmu_change_region_attr(
 836                                         CONFIG_SYS_SDRAM_BASE,
 837                                         gd->ram_size,
 838                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
 839                                         PTE_BLOCK_OUTER_SHARE           |
 840                                         PTE_BLOCK_NS                    |
 841                                         PTE_TYPE_VALID);
 842         } else {
 843                 mmu_change_region_attr(
 844                                         CONFIG_SYS_SDRAM_BASE,
 845                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
 846                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
 847                                         PTE_BLOCK_OUTER_SHARE           |
 848                                         PTE_BLOCK_NS                    |
 849                                         PTE_TYPE_VALID);
 850 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 851 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
 852 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
 853 #endif
 854                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
 855                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
 856                         mmu_change_region_attr(
 857                                         CONFIG_SYS_DDR_BLOCK2_BASE,
 858                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
 859                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
 860                                         PTE_BLOCK_OUTER_SHARE           |
 861                                         PTE_BLOCK_NS                    |
 862                                         PTE_TYPE_VALID);
 863                         mmu_change_region_attr(
 864                                         CONFIG_SYS_DDR_BLOCK3_BASE,
 865                                         gd->ram_size -
 866                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
 867                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
 868                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
 869                                         PTE_BLOCK_OUTER_SHARE           |
 870                                         PTE_BLOCK_NS                    |
 871                                         PTE_TYPE_VALID);
 872                 } else
 873 #endif
 874                 {
 875                         mmu_change_region_attr(
 876                                         CONFIG_SYS_DDR_BLOCK2_BASE,
 877                                         gd->ram_size -
 878                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
 879                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
 880                                         PTE_BLOCK_OUTER_SHARE           |
 881                                         PTE_BLOCK_NS                    |
 882                                         PTE_TYPE_VALID);
 883                 }
 884         }
 885 }
 886
 887 __weak int dram_init(void)
 888 {
 889         fsl_initdram();
 890 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 891         /* This will break-before-make MMU for DDR */
 892         update_early_mmu_table();
 893 #endif
 894
 895         return 0;
 896 }