arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2019 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <init.h>
  12 #include <hang.h>
  13 #include <log.h>
  14 #include <net.h>
  15 #include <vsprintf.h>
  16 #include <asm/cache.h>
  17 #include <asm/io.h>
  18 #include <linux/errno.h>
  19 #include <asm/system.h>
  20 #include <fm_eth.h>
  21 #include <asm/armv8/mmu.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/fsl_serdes.h>
  24 #include <asm/arch/soc.h>
  25 #include <asm/arch/cpu.h>
  26 #include <asm/arch/speed.h>
  27 #include <fsl_immap.h>
  28 #include <asm/arch/mp.h>
  29 #include <efi_loader.h>
  30 #include <fsl-mc/fsl_mc.h>
  31 #ifdef CONFIG_FSL_ESDHC
  32 #include <fsl_esdhc.h>
  33 #endif
  34 #include <asm/armv8/sec_firmware.h>
  35 #ifdef CONFIG_SYS_FSL_DDR
  36 #include <fsl_ddr.h>
  37 #endif
  38 #include <asm/arch/clock.h>
  39 #include <hwconfig.h>
  40 #include <fsl_qbman.h>
  41
  42 #ifdef CONFIG_TFABOOT
  43 #include <env_internal.h>
  44 #ifdef CONFIG_CHAIN_OF_TRUST
  45 #include <fsl_validate.h>
  46 #endif
  47 #endif
  48 #include <linux/mii.h>
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 static struct cpu_type cpu_type_list[] = {
  53         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  54         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  55         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  56         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  57         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  58         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  59         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  60         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  61         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  62         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  63         CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
  64         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  65         CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
  66         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  67         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  68         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  69         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  70         CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
  71         CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
  72         CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
  73         CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
  74         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  75         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  76         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  77         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  78         CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
  79         CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
  80         CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
  81 };
  82
  83 #define EARLY_PGTABLE_SIZE 0x5000
  84 static struct mm_region early_map[] = {
  85 #ifdef CONFIG_FSL_LSCH3
  86         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  87           CONFIG_SYS_FSL_CCSR_SIZE,
  88           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  89           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  90         },
  91         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  92           SYS_FSL_OCRAM_SPACE_SIZE,
  93           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  94         },
  95         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
  96           CONFIG_SYS_FSL_QSPI_SIZE1,
  97           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
  98 #ifdef CONFIG_FSL_IFC
  99         /* For IFC Region #1, only the first 4MB is cache-enabled */
 100         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
 101           CONFIG_SYS_FSL_IFC_SIZE1_1,
 102           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 103         },
 104         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 105           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 106           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 107           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 108         },
 109         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 110           CONFIG_SYS_FSL_IFC_SIZE1,
 111           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 112         },
 113 #endif
 114         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 115           CONFIG_SYS_FSL_DRAM_SIZE1,
 116 #if defined(CONFIG_TFABOOT) || \
 117         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 118           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 119 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 120           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 121 #endif
 122           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 123         },
 124 #ifdef CONFIG_FSL_IFC
 125         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 126         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 127           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 128           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 129         },
 130 #endif
 131         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 132           CONFIG_SYS_FSL_DCSR_SIZE,
 133           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 134           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 135         },
 136         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 137           CONFIG_SYS_FSL_DRAM_SIZE2,
 138           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 139           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 140         },
 141 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 142         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 143           CONFIG_SYS_FSL_DRAM_SIZE3,
 144           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 145           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 146         },
 147 #endif
 148 #elif defined(CONFIG_FSL_LSCH2)
 149         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 150           CONFIG_SYS_FSL_CCSR_SIZE,
 151           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 152           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 153         },
 154         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 155           SYS_FSL_OCRAM_SPACE_SIZE,
 156           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 157         },
 158         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 159           CONFIG_SYS_FSL_DCSR_SIZE,
 160           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 161           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 162         },
 163         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 164           CONFIG_SYS_FSL_QSPI_SIZE,
 165           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 166         },
 167 #ifdef CONFIG_FSL_IFC
 168         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 169           CONFIG_SYS_FSL_IFC_SIZE,
 170           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 171         },
 172 #endif
 173         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 174           CONFIG_SYS_FSL_DRAM_SIZE1,
 175 #if defined(CONFIG_TFABOOT) || \
 176         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 177           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 178 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 179           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 180 #endif
 181           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 182         },
 183         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 184           CONFIG_SYS_FSL_DRAM_SIZE2,
 185           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 186           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 187         },
 188 #endif
 189         {},     /* list terminator */
 190 };
 191
 192 static struct mm_region final_map[] = {
 193 #ifdef CONFIG_FSL_LSCH3
 194         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 195           CONFIG_SYS_FSL_CCSR_SIZE,
 196           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 197           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 198         },
 199         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 200           SYS_FSL_OCRAM_SPACE_SIZE,
 201           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 202         },
 203         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 204           CONFIG_SYS_FSL_DRAM_SIZE1,
 205           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 206           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 207         },
 208         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 209           CONFIG_SYS_FSL_QSPI_SIZE1,
 210           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 211           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 212         },
 213         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 214           CONFIG_SYS_FSL_QSPI_SIZE2,
 215           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 216           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 217         },
 218 #ifdef CONFIG_FSL_IFC
 219         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 220           CONFIG_SYS_FSL_IFC_SIZE2,
 221           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 222           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 223         },
 224 #endif
 225         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 226           CONFIG_SYS_FSL_DCSR_SIZE,
 227           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 228           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 229         },
 230         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 231           CONFIG_SYS_FSL_MC_SIZE,
 232           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 233           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 234         },
 235         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 236           CONFIG_SYS_FSL_NI_SIZE,
 237           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 238           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 239         },
 240         /* For QBMAN portal, only the first 64MB is cache-enabled */
 241         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 242           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 243           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 244           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 245         },
 246         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 247           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 248           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 249           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 250           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 251         },
 252         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 253           CONFIG_SYS_PCIE1_PHYS_SIZE,
 254           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 255           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 256         },
 257         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 258           CONFIG_SYS_PCIE2_PHYS_SIZE,
 259           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 260           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 261         },
 262 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 263         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 264           CONFIG_SYS_PCIE3_PHYS_SIZE,
 265           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 266           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 267         },
 268 #endif
 269 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 270         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 271           CONFIG_SYS_PCIE4_PHYS_SIZE,
 272           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 273           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 274         },
 275 #endif
 276 #ifdef SYS_PCIE5_PHYS_ADDR
 277         { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
 278           SYS_PCIE5_PHYS_SIZE,
 279           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 280           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 281         },
 282 #endif
 283 #ifdef SYS_PCIE6_PHYS_ADDR
 284         { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
 285           SYS_PCIE6_PHYS_SIZE,
 286           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 287           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 288         },
 289 #endif
 290         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 291           CONFIG_SYS_FSL_WRIOP1_SIZE,
 292           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 293           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 294         },
 295         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 296           CONFIG_SYS_FSL_AIOP1_SIZE,
 297           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 298           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 299         },
 300         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 301           CONFIG_SYS_FSL_PEBUF_SIZE,
 302           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 303           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 304         },
 305         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 306           CONFIG_SYS_FSL_DRAM_SIZE2,
 307           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 308           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 309         },
 310 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 311         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 312           CONFIG_SYS_FSL_DRAM_SIZE3,
 313           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 314           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 315         },
 316 #endif
 317 #elif defined(CONFIG_FSL_LSCH2)
 318         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 319           CONFIG_SYS_FSL_BOOTROM_SIZE,
 320           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 321           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 322         },
 323         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 324           CONFIG_SYS_FSL_CCSR_SIZE,
 325           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 326           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 327         },
 328         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 329           SYS_FSL_OCRAM_SPACE_SIZE,
 330           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 331         },
 332         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 333           CONFIG_SYS_FSL_DCSR_SIZE,
 334           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 335           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 336         },
 337         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 338           CONFIG_SYS_FSL_QSPI_SIZE,
 339           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 340           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 341         },
 342 #ifdef CONFIG_FSL_IFC
 343         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 344           CONFIG_SYS_FSL_IFC_SIZE,
 345           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 346         },
 347 #endif
 348         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 349           CONFIG_SYS_FSL_DRAM_SIZE1,
 350           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 351           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 352         },
 353         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 354           CONFIG_SYS_FSL_QBMAN_SIZE,
 355           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 356           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 357         },
 358         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 359           CONFIG_SYS_FSL_DRAM_SIZE2,
 360           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 361           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 362         },
 363         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 364           CONFIG_SYS_PCIE1_PHYS_SIZE,
 365           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 366           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 367         },
 368         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 369           CONFIG_SYS_PCIE2_PHYS_SIZE,
 370           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 371           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 372         },
 373 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 374         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 375           CONFIG_SYS_PCIE3_PHYS_SIZE,
 376           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 377           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 378         },
 379 #endif
 380         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 381           CONFIG_SYS_FSL_DRAM_SIZE3,
 382           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 383           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 384         },
 385 #endif
 386 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 387         {},     /* space holder for secure mem */
 388 #endif
 389         {},
 390 };
 391
 392 struct mm_region *mem_map = early_map;
 393
 394 void cpu_name(char *name)
 395 {
 396         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 397         unsigned int i, svr, ver;
 398
 399         svr = gur_in32(&gur->svr);
 400         ver = SVR_SOC_VER(svr);
 401
 402         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 403                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 404                         strcpy(name, cpu_type_list[i].name);
 405 #ifdef CONFIG_ARCH_LX2160A
 406                         if (IS_C_PROCESSOR(svr))
 407                                 strcat(name, "C");
 408 #endif
 409
 410                         if (IS_E_PROCESSOR(svr))
 411                                 strcat(name, "E");
 412
 413                         sprintf(name + strlen(name), " Rev%d.%d",
 414                                 SVR_MAJ(svr), SVR_MIN(svr));
 415                         break;
 416                 }
 417
 418         if (i == ARRAY_SIZE(cpu_type_list))
 419                 strcpy(name, "unknown");
 420 }
 421
 422 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 423 /*
 424  * To start MMU before DDR is available, we create MMU table in SRAM.
 425  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 426  * levels of translation tables here to cover 40-bit address space.
 427  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 428  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 429  * Note, the debug print in cache_v8.c is not usable for debugging
 430  * these early MMU tables because UART is not yet available.
 431  */
 432 static inline void early_mmu_setup(void)
 433 {
 434         unsigned int el = current_el();
 435
 436         /* global data is already setup, no allocation yet */
 437         if (el == 3)
 438                 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 439         else
 440                 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 441         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 442         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 443
 444         /* Create early page tables */
 445         setup_pgtables();
 446
 447         /* point TTBR to the new table */
 448         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 449                           get_tcr(el, NULL, NULL) &
 450                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 451                           MEMORY_ATTRIBUTES);
 452
 453         set_sctlr(get_sctlr() | CR_M);
 454 }
 455
 456 static void fix_pcie_mmu_map(void)
 457 {
 458 #ifdef CONFIG_ARCH_LS2080A
 459         unsigned int i;
 460         u32 svr, ver;
 461         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 462
 463         svr = gur_in32(&gur->svr);
 464         ver = SVR_SOC_VER(svr);
 465
 466         /* Fix PCIE base and size for LS2088A */
 467         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 468             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 469             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 470                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 471                         switch (final_map[i].phys) {
 472                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 473                                 final_map[i].phys = 0x2000000000ULL;
 474                                 final_map[i].virt = 0x2000000000ULL;
 475                                 final_map[i].size = 0x800000000ULL;
 476                                 break;
 477                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 478                                 final_map[i].phys = 0x2800000000ULL;
 479                                 final_map[i].virt = 0x2800000000ULL;
 480                                 final_map[i].size = 0x800000000ULL;
 481                                 break;
 482 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 483                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 484                                 final_map[i].phys = 0x3000000000ULL;
 485                                 final_map[i].virt = 0x3000000000ULL;
 486                                 final_map[i].size = 0x800000000ULL;
 487                                 break;
 488 #endif
 489 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 490                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 491                                 final_map[i].phys = 0x3800000000ULL;
 492                                 final_map[i].virt = 0x3800000000ULL;
 493                                 final_map[i].size = 0x800000000ULL;
 494                                 break;
 495 #endif
 496                         default:
 497                                 break;
 498                         }
 499                 }
 500         }
 501 #endif
 502 }
 503
 504 /*
 505  * The final tables look similar to early tables, but different in detail.
 506  * These tables are in DRAM. Sub tables are added to enable cache for
 507  * QBMan and OCRAM.
 508  *
 509  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 510  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 511  */
 512 static inline void final_mmu_setup(void)
 513 {
 514         u64 tlb_addr_save = gd->arch.tlb_addr;
 515         unsigned int el = current_el();
 516         int index;
 517
 518         /* fix the final_map before filling in the block entries */
 519         fix_pcie_mmu_map();
 520
 521         mem_map = final_map;
 522
 523         /* Update mapping for DDR to actual size */
 524         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 525                 /*
 526                  * Find the entry for DDR mapping and update the address and
 527                  * size. Zero-sized mapping will be skipped when creating MMU
 528                  * table.
 529                  */
 530                 switch (final_map[index].virt) {
 531                 case CONFIG_SYS_FSL_DRAM_BASE1:
 532                         final_map[index].virt = gd->bd->bi_dram[0].start;
 533                         final_map[index].phys = gd->bd->bi_dram[0].start;
 534                         final_map[index].size = gd->bd->bi_dram[0].size;
 535                         break;
 536 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 537                 case CONFIG_SYS_FSL_DRAM_BASE2:
 538 #if (CONFIG_NR_DRAM_BANKS >= 2)
 539                         final_map[index].virt = gd->bd->bi_dram[1].start;
 540                         final_map[index].phys = gd->bd->bi_dram[1].start;
 541                         final_map[index].size = gd->bd->bi_dram[1].size;
 542 #else
 543                         final_map[index].size = 0;
 544 #endif
 545                 break;
 546 #endif
 547 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 548                 case CONFIG_SYS_FSL_DRAM_BASE3:
 549 #if (CONFIG_NR_DRAM_BANKS >= 3)
 550                         final_map[index].virt = gd->bd->bi_dram[2].start;
 551                         final_map[index].phys = gd->bd->bi_dram[2].start;
 552                         final_map[index].size = gd->bd->bi_dram[2].size;
 553 #else
 554                         final_map[index].size = 0;
 555 #endif
 556                 break;
 557 #endif
 558                 default:
 559                         break;
 560                 }
 561         }
 562
 563 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 564         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 565                 if (el == 3) {
 566                         /*
 567                          * Only use gd->arch.secure_ram if the address is
 568                          * recalculated. Align to 4KB for MMU table.
 569                          */
 570                         /* put page tables in secure ram */
 571                         index = ARRAY_SIZE(final_map) - 2;
 572                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 573                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 574                         final_map[index].phys = final_map[index].virt;
 575                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 576                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 577                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 578                         tlb_addr_save = gd->arch.tlb_addr;
 579                 } else {
 580                         /* Use allocated (board_f.c) memory for TLB */
 581                         tlb_addr_save = gd->arch.tlb_allocated;
 582                         gd->arch.tlb_addr = tlb_addr_save;
 583                 }
 584         }
 585 #endif
 586
 587         /* Reset the fill ptr */
 588         gd->arch.tlb_fillptr = tlb_addr_save;
 589
 590         /* Create normal system page tables */
 591         setup_pgtables();
 592
 593         /* Create emergency page tables */
 594         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 595         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 596         setup_pgtables();
 597         gd->arch.tlb_addr = tlb_addr_save;
 598
 599         /* Disable cache and MMU */
 600         dcache_disable();       /* TLBs are invalidated */
 601         invalidate_icache_all();
 602
 603         /* point TTBR to the new table */
 604         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 605                           MEMORY_ATTRIBUTES);
 606
 607         set_sctlr(get_sctlr() | CR_M);
 608 }
 609
 610 u64 get_page_table_size(void)
 611 {
 612         return 0x10000;
 613 }
 614
 615 int arch_cpu_init(void)
 616 {
 617         /*
 618          * This function is called before U-Boot relocates itself to speed up
 619          * on system running. It is not necessary to run if performance is not
 620          * critical. Skip if MMU is already enabled by SPL or other means.
 621          */
 622         if (get_sctlr() & CR_M)
 623                 return 0;
 624
 625         icache_enable();
 626         __asm_invalidate_dcache_all();
 627         __asm_invalidate_tlb_all();
 628         early_mmu_setup();
 629         set_sctlr(get_sctlr() | CR_C);
 630         return 0;
 631 }
 632
 633 void mmu_setup(void)
 634 {
 635         final_mmu_setup();
 636 }
 637
 638 /*
 639  * This function is called from common/board_r.c.
 640  * It recreates MMU table in main memory.
 641  */
 642 void enable_caches(void)
 643 {
 644         mmu_setup();
 645         __asm_invalidate_tlb_all();
 646         icache_enable();
 647         dcache_enable();
 648 }
 649 #endif  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 650
 651 #ifdef CONFIG_TFABOOT
 652 enum boot_src __get_boot_src(u32 porsr1)
 653 {
 654         enum boot_src src = BOOT_SOURCE_RESERVED;
 655         u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
 656 #if !defined(CONFIG_NXP_LSCH3_2)
 657         u32 val;
 658 #endif
 659         debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
 660
 661 #if defined(CONFIG_FSL_LSCH3)
 662 #if defined(CONFIG_NXP_LSCH3_2)
 663         switch (rcw_src) {
 664         case RCW_SRC_SDHC1_VAL:
 665                 src = BOOT_SOURCE_SD_MMC;
 666         break;
 667         case RCW_SRC_SDHC2_VAL:
 668                 src = BOOT_SOURCE_SD_MMC2;
 669         break;
 670         case RCW_SRC_I2C1_VAL:
 671                 src = BOOT_SOURCE_I2C1_EXTENDED;
 672         break;
 673         case RCW_SRC_FLEXSPI_NAND2K_VAL:
 674                 src = BOOT_SOURCE_XSPI_NAND;
 675         break;
 676         case RCW_SRC_FLEXSPI_NAND4K_VAL:
 677                 src = BOOT_SOURCE_XSPI_NAND;
 678         break;
 679         case RCW_SRC_RESERVED_1_VAL:
 680                 src = BOOT_SOURCE_RESERVED;
 681         break;
 682         case RCW_SRC_FLEXSPI_NOR_24B:
 683                 src = BOOT_SOURCE_XSPI_NOR;
 684         break;
 685         default:
 686                 src = BOOT_SOURCE_RESERVED;
 687         }
 688 #else
 689         val = rcw_src & RCW_SRC_TYPE_MASK;
 690         if (val == RCW_SRC_NOR_VAL) {
 691                 val = rcw_src & NOR_TYPE_MASK;
 692
 693                 switch (val) {
 694                 case NOR_16B_VAL:
 695                 case NOR_32B_VAL:
 696                         src = BOOT_SOURCE_IFC_NOR;
 697                 break;
 698                 default:
 699                         src = BOOT_SOURCE_RESERVED;
 700                 }
 701         } else {
 702                 /* RCW SRC Serial Flash */
 703                 val = rcw_src & RCW_SRC_SERIAL_MASK;
 704                 switch (val) {
 705                 case RCW_SRC_QSPI_VAL:
 706                 /* RCW SRC Serial NOR (QSPI) */
 707                         src = BOOT_SOURCE_QSPI_NOR;
 708                         break;
 709                 case RCW_SRC_SD_CARD_VAL:
 710                 /* RCW SRC SD Card */
 711                         src = BOOT_SOURCE_SD_MMC;
 712                         break;
 713                 case RCW_SRC_EMMC_VAL:
 714                 /* RCW SRC EMMC */
 715                         src = BOOT_SOURCE_SD_MMC;
 716                         break;
 717                 case RCW_SRC_I2C1_VAL:
 718                 /* RCW SRC I2C1 Extended */
 719                         src = BOOT_SOURCE_I2C1_EXTENDED;
 720                         break;
 721                 default:
 722                         src = BOOT_SOURCE_RESERVED;
 723                 }
 724         }
 725 #endif
 726 #elif defined(CONFIG_FSL_LSCH2)
 727         /* RCW SRC NAND */
 728         val = rcw_src & RCW_SRC_NAND_MASK;
 729         if (val == RCW_SRC_NAND_VAL) {
 730                 val = rcw_src & NAND_RESERVED_MASK;
 731                 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
 732                         src = BOOT_SOURCE_IFC_NAND;
 733
 734         } else {
 735                 /* RCW SRC NOR */
 736                 val = rcw_src & RCW_SRC_NOR_MASK;
 737                 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
 738                         src = BOOT_SOURCE_IFC_NOR;
 739                 } else {
 740                         switch (rcw_src) {
 741                         case QSPI_VAL1:
 742                         case QSPI_VAL2:
 743                                 src = BOOT_SOURCE_QSPI_NOR;
 744                                 break;
 745                         case SD_VAL:
 746                                 src = BOOT_SOURCE_SD_MMC;
 747                                 break;
 748                         default:
 749                                 src = BOOT_SOURCE_RESERVED;
 750                         }
 751                 }
 752         }
 753 #endif
 754
 755         if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
 756                 src = BOOT_SOURCE_QSPI_NOR;
 757
 758         debug("%s: src 0x%x\n", __func__, src);
 759         return src;
 760 }
 761
 762 enum boot_src get_boot_src(void)
 763 {
 764         struct pt_regs regs;
 765         u32 porsr1 = 0;
 766
 767 #if defined(CONFIG_FSL_LSCH3)
 768         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 769 #elif defined(CONFIG_FSL_LSCH2)
 770         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 771 #endif
 772
 773         if (current_el() == 2) {
 774                 regs.regs[0] = SIP_SVC_RCW;
 775
 776                 smc_call(&regs);
 777                 if (!regs.regs[0])
 778                         porsr1 = regs.regs[1];
 779         }
 780
 781         if (current_el() == 3 || !porsr1) {
 782 #ifdef CONFIG_FSL_LSCH3
 783                 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 784 #elif defined(CONFIG_FSL_LSCH2)
 785                 porsr1 = in_be32(&gur->porsr1);
 786 #endif
 787         }
 788
 789         debug("%s: porsr1 0x%x\n", __func__, porsr1);
 790
 791         return __get_boot_src(porsr1);
 792 }
 793
 794 #ifdef CONFIG_ENV_IS_IN_MMC
 795 int mmc_get_env_dev(void)
 796 {
 797         enum boot_src src = get_boot_src();
 798         int dev = CONFIG_SYS_MMC_ENV_DEV;
 799
 800         switch (src) {
 801         case BOOT_SOURCE_SD_MMC:
 802                 dev = 0;
 803                 break;
 804         case BOOT_SOURCE_SD_MMC2:
 805                 dev = 1;
 806                 break;
 807         default:
 808                 break;
 809         }
 810
 811         return dev;
 812 }
 813 #endif
 814
 815 enum env_location env_get_location(enum env_operation op, int prio)
 816 {
 817         enum boot_src src = get_boot_src();
 818         enum env_location env_loc = ENVL_NOWHERE;
 819
 820         if (prio)
 821                 return ENVL_UNKNOWN;
 822
 823 #ifdef  CONFIG_ENV_IS_NOWHERE
 824         return env_loc;
 825 #endif
 826
 827         switch (src) {
 828         case BOOT_SOURCE_IFC_NOR:
 829                 env_loc = ENVL_FLASH;
 830                 break;
 831         case BOOT_SOURCE_QSPI_NOR:
 832                 /* FALLTHROUGH */
 833         case BOOT_SOURCE_XSPI_NOR:
 834                 env_loc = ENVL_SPI_FLASH;
 835                 break;
 836         case BOOT_SOURCE_IFC_NAND:
 837                 /* FALLTHROUGH */
 838         case BOOT_SOURCE_QSPI_NAND:
 839                 /* FALLTHROUGH */
 840         case BOOT_SOURCE_XSPI_NAND:
 841                 env_loc = ENVL_NAND;
 842                 break;
 843         case BOOT_SOURCE_SD_MMC:
 844                 /* FALLTHROUGH */
 845         case BOOT_SOURCE_SD_MMC2:
 846                 env_loc =  ENVL_MMC;
 847                 break;
 848         case BOOT_SOURCE_I2C1_EXTENDED:
 849                 /* FALLTHROUGH */
 850         default:
 851                 break;
 852         }
 853
 854         return env_loc;
 855 }
 856 #endif  /* CONFIG_TFABOOT */
 857
 858 u32 initiator_type(u32 cluster, int init_id)
 859 {
 860         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 861         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 862         u32 type = 0;
 863
 864         type = gur_in32(&gur->tp_ityp[idx]);
 865         if (type & TP_ITYP_AV)
 866                 return type;
 867
 868         return 0;
 869 }
 870
 871 u32 cpu_pos_mask(void)
 872 {
 873         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 874         int i = 0;
 875         u32 cluster, type, mask = 0;
 876
 877         do {
 878                 int j;
 879
 880                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 881                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 882                         type = initiator_type(cluster, j);
 883                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 884                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 885                 }
 886                 i++;
 887         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 888
 889         return mask;
 890 }
 891
 892 u32 cpu_mask(void)
 893 {
 894         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 895         int i = 0, count = 0;
 896         u32 cluster, type, mask = 0;
 897
 898         do {
 899                 int j;
 900
 901                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 902                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 903                         type = initiator_type(cluster, j);
 904                         if (type) {
 905                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 906                                         mask |= 1 << count;
 907                                 count++;
 908                         }
 909                 }
 910                 i++;
 911         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 912
 913         return mask;
 914 }
 915
 916 /*
 917  * Return the number of cores on this SOC.
 918  */
 919 int cpu_numcores(void)
 920 {
 921         return hweight32(cpu_mask());
 922 }
 923
 924 int fsl_qoriq_core_to_cluster(unsigned int core)
 925 {
 926         struct ccsr_gur __iomem *gur =
 927                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 928         int i = 0, count = 0;
 929         u32 cluster;
 930
 931         do {
 932                 int j;
 933
 934                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 935                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 936                         if (initiator_type(cluster, j)) {
 937                                 if (count == core)
 938                                         return i;
 939                                 count++;
 940                         }
 941                 }
 942                 i++;
 943         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 944
 945         return -1;      /* cannot identify the cluster */
 946 }
 947
 948 u32 fsl_qoriq_core_to_type(unsigned int core)
 949 {
 950         struct ccsr_gur __iomem *gur =
 951                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 952         int i = 0, count = 0;
 953         u32 cluster, type;
 954
 955         do {
 956                 int j;
 957
 958                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 959                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 960                         type = initiator_type(cluster, j);
 961                         if (type) {
 962                                 if (count == core)
 963                                         return type;
 964                                 count++;
 965                         }
 966                 }
 967                 i++;
 968         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 969
 970         return -1;      /* cannot identify the cluster */
 971 }
 972
 973 #ifndef CONFIG_FSL_LSCH3
 974 uint get_svr(void)
 975 {
 976         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 977
 978         return gur_in32(&gur->svr);
 979 }
 980 #endif
 981
 982 #ifdef CONFIG_DISPLAY_CPUINFO
 983 int print_cpuinfo(void)
 984 {
 985         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 986         struct sys_info sysinfo;
 987         char buf[32];
 988         unsigned int i, core;
 989         u32 type, rcw, svr = gur_in32(&gur->svr);
 990
 991         puts("SoC: ");
 992
 993         cpu_name(buf);
 994         printf(" %s (0x%x)\n", buf, svr);
 995         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 996         get_sys_info(&sysinfo);
 997         puts("Clock Configuration:");
 998         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 999                 if (!(i % 3))
1000                         puts("\n       ");
1001                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
1002                 printf("CPU%d(%s):%-4s MHz  ", core,
1003                        type == TY_ITYP_VER_A7 ? "A7 " :
1004                        (type == TY_ITYP_VER_A53 ? "A53" :
1005                        (type == TY_ITYP_VER_A57 ? "A57" :
1006                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
1007                        strmhz(buf, sysinfo.freq_processor[core]));
1008         }
1009         /* Display platform clock as Bus frequency. */
1010         printf("\n       Bus:      %-4s MHz  ",
1011                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1012         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1013 #ifdef CONFIG_SYS_DPAA_FMAN
1014         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1015 #endif
1016 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1017         if (soc_has_dp_ddr()) {
1018                 printf("     DP-DDR:   %-4s MT/s",
1019                        strmhz(buf, sysinfo.freq_ddrbus2));
1020         }
1021 #endif
1022         puts("\n");
1023
1024         /*
1025          * Display the RCW, so that no one gets confused as to what RCW
1026          * we're actually using for this boot.
1027          */
1028         puts("Reset Configuration Word (RCW):");
1029         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1030                 rcw = gur_in32(&gur->rcwsr[i]);
1031                 if ((i % 4) == 0)
1032                         printf("\n       %08x:", i * 4);
1033                 printf(" %08x", rcw);
1034         }
1035         puts("\n");
1036
1037         return 0;
1038 }
1039 #endif
1040
1041 #ifdef CONFIG_FSL_ESDHC
1042 int cpu_mmc_init(bd_t *bis)
1043 {
1044         return fsl_esdhc_mmc_init(bis);
1045 }
1046 #endif
1047
1048 int cpu_eth_init(bd_t *bis)
1049 {
1050         int error = 0;
1051
1052 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1053         error = fsl_mc_ldpaa_init(bis);
1054 #endif
1055 #ifdef CONFIG_FMAN_ENET
1056         fm_standard_init(bis);
1057 #endif
1058         return error;
1059 }
1060
1061 static inline int check_psci(void)
1062 {
1063         unsigned int psci_ver;
1064
1065         psci_ver = sec_firmware_support_psci_version();
1066         if (psci_ver == PSCI_INVALID_VER)
1067                 return 1;
1068
1069         return 0;
1070 }
1071
1072 static void config_core_prefetch(void)
1073 {
1074         char *buf = NULL;
1075         char buffer[HWCONFIG_BUFFER_SIZE];
1076         const char *prefetch_arg = NULL;
1077         size_t arglen;
1078         unsigned int mask;
1079         struct pt_regs regs;
1080
1081         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1082                 buf = buffer;
1083         else
1084                 return;
1085
1086         prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1087                                          &arglen, buf);
1088
1089         if (prefetch_arg) {
1090                 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1091                 if (mask & 0x1) {
1092                         printf("Core0 prefetch can't be disabled\n");
1093                         return;
1094                 }
1095
1096 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1097                 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1098                 regs.regs[1] = mask;
1099                 smc_call(&regs);
1100
1101                 if (regs.regs[0])
1102                         printf("Prefetch disable config failed for mask ");
1103                 else
1104                         printf("Prefetch disable config passed for mask ");
1105                 printf("0x%x\n", mask);
1106         }
1107 }
1108
1109 #ifdef CONFIG_PCIE_ECAM_GENERIC
1110 __weak void set_ecam_icids(void)
1111 {
1112 }
1113 #endif
1114
1115 int arch_early_init_r(void)
1116 {
1117 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1118         u32 svr_dev_id;
1119         /*
1120          * erratum A009635 is valid only for LS2080A SoC and
1121          * its personalitiesi
1122          */
1123         svr_dev_id = get_svr();
1124         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1125                 erratum_a009635();
1126 #endif
1127 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1128         erratum_a009942_check_cpo();
1129 #endif
1130         if (check_psci()) {
1131                 debug("PSCI: PSCI does not exist.\n");
1132
1133                 /* if PSCI does not exist, boot secondary cores here */
1134                 if (fsl_layerscape_wake_seconday_cores())
1135                         printf("Did not wake secondary cores\n");
1136         }
1137
1138         config_core_prefetch();
1139
1140 #ifdef CONFIG_SYS_HAS_SERDES
1141         fsl_serdes_init();
1142 #endif
1143 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1144         /* some dpmacs in armv8a based freescale layerscape SOCs can be
1145          * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1146          * EC*_PMUX(rgmii) bits in RCW.
1147          * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1148          * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1149          * Now if a dpmac is enabled by serdes bits then it takes precedence
1150          * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
1151          * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
1152          * then the dpmac is SGMII and not RGMII.
1153          *
1154          * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
1155          * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
1156          * or not? if it is (fsl_serdes_init has already enabled the dpmac),
1157          * then don't enable it.
1158          */
1159         fsl_rgmii_init();
1160 #endif
1161 #ifdef CONFIG_FMAN_ENET
1162 #ifndef CONFIG_DM_ETH
1163         fman_enet_init();
1164 #endif
1165 #endif
1166 #ifdef CONFIG_SYS_DPAA_QBMAN
1167         setup_qbman_portals();
1168 #endif
1169 #ifdef CONFIG_PCIE_ECAM_GENERIC
1170         set_ecam_icids();
1171 #endif
1172         return 0;
1173 }
1174
1175 int timer_init(void)
1176 {
1177         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1178 #ifdef CONFIG_FSL_LSCH3
1179         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1180 #endif
1181 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1182         defined(CONFIG_ARCH_LS1028A)
1183         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1184         u32 svr_dev_id;
1185 #endif
1186 #ifdef COUNTER_FREQUENCY_REAL
1187         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1188
1189         /* Update with accurate clock frequency */
1190         if (current_el() == 3)
1191                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1192 #endif
1193
1194 #ifdef CONFIG_FSL_LSCH3
1195         /* Enable timebase for all clusters.
1196          * It is safe to do so even some clusters are not enabled.
1197          */
1198         out_le32(cltbenr, 0xf);
1199 #endif
1200
1201 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1202         defined(CONFIG_ARCH_LS1028A)
1203         /*
1204          * In certain Layerscape SoCs, the clock for each core's
1205          * has an enable bit in the PMU Physical Core Time Base Enable
1206          * Register (PCTBENR), which allows the watchdog to operate.
1207          */
1208         setbits_le32(pctbenr, 0xff);
1209         /*
1210          * For LS2080A SoC and its personalities, timer controller
1211          * offset is different
1212          */
1213         svr_dev_id = get_svr();
1214         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1215                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1216
1217 #endif
1218
1219         /* Enable clock for timer
1220          * This is a global setting.
1221          */
1222         out_le32(cntcr, 0x1);
1223
1224         return 0;
1225 }
1226
1227 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1228
1229 void __efi_runtime reset_cpu(ulong addr)
1230 {
1231         u32 val;
1232
1233 #ifdef CONFIG_ARCH_LX2160A
1234         val = in_le32(rstcr);
1235         val |= 0x01;
1236         out_le32(rstcr, val);
1237 #else
1238         /* Raise RESET_REQ_B */
1239         val = scfg_in32(rstcr);
1240         val |= 0x02;
1241         scfg_out32(rstcr, val);
1242 #endif
1243 }
1244
1245 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1246
1247 void __efi_runtime EFIAPI efi_reset_system(
1248                        enum efi_reset_type reset_type,
1249                        efi_status_t reset_status,
1250                        unsigned long data_size, void *reset_data)
1251 {
1252         switch (reset_type) {
1253         case EFI_RESET_COLD:
1254         case EFI_RESET_WARM:
1255         case EFI_RESET_PLATFORM_SPECIFIC:
1256                 reset_cpu(0);
1257                 break;
1258         case EFI_RESET_SHUTDOWN:
1259                 /* Nothing we can do */
1260                 break;
1261         }
1262
1263         while (1) { }
1264 }
1265
1266 efi_status_t efi_reset_system_init(void)
1267 {
1268         return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1269 }
1270
1271 #endif
1272
1273 /*
1274  * Calculate reserved memory with given memory bank
1275  * Return aligned memory size on success
1276  * Return (ram_size + needed size) for failure
1277  */
1278 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1279 {
1280         phys_size_t ram_top = ram_size;
1281
1282 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1283         ram_top = mc_get_dram_block_size();
1284         if (ram_top > ram_size)
1285                 return ram_size + ram_top;
1286
1287         ram_top = ram_size - ram_top;
1288         /* The start address of MC reserved memory needs to be aligned. */
1289         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1290 #endif
1291
1292         return ram_size - ram_top;
1293 }
1294
1295 phys_size_t get_effective_memsize(void)
1296 {
1297         phys_size_t ea_size, rem = 0;
1298
1299         /*
1300          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1301          * first region is 2GB space at 0x8000_0000. Secure memory needs to
1302          * allocated from first region. If the memory extends to  the second
1303          * region (or the third region if applicable), Management Complex (MC)
1304          * memory should be put into the highest region, i.e. the end of DDR
1305          * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1306          * U-Boot doesn't relocate itself into higher address. Should DDR be
1307          * configured to skip the first region, this function needs to be
1308          * adjusted.
1309          */
1310         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1311                 ea_size = CONFIG_MAX_MEM_MAPPED;
1312                 rem = gd->ram_size - ea_size;
1313         } else {
1314                 ea_size = gd->ram_size;
1315         }
1316
1317 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1318         /* Check if we have enough space for secure memory */
1319         if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1320                 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1321         else
1322                 printf("Error: No enough space for secure memory.\n");
1323 #endif
1324         /* Check if we have enough memory for MC */
1325         if (rem < board_reserve_ram_top(rem)) {
1326                 /* Not enough memory in high region to reserve */
1327                 if (ea_size > board_reserve_ram_top(ea_size))
1328                         ea_size -= board_reserve_ram_top(ea_size);
1329                 else
1330                         printf("Error: No enough space for reserved memory.\n");
1331         }
1332
1333         return ea_size;
1334 }
1335
1336 #ifdef CONFIG_TFABOOT
1337 phys_size_t tfa_get_dram_size(void)
1338 {
1339         struct pt_regs regs;
1340         phys_size_t dram_size = 0;
1341
1342         regs.regs[0] = SMC_DRAM_BANK_INFO;
1343         regs.regs[1] = -1;
1344
1345         smc_call(&regs);
1346         if (regs.regs[0])
1347                 return 0;
1348
1349         dram_size = regs.regs[1];
1350         return dram_size;
1351 }
1352
1353 static int tfa_dram_init_banksize(void)
1354 {
1355         int i = 0, ret = 0;
1356         struct pt_regs regs;
1357         phys_size_t dram_size = tfa_get_dram_size();
1358
1359         debug("dram_size %llx\n", dram_size);
1360
1361         if (!dram_size)
1362                 return -EINVAL;
1363
1364         do {
1365                 regs.regs[0] = SMC_DRAM_BANK_INFO;
1366                 regs.regs[1] = i;
1367
1368                 smc_call(&regs);
1369                 if (regs.regs[0]) {
1370                         ret = -EINVAL;
1371                         break;
1372                 }
1373
1374                 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1375                       regs.regs[2]);
1376                 gd->bd->bi_dram[i].start = regs.regs[1];
1377                 gd->bd->bi_dram[i].size = regs.regs[2];
1378
1379                 dram_size -= gd->bd->bi_dram[i].size;
1380
1381                 i++;
1382         } while (dram_size);
1383
1384         if (i > 0)
1385                 ret = 0;
1386
1387 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1388         /* Assign memory for MC */
1389 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1390         if (gd->bd->bi_dram[2].size >=
1391             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1392                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1393                             gd->bd->bi_dram[2].size -
1394                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1395         } else
1396 #endif
1397         {
1398                 if (gd->bd->bi_dram[1].size >=
1399                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1400                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1401                                 gd->bd->bi_dram[1].size -
1402                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1403                 } else if (gd->bd->bi_dram[0].size >
1404                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1405                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1406                                 gd->bd->bi_dram[0].size -
1407                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1408                 }
1409         }
1410 #endif  /* CONFIG_RESV_RAM */
1411
1412         return ret;
1413 }
1414 #endif
1415
1416 int dram_init_banksize(void)
1417 {
1418 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1419         phys_size_t dp_ddr_size;
1420 #endif
1421
1422 #ifdef CONFIG_TFABOOT
1423         if (!tfa_dram_init_banksize())
1424                 return 0;
1425 #endif
1426         /*
1427          * gd->ram_size has the total size of DDR memory, less reserved secure
1428          * memory. The DDR extends from low region to high region(s) presuming
1429          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1430          * the location of secure memory. gd->arch.resv_ram tracks the location
1431          * of reserved memory for Management Complex (MC). Because gd->ram_size
1432          * is reduced by this function if secure memory is reserved, checking
1433          * gd->arch.secure_ram should be done to avoid running it repeatedly.
1434          */
1435
1436 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1437         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1438                 debug("No need to run again, skip %s\n", __func__);
1439
1440                 return 0;
1441         }
1442 #endif
1443
1444         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1445         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1446                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1447                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1448                 gd->bd->bi_dram[1].size = gd->ram_size -
1449                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
1450 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1451                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1452                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1453                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1454                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
1455                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1456                 }
1457 #endif
1458         } else {
1459                 gd->bd->bi_dram[0].size = gd->ram_size;
1460         }
1461 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1462         if (gd->bd->bi_dram[0].size >
1463                                 CONFIG_SYS_MEM_RESERVE_SECURE) {
1464                 gd->bd->bi_dram[0].size -=
1465                                 CONFIG_SYS_MEM_RESERVE_SECURE;
1466                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1467                                       gd->bd->bi_dram[0].size;
1468                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1469                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1470         }
1471 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
1472
1473 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1474         /* Assign memory for MC */
1475 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1476         if (gd->bd->bi_dram[2].size >=
1477             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1478                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1479                             gd->bd->bi_dram[2].size -
1480                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1481         } else
1482 #endif
1483         {
1484                 if (gd->bd->bi_dram[1].size >=
1485                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1486                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1487                                 gd->bd->bi_dram[1].size -
1488                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1489                 } else if (gd->bd->bi_dram[0].size >
1490                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1491                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1492                                 gd->bd->bi_dram[0].size -
1493                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1494                 }
1495         }
1496 #endif  /* CONFIG_RESV_RAM */
1497
1498 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1499 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1500 #error "This SoC shouldn't have DP DDR"
1501 #endif
1502         if (soc_has_dp_ddr()) {
1503                 /* initialize DP-DDR here */
1504                 puts("DP-DDR:  ");
1505                 /*
1506                  * DDR controller use 0 as the base address for binding.
1507                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1508                  */
1509                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1510                                           CONFIG_DP_DDR_CTRL,
1511                                           CONFIG_DP_DDR_NUM_CTRLS,
1512                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1513                                           NULL, NULL, NULL);
1514                 if (dp_ddr_size) {
1515                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1516                         gd->bd->bi_dram[2].size = dp_ddr_size;
1517                 } else {
1518                         puts("Not detected");
1519                 }
1520         }
1521 #endif
1522
1523 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1524         debug("%s is called. gd->ram_size is reduced to %lu\n",
1525               __func__, (ulong)gd->ram_size);
1526 #endif
1527
1528         return 0;
1529 }
1530
1531 #if CONFIG_IS_ENABLED(EFI_LOADER)
1532 void efi_add_known_memory(void)
1533 {
1534         int i;
1535         phys_addr_t ram_start;
1536         phys_size_t ram_size;
1537
1538         /* Add RAM */
1539         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1540 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1541 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1542 #error "This SoC shouldn't have DP DDR"
1543 #endif
1544                 if (i == 2)
1545                         continue;       /* skip DP-DDR */
1546 #endif
1547                 ram_start = gd->bd->bi_dram[i].start;
1548                 ram_size = gd->bd->bi_dram[i].size;
1549 #ifdef CONFIG_RESV_RAM
1550                 if (gd->arch.resv_ram >= ram_start &&
1551                     gd->arch.resv_ram < ram_start + ram_size)
1552                         ram_size = gd->arch.resv_ram - ram_start;
1553 #endif
1554                 efi_add_memory_map(ram_start, ram_size,
1555                                    EFI_CONVENTIONAL_MEMORY);
1556         }
1557 }
1558 #endif
1559
1560 /*
1561  * Before DDR size is known, early MMU table have DDR mapped as device memory
1562  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1563  * needs to be set for these mappings.
1564  * If a special case configures DDR with holes in the mapping, the holes need
1565  * to be marked as invalid. This is not implemented in this function.
1566  */
1567 void update_early_mmu_table(void)
1568 {
1569         if (!gd->arch.tlb_addr)
1570                 return;
1571
1572         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1573                 mmu_change_region_attr(
1574                                         CONFIG_SYS_SDRAM_BASE,
1575                                         gd->ram_size,
1576                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1577                                         PTE_BLOCK_OUTER_SHARE           |
1578                                         PTE_BLOCK_NS                    |
1579                                         PTE_TYPE_VALID);
1580         } else {
1581                 mmu_change_region_attr(
1582                                         CONFIG_SYS_SDRAM_BASE,
1583                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1584                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1585                                         PTE_BLOCK_OUTER_SHARE           |
1586                                         PTE_BLOCK_NS                    |
1587                                         PTE_TYPE_VALID);
1588 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1589 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1590 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1591 #endif
1592                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1593                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
1594                         mmu_change_region_attr(
1595                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1596                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1597                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1598                                         PTE_BLOCK_OUTER_SHARE           |
1599                                         PTE_BLOCK_NS                    |
1600                                         PTE_TYPE_VALID);
1601                         mmu_change_region_attr(
1602                                         CONFIG_SYS_DDR_BLOCK3_BASE,
1603                                         gd->ram_size -
1604                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
1605                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1606                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1607                                         PTE_BLOCK_OUTER_SHARE           |
1608                                         PTE_BLOCK_NS                    |
1609                                         PTE_TYPE_VALID);
1610                 } else
1611 #endif
1612                 {
1613                         mmu_change_region_attr(
1614                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1615                                         gd->ram_size -
1616                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1617                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1618                                         PTE_BLOCK_OUTER_SHARE           |
1619                                         PTE_BLOCK_NS                    |
1620                                         PTE_TYPE_VALID);
1621                 }
1622         }
1623 }
1624
1625 __weak int dram_init(void)
1626 {
1627         fsl_initdram();
1628 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1629         defined(CONFIG_SPL_BUILD)
1630         /* This will break-before-make MMU for DDR */
1631         update_early_mmu_table();
1632 #endif
1633
1634         return 0;
1635 }
1636
1637 #ifdef CONFIG_ARCH_MISC_INIT
1638 __weak int serdes_misc_init(void)
1639 {
1640         return 0;
1641 }
1642
1643 int arch_misc_init(void)
1644 {
1645         serdes_misc_init();
1646
1647         return 0;
1648 }
1649 #endif