1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
9 #include <fsl_ddr_sdram.h>
11 #include <linux/errno.h>
12 #include <asm/system.h>
14 #include <asm/armv8/mmu.h>
16 #include <asm/arch/fsl_serdes.h>
17 #include <asm/arch/soc.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/speed.h>
20 #include <fsl_immap.h>
21 #include <asm/arch/mp.h>
22 #include <efi_loader.h>
23 #include <fsl-mc/fsl_mc.h>
24 #ifdef CONFIG_FSL_ESDHC
25 #include <fsl_esdhc.h>
27 #include <asm/armv8/sec_firmware.h>
28 #ifdef CONFIG_SYS_FSL_DDR
31 #include <asm/arch/clock.h>
33 #include <fsl_qbman.h>
36 #include <env_internal.h>
37 #ifdef CONFIG_CHAIN_OF_TRUST
38 #include <fsl_validate.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 static struct cpu_type cpu_type_list[] = {
45 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
46 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
47 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
48 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
49 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
50 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
51 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
52 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
53 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
54 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
55 CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
56 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
57 CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
58 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
59 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
60 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
61 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
62 CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
63 CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
64 CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
65 CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
66 CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
67 CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
68 CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
69 CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
70 CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
71 CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
72 CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
75 #define EARLY_PGTABLE_SIZE 0x5000
76 static struct mm_region early_map[] = {
77 #ifdef CONFIG_FSL_LSCH3
78 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
79 CONFIG_SYS_FSL_CCSR_SIZE,
80 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
81 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
83 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
84 SYS_FSL_OCRAM_SPACE_SIZE,
85 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
87 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
88 CONFIG_SYS_FSL_QSPI_SIZE1,
89 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
91 /* For IFC Region #1, only the first 4MB is cache-enabled */
92 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
93 CONFIG_SYS_FSL_IFC_SIZE1_1,
94 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
96 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
97 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
98 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
99 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
101 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
102 CONFIG_SYS_FSL_IFC_SIZE1,
103 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
106 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
107 CONFIG_SYS_FSL_DRAM_SIZE1,
108 #if defined(CONFIG_TFABOOT) || \
109 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
110 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
111 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
112 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
114 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
116 #ifdef CONFIG_FSL_IFC
117 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
118 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
119 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
120 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
123 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
124 CONFIG_SYS_FSL_DCSR_SIZE,
125 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
126 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
128 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
129 CONFIG_SYS_FSL_DRAM_SIZE2,
130 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
131 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
133 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
134 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
135 CONFIG_SYS_FSL_DRAM_SIZE3,
136 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
137 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
140 #elif defined(CONFIG_FSL_LSCH2)
141 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
142 CONFIG_SYS_FSL_CCSR_SIZE,
143 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
144 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
146 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
147 SYS_FSL_OCRAM_SPACE_SIZE,
148 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
150 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
151 CONFIG_SYS_FSL_DCSR_SIZE,
152 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
153 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
155 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
156 CONFIG_SYS_FSL_QSPI_SIZE,
157 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
159 #ifdef CONFIG_FSL_IFC
160 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
161 CONFIG_SYS_FSL_IFC_SIZE,
162 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
165 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
166 CONFIG_SYS_FSL_DRAM_SIZE1,
167 #if defined(CONFIG_TFABOOT) || \
168 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
169 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
170 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
171 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
173 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
175 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
176 CONFIG_SYS_FSL_DRAM_SIZE2,
177 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
178 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
181 {}, /* list terminator */
184 static struct mm_region final_map[] = {
185 #ifdef CONFIG_FSL_LSCH3
186 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
187 CONFIG_SYS_FSL_CCSR_SIZE,
188 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
189 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
191 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
192 SYS_FSL_OCRAM_SPACE_SIZE,
193 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
195 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
196 CONFIG_SYS_FSL_DRAM_SIZE1,
197 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
198 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
200 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
201 CONFIG_SYS_FSL_QSPI_SIZE1,
202 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
203 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
205 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
206 CONFIG_SYS_FSL_QSPI_SIZE2,
207 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
208 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
210 #ifdef CONFIG_FSL_IFC
211 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
212 CONFIG_SYS_FSL_IFC_SIZE2,
213 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
214 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
217 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
218 CONFIG_SYS_FSL_DCSR_SIZE,
219 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
220 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
222 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
223 CONFIG_SYS_FSL_MC_SIZE,
224 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
225 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
227 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
228 CONFIG_SYS_FSL_NI_SIZE,
229 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
230 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
232 /* For QBMAN portal, only the first 64MB is cache-enabled */
233 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
234 CONFIG_SYS_FSL_QBMAN_SIZE_1,
235 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
236 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
238 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
239 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
240 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
241 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
242 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
244 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
245 CONFIG_SYS_PCIE1_PHYS_SIZE,
246 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
247 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
249 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
250 CONFIG_SYS_PCIE2_PHYS_SIZE,
251 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
252 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
254 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
255 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
256 CONFIG_SYS_PCIE3_PHYS_SIZE,
257 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
258 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
261 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
262 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
263 CONFIG_SYS_PCIE4_PHYS_SIZE,
264 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
265 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
268 #ifdef SYS_PCIE5_PHYS_ADDR
269 { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
271 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
272 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
275 #ifdef SYS_PCIE6_PHYS_ADDR
276 { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
278 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
279 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
282 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
283 CONFIG_SYS_FSL_WRIOP1_SIZE,
284 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
285 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
287 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
288 CONFIG_SYS_FSL_AIOP1_SIZE,
289 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
290 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
292 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
293 CONFIG_SYS_FSL_PEBUF_SIZE,
294 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
295 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
297 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
298 CONFIG_SYS_FSL_DRAM_SIZE2,
299 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
300 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
302 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
303 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
304 CONFIG_SYS_FSL_DRAM_SIZE3,
305 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
306 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
309 #elif defined(CONFIG_FSL_LSCH2)
310 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
311 CONFIG_SYS_FSL_BOOTROM_SIZE,
312 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
313 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
315 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
316 CONFIG_SYS_FSL_CCSR_SIZE,
317 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
318 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
320 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
321 SYS_FSL_OCRAM_SPACE_SIZE,
322 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
324 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
325 CONFIG_SYS_FSL_DCSR_SIZE,
326 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
327 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
329 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
330 CONFIG_SYS_FSL_QSPI_SIZE,
331 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
332 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
334 #ifdef CONFIG_FSL_IFC
335 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
336 CONFIG_SYS_FSL_IFC_SIZE,
337 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
340 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
341 CONFIG_SYS_FSL_DRAM_SIZE1,
342 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
343 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
345 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
346 CONFIG_SYS_FSL_QBMAN_SIZE,
347 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
348 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
350 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
351 CONFIG_SYS_FSL_DRAM_SIZE2,
352 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
353 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
355 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
356 CONFIG_SYS_PCIE1_PHYS_SIZE,
357 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
358 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
360 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
361 CONFIG_SYS_PCIE2_PHYS_SIZE,
362 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
363 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
365 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
366 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
367 CONFIG_SYS_PCIE3_PHYS_SIZE,
368 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
369 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
372 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
373 CONFIG_SYS_FSL_DRAM_SIZE3,
374 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
375 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
378 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
379 {}, /* space holder for secure mem */
384 struct mm_region *mem_map = early_map;
386 void cpu_name(char *name)
388 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
389 unsigned int i, svr, ver;
391 svr = gur_in32(&gur->svr);
392 ver = SVR_SOC_VER(svr);
394 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
395 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
396 strcpy(name, cpu_type_list[i].name);
397 #ifdef CONFIG_ARCH_LX2160A
398 if (IS_C_PROCESSOR(svr))
402 if (IS_E_PROCESSOR(svr))
405 sprintf(name + strlen(name), " Rev%d.%d",
406 SVR_MAJ(svr), SVR_MIN(svr));
410 if (i == ARRAY_SIZE(cpu_type_list))
411 strcpy(name, "unknown");
414 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
416 * To start MMU before DDR is available, we create MMU table in SRAM.
417 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
418 * levels of translation tables here to cover 40-bit address space.
419 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
420 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
421 * Note, the debug print in cache_v8.c is not usable for debugging
422 * these early MMU tables because UART is not yet available.
424 static inline void early_mmu_setup(void)
426 unsigned int el = current_el();
428 /* global data is already setup, no allocation yet */
430 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
432 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
433 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
434 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
436 /* Create early page tables */
439 /* point TTBR to the new table */
440 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
441 get_tcr(el, NULL, NULL) &
442 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
445 set_sctlr(get_sctlr() | CR_M);
448 static void fix_pcie_mmu_map(void)
450 #ifdef CONFIG_ARCH_LS2080A
453 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
455 svr = gur_in32(&gur->svr);
456 ver = SVR_SOC_VER(svr);
458 /* Fix PCIE base and size for LS2088A */
459 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
460 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
461 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
462 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
463 switch (final_map[i].phys) {
464 case CONFIG_SYS_PCIE1_PHYS_ADDR:
465 final_map[i].phys = 0x2000000000ULL;
466 final_map[i].virt = 0x2000000000ULL;
467 final_map[i].size = 0x800000000ULL;
469 case CONFIG_SYS_PCIE2_PHYS_ADDR:
470 final_map[i].phys = 0x2800000000ULL;
471 final_map[i].virt = 0x2800000000ULL;
472 final_map[i].size = 0x800000000ULL;
474 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
475 case CONFIG_SYS_PCIE3_PHYS_ADDR:
476 final_map[i].phys = 0x3000000000ULL;
477 final_map[i].virt = 0x3000000000ULL;
478 final_map[i].size = 0x800000000ULL;
481 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
482 case CONFIG_SYS_PCIE4_PHYS_ADDR:
483 final_map[i].phys = 0x3800000000ULL;
484 final_map[i].virt = 0x3800000000ULL;
485 final_map[i].size = 0x800000000ULL;
497 * The final tables look similar to early tables, but different in detail.
498 * These tables are in DRAM. Sub tables are added to enable cache for
501 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
502 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
504 static inline void final_mmu_setup(void)
506 u64 tlb_addr_save = gd->arch.tlb_addr;
507 unsigned int el = current_el();
510 /* fix the final_map before filling in the block entries */
515 /* Update mapping for DDR to actual size */
516 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
518 * Find the entry for DDR mapping and update the address and
519 * size. Zero-sized mapping will be skipped when creating MMU
522 switch (final_map[index].virt) {
523 case CONFIG_SYS_FSL_DRAM_BASE1:
524 final_map[index].virt = gd->bd->bi_dram[0].start;
525 final_map[index].phys = gd->bd->bi_dram[0].start;
526 final_map[index].size = gd->bd->bi_dram[0].size;
528 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
529 case CONFIG_SYS_FSL_DRAM_BASE2:
530 #if (CONFIG_NR_DRAM_BANKS >= 2)
531 final_map[index].virt = gd->bd->bi_dram[1].start;
532 final_map[index].phys = gd->bd->bi_dram[1].start;
533 final_map[index].size = gd->bd->bi_dram[1].size;
535 final_map[index].size = 0;
539 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
540 case CONFIG_SYS_FSL_DRAM_BASE3:
541 #if (CONFIG_NR_DRAM_BANKS >= 3)
542 final_map[index].virt = gd->bd->bi_dram[2].start;
543 final_map[index].phys = gd->bd->bi_dram[2].start;
544 final_map[index].size = gd->bd->bi_dram[2].size;
546 final_map[index].size = 0;
555 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
556 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
559 * Only use gd->arch.secure_ram if the address is
560 * recalculated. Align to 4KB for MMU table.
562 /* put page tables in secure ram */
563 index = ARRAY_SIZE(final_map) - 2;
564 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
565 final_map[index].virt = gd->arch.secure_ram & ~0x3;
566 final_map[index].phys = final_map[index].virt;
567 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
568 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
569 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
570 tlb_addr_save = gd->arch.tlb_addr;
572 /* Use allocated (board_f.c) memory for TLB */
573 tlb_addr_save = gd->arch.tlb_allocated;
574 gd->arch.tlb_addr = tlb_addr_save;
579 /* Reset the fill ptr */
580 gd->arch.tlb_fillptr = tlb_addr_save;
582 /* Create normal system page tables */
585 /* Create emergency page tables */
586 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
587 gd->arch.tlb_emerg = gd->arch.tlb_addr;
589 gd->arch.tlb_addr = tlb_addr_save;
591 /* Disable cache and MMU */
592 dcache_disable(); /* TLBs are invalidated */
593 invalidate_icache_all();
595 /* point TTBR to the new table */
596 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
599 set_sctlr(get_sctlr() | CR_M);
602 u64 get_page_table_size(void)
607 int arch_cpu_init(void)
610 * This function is called before U-Boot relocates itself to speed up
611 * on system running. It is not necessary to run if performance is not
612 * critical. Skip if MMU is already enabled by SPL or other means.
614 if (get_sctlr() & CR_M)
618 __asm_invalidate_dcache_all();
619 __asm_invalidate_tlb_all();
621 set_sctlr(get_sctlr() | CR_C);
631 * This function is called from common/board_r.c.
632 * It recreates MMU table in main memory.
634 void enable_caches(void)
637 __asm_invalidate_tlb_all();
641 #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
643 #ifdef CONFIG_TFABOOT
644 enum boot_src __get_boot_src(u32 porsr1)
646 enum boot_src src = BOOT_SOURCE_RESERVED;
647 u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
648 #if !defined(CONFIG_NXP_LSCH3_2)
651 debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
653 #if defined(CONFIG_FSL_LSCH3)
654 #if defined(CONFIG_NXP_LSCH3_2)
656 case RCW_SRC_SDHC1_VAL:
657 src = BOOT_SOURCE_SD_MMC;
659 case RCW_SRC_SDHC2_VAL:
660 src = BOOT_SOURCE_SD_MMC2;
662 case RCW_SRC_I2C1_VAL:
663 src = BOOT_SOURCE_I2C1_EXTENDED;
665 case RCW_SRC_FLEXSPI_NAND2K_VAL:
666 src = BOOT_SOURCE_XSPI_NAND;
668 case RCW_SRC_FLEXSPI_NAND4K_VAL:
669 src = BOOT_SOURCE_XSPI_NAND;
671 case RCW_SRC_RESERVED_1_VAL:
672 src = BOOT_SOURCE_RESERVED;
674 case RCW_SRC_FLEXSPI_NOR_24B:
675 src = BOOT_SOURCE_XSPI_NOR;
678 src = BOOT_SOURCE_RESERVED;
681 val = rcw_src & RCW_SRC_TYPE_MASK;
682 if (val == RCW_SRC_NOR_VAL) {
683 val = rcw_src & NOR_TYPE_MASK;
688 src = BOOT_SOURCE_IFC_NOR;
691 src = BOOT_SOURCE_RESERVED;
694 /* RCW SRC Serial Flash */
695 val = rcw_src & RCW_SRC_SERIAL_MASK;
697 case RCW_SRC_QSPI_VAL:
698 /* RCW SRC Serial NOR (QSPI) */
699 src = BOOT_SOURCE_QSPI_NOR;
701 case RCW_SRC_SD_CARD_VAL:
702 /* RCW SRC SD Card */
703 src = BOOT_SOURCE_SD_MMC;
705 case RCW_SRC_EMMC_VAL:
707 src = BOOT_SOURCE_SD_MMC;
709 case RCW_SRC_I2C1_VAL:
710 /* RCW SRC I2C1 Extended */
711 src = BOOT_SOURCE_I2C1_EXTENDED;
714 src = BOOT_SOURCE_RESERVED;
718 #elif defined(CONFIG_FSL_LSCH2)
720 val = rcw_src & RCW_SRC_NAND_MASK;
721 if (val == RCW_SRC_NAND_VAL) {
722 val = rcw_src & NAND_RESERVED_MASK;
723 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
724 src = BOOT_SOURCE_IFC_NAND;
728 val = rcw_src & RCW_SRC_NOR_MASK;
729 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
730 src = BOOT_SOURCE_IFC_NOR;
735 src = BOOT_SOURCE_QSPI_NOR;
738 src = BOOT_SOURCE_SD_MMC;
741 src = BOOT_SOURCE_RESERVED;
747 if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
748 src = BOOT_SOURCE_QSPI_NOR;
750 debug("%s: src 0x%x\n", __func__, src);
754 enum boot_src get_boot_src(void)
759 #if defined(CONFIG_FSL_LSCH3)
760 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
761 #elif defined(CONFIG_FSL_LSCH2)
762 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
765 if (current_el() == 2) {
766 regs.regs[0] = SIP_SVC_RCW;
770 porsr1 = regs.regs[1];
773 if (current_el() == 3 || !porsr1) {
774 #ifdef CONFIG_FSL_LSCH3
775 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
776 #elif defined(CONFIG_FSL_LSCH2)
777 porsr1 = in_be32(&gur->porsr1);
781 debug("%s: porsr1 0x%x\n", __func__, porsr1);
783 return __get_boot_src(porsr1);
786 #ifdef CONFIG_ENV_IS_IN_MMC
787 int mmc_get_env_dev(void)
789 enum boot_src src = get_boot_src();
790 int dev = CONFIG_SYS_MMC_ENV_DEV;
793 case BOOT_SOURCE_SD_MMC:
796 case BOOT_SOURCE_SD_MMC2:
807 enum env_location env_get_location(enum env_operation op, int prio)
809 enum boot_src src = get_boot_src();
810 enum env_location env_loc = ENVL_NOWHERE;
815 #ifdef CONFIG_ENV_IS_NOWHERE
820 case BOOT_SOURCE_IFC_NOR:
821 env_loc = ENVL_FLASH;
823 case BOOT_SOURCE_QSPI_NOR:
825 case BOOT_SOURCE_XSPI_NOR:
826 env_loc = ENVL_SPI_FLASH;
828 case BOOT_SOURCE_IFC_NAND:
830 case BOOT_SOURCE_QSPI_NAND:
832 case BOOT_SOURCE_XSPI_NAND:
835 case BOOT_SOURCE_SD_MMC:
837 case BOOT_SOURCE_SD_MMC2:
840 case BOOT_SOURCE_I2C1_EXTENDED:
848 #endif /* CONFIG_TFABOOT */
850 u32 initiator_type(u32 cluster, int init_id)
852 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
853 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
856 type = gur_in32(&gur->tp_ityp[idx]);
857 if (type & TP_ITYP_AV)
863 u32 cpu_pos_mask(void)
865 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
867 u32 cluster, type, mask = 0;
872 cluster = gur_in32(&gur->tp_cluster[i].lower);
873 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
874 type = initiator_type(cluster, j);
875 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
876 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
879 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
886 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
887 int i = 0, count = 0;
888 u32 cluster, type, mask = 0;
893 cluster = gur_in32(&gur->tp_cluster[i].lower);
894 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
895 type = initiator_type(cluster, j);
897 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
903 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
909 * Return the number of cores on this SOC.
911 int cpu_numcores(void)
913 return hweight32(cpu_mask());
916 int fsl_qoriq_core_to_cluster(unsigned int core)
918 struct ccsr_gur __iomem *gur =
919 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
920 int i = 0, count = 0;
926 cluster = gur_in32(&gur->tp_cluster[i].lower);
927 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
928 if (initiator_type(cluster, j)) {
935 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
937 return -1; /* cannot identify the cluster */
940 u32 fsl_qoriq_core_to_type(unsigned int core)
942 struct ccsr_gur __iomem *gur =
943 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
944 int i = 0, count = 0;
950 cluster = gur_in32(&gur->tp_cluster[i].lower);
951 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
952 type = initiator_type(cluster, j);
960 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
962 return -1; /* cannot identify the cluster */
965 #ifndef CONFIG_FSL_LSCH3
968 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
970 return gur_in32(&gur->svr);
974 #ifdef CONFIG_DISPLAY_CPUINFO
975 int print_cpuinfo(void)
977 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
978 struct sys_info sysinfo;
980 unsigned int i, core;
981 u32 type, rcw, svr = gur_in32(&gur->svr);
986 printf(" %s (0x%x)\n", buf, svr);
987 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
988 get_sys_info(&sysinfo);
989 puts("Clock Configuration:");
990 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
993 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
994 printf("CPU%d(%s):%-4s MHz ", core,
995 type == TY_ITYP_VER_A7 ? "A7 " :
996 (type == TY_ITYP_VER_A53 ? "A53" :
997 (type == TY_ITYP_VER_A57 ? "A57" :
998 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
999 strmhz(buf, sysinfo.freq_processor[core]));
1001 /* Display platform clock as Bus frequency. */
1002 printf("\n Bus: %-4s MHz ",
1003 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1004 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1005 #ifdef CONFIG_SYS_DPAA_FMAN
1006 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1008 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1009 if (soc_has_dp_ddr()) {
1010 printf(" DP-DDR: %-4s MT/s",
1011 strmhz(buf, sysinfo.freq_ddrbus2));
1017 * Display the RCW, so that no one gets confused as to what RCW
1018 * we're actually using for this boot.
1020 puts("Reset Configuration Word (RCW):");
1021 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1022 rcw = gur_in32(&gur->rcwsr[i]);
1024 printf("\n %08x:", i * 4);
1025 printf(" %08x", rcw);
1033 #ifdef CONFIG_FSL_ESDHC
1034 int cpu_mmc_init(bd_t *bis)
1036 return fsl_esdhc_mmc_init(bis);
1040 int cpu_eth_init(bd_t *bis)
1044 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1045 error = fsl_mc_ldpaa_init(bis);
1047 #ifdef CONFIG_FMAN_ENET
1048 fm_standard_init(bis);
1053 static inline int check_psci(void)
1055 unsigned int psci_ver;
1057 psci_ver = sec_firmware_support_psci_version();
1058 if (psci_ver == PSCI_INVALID_VER)
1064 static void config_core_prefetch(void)
1067 char buffer[HWCONFIG_BUFFER_SIZE];
1068 const char *prefetch_arg = NULL;
1071 struct pt_regs regs;
1073 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1076 prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1080 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1082 printf("Core0 prefetch can't be disabled\n");
1086 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1087 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1088 regs.regs[1] = mask;
1092 printf("Prefetch disable config failed for mask ");
1094 printf("Prefetch disable config passed for mask ");
1095 printf("0x%x\n", mask);
1099 int arch_early_init_r(void)
1101 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1104 * erratum A009635 is valid only for LS2080A SoC and
1105 * its personalitiesi
1107 svr_dev_id = get_svr();
1108 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1111 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1112 erratum_a009942_check_cpo();
1115 debug("PSCI: PSCI does not exist.\n");
1117 /* if PSCI does not exist, boot secondary cores here */
1118 if (fsl_layerscape_wake_seconday_cores())
1119 printf("Did not wake secondary cores\n");
1122 config_core_prefetch();
1124 #ifdef CONFIG_SYS_HAS_SERDES
1127 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1128 /* some dpmacs in armv8a based freescale layerscape SOCs can be
1129 * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1130 * EC*_PMUX(rgmii) bits in RCW.
1131 * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1132 * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1133 * Now if a dpmac is enabled by serdes bits then it takes precedence
1134 * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
1135 * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
1136 * then the dpmac is SGMII and not RGMII.
1138 * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
1139 * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
1140 * or not? if it is (fsl_serdes_init has already enabled the dpmac),
1141 * then don't enable it.
1145 #ifdef CONFIG_FMAN_ENET
1148 #ifdef CONFIG_SYS_DPAA_QBMAN
1149 setup_qbman_portals();
1154 int timer_init(void)
1156 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1157 #ifdef CONFIG_FSL_LSCH3
1158 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1160 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1161 defined(CONFIG_ARCH_LS1028A)
1162 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1165 #ifdef COUNTER_FREQUENCY_REAL
1166 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1168 /* Update with accurate clock frequency */
1169 if (current_el() == 3)
1170 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1173 #ifdef CONFIG_FSL_LSCH3
1174 /* Enable timebase for all clusters.
1175 * It is safe to do so even some clusters are not enabled.
1177 out_le32(cltbenr, 0xf);
1180 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1181 defined(CONFIG_ARCH_LS1028A)
1183 * In certain Layerscape SoCs, the clock for each core's
1184 * has an enable bit in the PMU Physical Core Time Base Enable
1185 * Register (PCTBENR), which allows the watchdog to operate.
1187 setbits_le32(pctbenr, 0xff);
1189 * For LS2080A SoC and its personalities, timer controller
1190 * offset is different
1192 svr_dev_id = get_svr();
1193 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1194 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1198 /* Enable clock for timer
1199 * This is a global setting.
1201 out_le32(cntcr, 0x1);
1206 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1208 void __efi_runtime reset_cpu(ulong addr)
1212 #ifdef CONFIG_ARCH_LX2160A
1213 val = in_le32(rstcr);
1215 out_le32(rstcr, val);
1217 /* Raise RESET_REQ_B */
1218 val = scfg_in32(rstcr);
1220 scfg_out32(rstcr, val);
1224 #ifdef CONFIG_EFI_LOADER
1226 void __efi_runtime EFIAPI efi_reset_system(
1227 enum efi_reset_type reset_type,
1228 efi_status_t reset_status,
1229 unsigned long data_size, void *reset_data)
1231 switch (reset_type) {
1232 case EFI_RESET_COLD:
1233 case EFI_RESET_WARM:
1234 case EFI_RESET_PLATFORM_SPECIFIC:
1237 case EFI_RESET_SHUTDOWN:
1238 /* Nothing we can do */
1245 efi_status_t efi_reset_system_init(void)
1247 return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1253 * Calculate reserved memory with given memory bank
1254 * Return aligned memory size on success
1255 * Return (ram_size + needed size) for failure
1257 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1259 phys_size_t ram_top = ram_size;
1261 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1262 ram_top = mc_get_dram_block_size();
1263 if (ram_top > ram_size)
1264 return ram_size + ram_top;
1266 ram_top = ram_size - ram_top;
1267 /* The start address of MC reserved memory needs to be aligned. */
1268 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1271 return ram_size - ram_top;
1274 phys_size_t get_effective_memsize(void)
1276 phys_size_t ea_size, rem = 0;
1279 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1280 * first region is 2GB space at 0x8000_0000. Secure memory needs to
1281 * allocated from first region. If the memory extends to the second
1282 * region (or the third region if applicable), Management Complex (MC)
1283 * memory should be put into the highest region, i.e. the end of DDR
1284 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1285 * U-Boot doesn't relocate itself into higher address. Should DDR be
1286 * configured to skip the first region, this function needs to be
1289 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1290 ea_size = CONFIG_MAX_MEM_MAPPED;
1291 rem = gd->ram_size - ea_size;
1293 ea_size = gd->ram_size;
1296 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1297 /* Check if we have enough space for secure memory */
1298 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1299 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1301 printf("Error: No enough space for secure memory.\n");
1303 /* Check if we have enough memory for MC */
1304 if (rem < board_reserve_ram_top(rem)) {
1305 /* Not enough memory in high region to reserve */
1306 if (ea_size > board_reserve_ram_top(ea_size))
1307 ea_size -= board_reserve_ram_top(ea_size);
1309 printf("Error: No enough space for reserved memory.\n");
1315 #ifdef CONFIG_TFABOOT
1316 phys_size_t tfa_get_dram_size(void)
1318 struct pt_regs regs;
1319 phys_size_t dram_size = 0;
1321 regs.regs[0] = SMC_DRAM_BANK_INFO;
1328 dram_size = regs.regs[1];
1332 static int tfa_dram_init_banksize(void)
1335 struct pt_regs regs;
1336 phys_size_t dram_size = tfa_get_dram_size();
1338 debug("dram_size %llx\n", dram_size);
1344 regs.regs[0] = SMC_DRAM_BANK_INFO;
1353 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1355 gd->bd->bi_dram[i].start = regs.regs[1];
1356 gd->bd->bi_dram[i].size = regs.regs[2];
1358 dram_size -= gd->bd->bi_dram[i].size;
1361 } while (dram_size);
1366 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1367 /* Assign memory for MC */
1368 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1369 if (gd->bd->bi_dram[2].size >=
1370 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1371 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1372 gd->bd->bi_dram[2].size -
1373 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1377 if (gd->bd->bi_dram[1].size >=
1378 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1379 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1380 gd->bd->bi_dram[1].size -
1381 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1382 } else if (gd->bd->bi_dram[0].size >
1383 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1384 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1385 gd->bd->bi_dram[0].size -
1386 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1389 #endif /* CONFIG_FSL_MC_ENET */
1395 int dram_init_banksize(void)
1397 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1398 phys_size_t dp_ddr_size;
1401 #ifdef CONFIG_TFABOOT
1402 if (!tfa_dram_init_banksize())
1406 * gd->ram_size has the total size of DDR memory, less reserved secure
1407 * memory. The DDR extends from low region to high region(s) presuming
1408 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1409 * the location of secure memory. gd->arch.resv_ram tracks the location
1410 * of reserved memory for Management Complex (MC). Because gd->ram_size
1411 * is reduced by this function if secure memory is reserved, checking
1412 * gd->arch.secure_ram should be done to avoid running it repeatedly.
1415 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1416 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1417 debug("No need to run again, skip %s\n", __func__);
1423 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1424 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1425 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1426 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1427 gd->bd->bi_dram[1].size = gd->ram_size -
1428 CONFIG_SYS_DDR_BLOCK1_SIZE;
1429 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1430 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1431 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1432 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1433 CONFIG_SYS_DDR_BLOCK2_SIZE;
1434 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1438 gd->bd->bi_dram[0].size = gd->ram_size;
1440 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1441 if (gd->bd->bi_dram[0].size >
1442 CONFIG_SYS_MEM_RESERVE_SECURE) {
1443 gd->bd->bi_dram[0].size -=
1444 CONFIG_SYS_MEM_RESERVE_SECURE;
1445 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1446 gd->bd->bi_dram[0].size;
1447 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1448 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1450 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
1452 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1453 /* Assign memory for MC */
1454 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1455 if (gd->bd->bi_dram[2].size >=
1456 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1457 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1458 gd->bd->bi_dram[2].size -
1459 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1463 if (gd->bd->bi_dram[1].size >=
1464 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1465 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1466 gd->bd->bi_dram[1].size -
1467 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1468 } else if (gd->bd->bi_dram[0].size >
1469 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1470 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1471 gd->bd->bi_dram[0].size -
1472 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1475 #endif /* CONFIG_FSL_MC_ENET */
1477 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1478 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1479 #error "This SoC shouldn't have DP DDR"
1481 if (soc_has_dp_ddr()) {
1482 /* initialize DP-DDR here */
1485 * DDR controller use 0 as the base address for binding.
1486 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1488 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1490 CONFIG_DP_DDR_NUM_CTRLS,
1491 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1494 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1495 gd->bd->bi_dram[2].size = dp_ddr_size;
1497 puts("Not detected");
1502 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1503 debug("%s is called. gd->ram_size is reduced to %lu\n",
1504 __func__, (ulong)gd->ram_size);
1510 #if CONFIG_IS_ENABLED(EFI_LOADER)
1511 void efi_add_known_memory(void)
1514 phys_addr_t ram_start, start;
1515 phys_size_t ram_size;
1519 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1520 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1521 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1522 #error "This SoC shouldn't have DP DDR"
1525 continue; /* skip DP-DDR */
1527 ram_start = gd->bd->bi_dram[i].start;
1528 ram_size = gd->bd->bi_dram[i].size;
1529 #ifdef CONFIG_RESV_RAM
1530 if (gd->arch.resv_ram >= ram_start &&
1531 gd->arch.resv_ram < ram_start + ram_size)
1532 ram_size = gd->arch.resv_ram - ram_start;
1534 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1535 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1537 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1544 * Before DDR size is known, early MMU table have DDR mapped as device memory
1545 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1546 * needs to be set for these mappings.
1547 * If a special case configures DDR with holes in the mapping, the holes need
1548 * to be marked as invalid. This is not implemented in this function.
1550 void update_early_mmu_table(void)
1552 if (!gd->arch.tlb_addr)
1555 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1556 mmu_change_region_attr(
1557 CONFIG_SYS_SDRAM_BASE,
1559 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1560 PTE_BLOCK_OUTER_SHARE |
1564 mmu_change_region_attr(
1565 CONFIG_SYS_SDRAM_BASE,
1566 CONFIG_SYS_DDR_BLOCK1_SIZE,
1567 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1568 PTE_BLOCK_OUTER_SHARE |
1571 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1572 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1573 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1575 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1576 CONFIG_SYS_DDR_BLOCK2_SIZE) {
1577 mmu_change_region_attr(
1578 CONFIG_SYS_DDR_BLOCK2_BASE,
1579 CONFIG_SYS_DDR_BLOCK2_SIZE,
1580 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1581 PTE_BLOCK_OUTER_SHARE |
1584 mmu_change_region_attr(
1585 CONFIG_SYS_DDR_BLOCK3_BASE,
1587 CONFIG_SYS_DDR_BLOCK1_SIZE -
1588 CONFIG_SYS_DDR_BLOCK2_SIZE,
1589 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1590 PTE_BLOCK_OUTER_SHARE |
1596 mmu_change_region_attr(
1597 CONFIG_SYS_DDR_BLOCK2_BASE,
1599 CONFIG_SYS_DDR_BLOCK1_SIZE,
1600 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1601 PTE_BLOCK_OUTER_SHARE |
1608 __weak int dram_init(void)
1611 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1612 defined(CONFIG_SPL_BUILD)
1613 /* This will break-before-make MMU for DDR */
1614 update_early_mmu_table();