arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2020 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <init.h>
  12 #include <hang.h>
  13 #include <log.h>
  14 #include <net.h>
  15 #include <vsprintf.h>
  16 #include <asm/cache.h>
  17 #include <asm/io.h>
  18 #include <asm/ptrace.h>
  19 #include <linux/errno.h>
  20 #include <asm/system.h>
  21 #include <fm_eth.h>
  22 #include <asm/armv8/mmu.h>
  23 #include <asm/io.h>
  24 #include <asm/arch/fsl_serdes.h>
  25 #include <asm/arch/soc.h>
  26 #include <asm/arch/cpu.h>
  27 #include <asm/arch/speed.h>
  28 #include <fsl_immap.h>
  29 #include <asm/arch/mp.h>
  30 #include <efi_loader.h>
  31 #include <fsl-mc/fsl_mc.h>
  32 #ifdef CONFIG_FSL_ESDHC
  33 #include <fsl_esdhc.h>
  34 #endif
  35 #include <asm/armv8/sec_firmware.h>
  36 #ifdef CONFIG_SYS_FSL_DDR
  37 #include <fsl_ddr.h>
  38 #endif
  39 #include <asm/arch/clock.h>
  40 #include <hwconfig.h>
  41 #include <fsl_qbman.h>
  42
  43 #ifdef CONFIG_TFABOOT
  44 #include <env_internal.h>
  45 #ifdef CONFIG_CHAIN_OF_TRUST
  46 #include <fsl_validate.h>
  47 #endif
  48 #endif
  49 #include <linux/mii.h>
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 static struct cpu_type cpu_type_list[] = {
  54         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  55         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  56         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  57         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  58         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  59         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  60         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  61         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  62         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  63         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  64         CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
  65         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  66         CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
  67         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  68         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  69         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  70         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  71         CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
  72         CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
  73         CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
  74         CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
  75         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  76         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  77         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  78         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  79         CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
  80         CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
  81         CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
  82 };
  83
  84 #define EARLY_PGTABLE_SIZE 0x5000
  85 static struct mm_region early_map[] = {
  86 #ifdef CONFIG_FSL_LSCH3
  87         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  88           CONFIG_SYS_FSL_CCSR_SIZE,
  89           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  90           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  91         },
  92         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  93           SYS_FSL_OCRAM_SPACE_SIZE,
  94           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  95         },
  96         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
  97           CONFIG_SYS_FSL_QSPI_SIZE1,
  98           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
  99 #ifdef CONFIG_FSL_IFC
 100         /* For IFC Region #1, only the first 4MB is cache-enabled */
 101         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
 102           CONFIG_SYS_FSL_IFC_SIZE1_1,
 103           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 104         },
 105         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 106           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 107           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 108           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 109         },
 110         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 111           CONFIG_SYS_FSL_IFC_SIZE1,
 112           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 113         },
 114 #endif
 115         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 116           CONFIG_SYS_FSL_DRAM_SIZE1,
 117 #if defined(CONFIG_TFABOOT) || \
 118         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 119           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 120 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 121           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 122 #endif
 123           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 124         },
 125 #ifdef CONFIG_FSL_IFC
 126         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 127         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 128           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 129           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 130         },
 131 #endif
 132         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 133           CONFIG_SYS_FSL_DCSR_SIZE,
 134           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 135           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 136         },
 137         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 138           CONFIG_SYS_FSL_DRAM_SIZE2,
 139           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 140           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 141         },
 142 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 143         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 144           CONFIG_SYS_FSL_DRAM_SIZE3,
 145           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 146           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 147         },
 148 #endif
 149 #elif defined(CONFIG_FSL_LSCH2)
 150         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 151           CONFIG_SYS_FSL_CCSR_SIZE,
 152           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 153           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 154         },
 155         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 156           SYS_FSL_OCRAM_SPACE_SIZE,
 157           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 158         },
 159         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 160           CONFIG_SYS_FSL_DCSR_SIZE,
 161           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 162           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 163         },
 164         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 165           CONFIG_SYS_FSL_QSPI_SIZE,
 166           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 167         },
 168 #ifdef CONFIG_FSL_IFC
 169         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 170           CONFIG_SYS_FSL_IFC_SIZE,
 171           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 172         },
 173 #endif
 174         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 175           CONFIG_SYS_FSL_DRAM_SIZE1,
 176 #if defined(CONFIG_TFABOOT) || \
 177         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 178           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 179 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 180           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 181 #endif
 182           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 183         },
 184         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 185           CONFIG_SYS_FSL_DRAM_SIZE2,
 186           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 187           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 188         },
 189 #endif
 190         {},     /* list terminator */
 191 };
 192
 193 static struct mm_region final_map[] = {
 194 #ifdef CONFIG_FSL_LSCH3
 195         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 196           CONFIG_SYS_FSL_CCSR_SIZE,
 197           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 198           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 199         },
 200         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 201           SYS_FSL_OCRAM_SPACE_SIZE,
 202           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 203         },
 204         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 205           CONFIG_SYS_FSL_DRAM_SIZE1,
 206           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 207           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 208         },
 209         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 210           CONFIG_SYS_FSL_QSPI_SIZE1,
 211           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 212           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 213         },
 214         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 215           CONFIG_SYS_FSL_QSPI_SIZE2,
 216           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 217           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 218         },
 219 #ifdef CONFIG_FSL_IFC
 220         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 221           CONFIG_SYS_FSL_IFC_SIZE2,
 222           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 223           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 224         },
 225 #endif
 226         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 227           CONFIG_SYS_FSL_DCSR_SIZE,
 228           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 229           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 230         },
 231         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 232           CONFIG_SYS_FSL_MC_SIZE,
 233           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 234           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 235         },
 236         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 237           CONFIG_SYS_FSL_NI_SIZE,
 238           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 239           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 240         },
 241         /* For QBMAN portal, only the first 64MB is cache-enabled */
 242         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 243           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 244           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 245           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 246         },
 247         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 248           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 249           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 250           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 251           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 252         },
 253         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 254           CONFIG_SYS_PCIE1_PHYS_SIZE,
 255           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 256           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 257         },
 258         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 259           CONFIG_SYS_PCIE2_PHYS_SIZE,
 260           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 261           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 262         },
 263 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 264         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 265           CONFIG_SYS_PCIE3_PHYS_SIZE,
 266           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 267           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 268         },
 269 #endif
 270 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 271         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 272           CONFIG_SYS_PCIE4_PHYS_SIZE,
 273           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 274           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 275         },
 276 #endif
 277 #ifdef SYS_PCIE5_PHYS_ADDR
 278         { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
 279           SYS_PCIE5_PHYS_SIZE,
 280           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 281           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 282         },
 283 #endif
 284 #ifdef SYS_PCIE6_PHYS_ADDR
 285         { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
 286           SYS_PCIE6_PHYS_SIZE,
 287           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 288           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 289         },
 290 #endif
 291         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 292           CONFIG_SYS_FSL_WRIOP1_SIZE,
 293           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 294           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 295         },
 296         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 297           CONFIG_SYS_FSL_AIOP1_SIZE,
 298           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 299           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 300         },
 301         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 302           CONFIG_SYS_FSL_PEBUF_SIZE,
 303           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 304           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 305         },
 306         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 307           CONFIG_SYS_FSL_DRAM_SIZE2,
 308           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 309           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 310         },
 311 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 312         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 313           CONFIG_SYS_FSL_DRAM_SIZE3,
 314           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 315           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 316         },
 317 #endif
 318 #elif defined(CONFIG_FSL_LSCH2)
 319         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 320           CONFIG_SYS_FSL_BOOTROM_SIZE,
 321           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 322           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 323         },
 324         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 325           CONFIG_SYS_FSL_CCSR_SIZE,
 326           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 327           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 328         },
 329         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 330           SYS_FSL_OCRAM_SPACE_SIZE,
 331           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 332         },
 333         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 334           CONFIG_SYS_FSL_DCSR_SIZE,
 335           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 336           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 337         },
 338         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 339           CONFIG_SYS_FSL_QSPI_SIZE,
 340           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 341           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 342         },
 343 #ifdef CONFIG_FSL_IFC
 344         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 345           CONFIG_SYS_FSL_IFC_SIZE,
 346           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 347         },
 348 #endif
 349         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 350           CONFIG_SYS_FSL_DRAM_SIZE1,
 351           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 352           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 353         },
 354         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 355           CONFIG_SYS_FSL_QBMAN_SIZE,
 356           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 357           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 358         },
 359         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 360           CONFIG_SYS_FSL_DRAM_SIZE2,
 361           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 362           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 363         },
 364         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 365           CONFIG_SYS_PCIE1_PHYS_SIZE,
 366           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 367           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 368         },
 369         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 370           CONFIG_SYS_PCIE2_PHYS_SIZE,
 371           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 372           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 373         },
 374 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 375         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 376           CONFIG_SYS_PCIE3_PHYS_SIZE,
 377           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 378           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 379         },
 380 #endif
 381         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 382           CONFIG_SYS_FSL_DRAM_SIZE3,
 383           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 384           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 385         },
 386 #endif
 387 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 388         {},     /* space holder for secure mem */
 389 #endif
 390         {},
 391 };
 392
 393 struct mm_region *mem_map = early_map;
 394
 395 void cpu_name(char *name)
 396 {
 397         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 398         unsigned int i, svr, ver;
 399
 400         svr = gur_in32(&gur->svr);
 401         ver = SVR_SOC_VER(svr);
 402
 403         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 404                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 405                         strcpy(name, cpu_type_list[i].name);
 406 #ifdef CONFIG_ARCH_LX2160A
 407                         if (IS_C_PROCESSOR(svr))
 408                                 strcat(name, "C");
 409 #endif
 410
 411                         if (IS_E_PROCESSOR(svr))
 412                                 strcat(name, "E");
 413
 414                         sprintf(name + strlen(name), " Rev%d.%d",
 415                                 SVR_MAJ(svr), SVR_MIN(svr));
 416                         break;
 417                 }
 418
 419         if (i == ARRAY_SIZE(cpu_type_list))
 420                 strcpy(name, "unknown");
 421 }
 422
 423 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 424 /*
 425  * To start MMU before DDR is available, we create MMU table in SRAM.
 426  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 427  * levels of translation tables here to cover 40-bit address space.
 428  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 429  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 430  * Note, the debug print in cache_v8.c is not usable for debugging
 431  * these early MMU tables because UART is not yet available.
 432  */
 433 static inline void early_mmu_setup(void)
 434 {
 435         unsigned int el = current_el();
 436
 437         /* global data is already setup, no allocation yet */
 438         if (el == 3)
 439                 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 440         else
 441                 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 442         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 443         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 444
 445         /* Create early page tables */
 446         setup_pgtables();
 447
 448         /* point TTBR to the new table */
 449         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 450                           get_tcr(el, NULL, NULL) &
 451                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 452                           MEMORY_ATTRIBUTES);
 453
 454         set_sctlr(get_sctlr() | CR_M);
 455 }
 456
 457 static void fix_pcie_mmu_map(void)
 458 {
 459 #ifdef CONFIG_ARCH_LS2080A
 460         unsigned int i;
 461         u32 svr, ver;
 462         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 463
 464         svr = gur_in32(&gur->svr);
 465         ver = SVR_SOC_VER(svr);
 466
 467         /* Fix PCIE base and size for LS2088A */
 468         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 469             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 470             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 471                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 472                         switch (final_map[i].phys) {
 473                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 474                                 final_map[i].phys = 0x2000000000ULL;
 475                                 final_map[i].virt = 0x2000000000ULL;
 476                                 final_map[i].size = 0x800000000ULL;
 477                                 break;
 478                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 479                                 final_map[i].phys = 0x2800000000ULL;
 480                                 final_map[i].virt = 0x2800000000ULL;
 481                                 final_map[i].size = 0x800000000ULL;
 482                                 break;
 483 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 484                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 485                                 final_map[i].phys = 0x3000000000ULL;
 486                                 final_map[i].virt = 0x3000000000ULL;
 487                                 final_map[i].size = 0x800000000ULL;
 488                                 break;
 489 #endif
 490 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 491                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 492                                 final_map[i].phys = 0x3800000000ULL;
 493                                 final_map[i].virt = 0x3800000000ULL;
 494                                 final_map[i].size = 0x800000000ULL;
 495                                 break;
 496 #endif
 497                         default:
 498                                 break;
 499                         }
 500                 }
 501         }
 502 #endif
 503 }
 504
 505 /*
 506  * The final tables look similar to early tables, but different in detail.
 507  * These tables are in DRAM. Sub tables are added to enable cache for
 508  * QBMan and OCRAM.
 509  *
 510  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 511  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 512  */
 513 static inline void final_mmu_setup(void)
 514 {
 515         u64 tlb_addr_save = gd->arch.tlb_addr;
 516         unsigned int el = current_el();
 517         int index;
 518
 519         /* fix the final_map before filling in the block entries */
 520         fix_pcie_mmu_map();
 521
 522         mem_map = final_map;
 523
 524         /* Update mapping for DDR to actual size */
 525         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 526                 /*
 527                  * Find the entry for DDR mapping and update the address and
 528                  * size. Zero-sized mapping will be skipped when creating MMU
 529                  * table.
 530                  */
 531                 switch (final_map[index].virt) {
 532                 case CONFIG_SYS_FSL_DRAM_BASE1:
 533                         final_map[index].virt = gd->bd->bi_dram[0].start;
 534                         final_map[index].phys = gd->bd->bi_dram[0].start;
 535                         final_map[index].size = gd->bd->bi_dram[0].size;
 536                         break;
 537 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 538                 case CONFIG_SYS_FSL_DRAM_BASE2:
 539 #if (CONFIG_NR_DRAM_BANKS >= 2)
 540                         final_map[index].virt = gd->bd->bi_dram[1].start;
 541                         final_map[index].phys = gd->bd->bi_dram[1].start;
 542                         final_map[index].size = gd->bd->bi_dram[1].size;
 543 #else
 544                         final_map[index].size = 0;
 545 #endif
 546                 break;
 547 #endif
 548 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 549                 case CONFIG_SYS_FSL_DRAM_BASE3:
 550 #if (CONFIG_NR_DRAM_BANKS >= 3)
 551                         final_map[index].virt = gd->bd->bi_dram[2].start;
 552                         final_map[index].phys = gd->bd->bi_dram[2].start;
 553                         final_map[index].size = gd->bd->bi_dram[2].size;
 554 #else
 555                         final_map[index].size = 0;
 556 #endif
 557                 break;
 558 #endif
 559                 default:
 560                         break;
 561                 }
 562         }
 563
 564 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 565         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 566                 if (el == 3) {
 567                         /*
 568                          * Only use gd->arch.secure_ram if the address is
 569                          * recalculated. Align to 4KB for MMU table.
 570                          */
 571                         /* put page tables in secure ram */
 572                         index = ARRAY_SIZE(final_map) - 2;
 573                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 574                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 575                         final_map[index].phys = final_map[index].virt;
 576                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 577                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 578                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 579                         tlb_addr_save = gd->arch.tlb_addr;
 580                 } else {
 581                         /* Use allocated (board_f.c) memory for TLB */
 582                         tlb_addr_save = gd->arch.tlb_allocated;
 583                         gd->arch.tlb_addr = tlb_addr_save;
 584                 }
 585         }
 586 #endif
 587
 588         /* Reset the fill ptr */
 589         gd->arch.tlb_fillptr = tlb_addr_save;
 590
 591         /* Create normal system page tables */
 592         setup_pgtables();
 593
 594         /* Create emergency page tables */
 595         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 596         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 597         setup_pgtables();
 598         gd->arch.tlb_addr = tlb_addr_save;
 599
 600         /* Disable cache and MMU */
 601         dcache_disable();       /* TLBs are invalidated */
 602         invalidate_icache_all();
 603
 604         /* point TTBR to the new table */
 605         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 606                           MEMORY_ATTRIBUTES);
 607
 608         set_sctlr(get_sctlr() | CR_M);
 609 }
 610
 611 u64 get_page_table_size(void)
 612 {
 613         return 0x10000;
 614 }
 615
 616 int arch_cpu_init(void)
 617 {
 618         /*
 619          * This function is called before U-Boot relocates itself to speed up
 620          * on system running. It is not necessary to run if performance is not
 621          * critical. Skip if MMU is already enabled by SPL or other means.
 622          */
 623         if (get_sctlr() & CR_M)
 624                 return 0;
 625
 626         icache_enable();
 627         __asm_invalidate_dcache_all();
 628         __asm_invalidate_tlb_all();
 629         early_mmu_setup();
 630         set_sctlr(get_sctlr() | CR_C);
 631         return 0;
 632 }
 633
 634 void mmu_setup(void)
 635 {
 636         final_mmu_setup();
 637 }
 638
 639 /*
 640  * This function is called from common/board_r.c.
 641  * It recreates MMU table in main memory.
 642  */
 643 void enable_caches(void)
 644 {
 645         mmu_setup();
 646         __asm_invalidate_tlb_all();
 647         icache_enable();
 648         dcache_enable();
 649 }
 650 #endif  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 651
 652 #ifdef CONFIG_TFABOOT
 653 enum boot_src __get_boot_src(u32 porsr1)
 654 {
 655         enum boot_src src = BOOT_SOURCE_RESERVED;
 656         u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
 657 #if !defined(CONFIG_NXP_LSCH3_2)
 658         u32 val;
 659 #endif
 660         debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
 661
 662 #if defined(CONFIG_FSL_LSCH3)
 663 #if defined(CONFIG_NXP_LSCH3_2)
 664         switch (rcw_src) {
 665         case RCW_SRC_SDHC1_VAL:
 666                 src = BOOT_SOURCE_SD_MMC;
 667         break;
 668         case RCW_SRC_SDHC2_VAL:
 669                 src = BOOT_SOURCE_SD_MMC2;
 670         break;
 671         case RCW_SRC_I2C1_VAL:
 672                 src = BOOT_SOURCE_I2C1_EXTENDED;
 673         break;
 674         case RCW_SRC_FLEXSPI_NAND2K_VAL:
 675                 src = BOOT_SOURCE_XSPI_NAND;
 676         break;
 677         case RCW_SRC_FLEXSPI_NAND4K_VAL:
 678                 src = BOOT_SOURCE_XSPI_NAND;
 679         break;
 680         case RCW_SRC_RESERVED_1_VAL:
 681                 src = BOOT_SOURCE_RESERVED;
 682         break;
 683         case RCW_SRC_FLEXSPI_NOR_24B:
 684                 src = BOOT_SOURCE_XSPI_NOR;
 685         break;
 686         default:
 687                 src = BOOT_SOURCE_RESERVED;
 688         }
 689 #else
 690         val = rcw_src & RCW_SRC_TYPE_MASK;
 691         if (val == RCW_SRC_NOR_VAL) {
 692                 val = rcw_src & NOR_TYPE_MASK;
 693
 694                 switch (val) {
 695                 case NOR_16B_VAL:
 696                 case NOR_32B_VAL:
 697                         src = BOOT_SOURCE_IFC_NOR;
 698                 break;
 699                 default:
 700                         src = BOOT_SOURCE_RESERVED;
 701                 }
 702         } else {
 703                 /* RCW SRC Serial Flash */
 704                 val = rcw_src & RCW_SRC_SERIAL_MASK;
 705                 switch (val) {
 706                 case RCW_SRC_QSPI_VAL:
 707                 /* RCW SRC Serial NOR (QSPI) */
 708                         src = BOOT_SOURCE_QSPI_NOR;
 709                         break;
 710                 case RCW_SRC_SD_CARD_VAL:
 711                 /* RCW SRC SD Card */
 712                         src = BOOT_SOURCE_SD_MMC;
 713                         break;
 714                 case RCW_SRC_EMMC_VAL:
 715                 /* RCW SRC EMMC */
 716                         src = BOOT_SOURCE_SD_MMC;
 717                         break;
 718                 case RCW_SRC_I2C1_VAL:
 719                 /* RCW SRC I2C1 Extended */
 720                         src = BOOT_SOURCE_I2C1_EXTENDED;
 721                         break;
 722                 default:
 723                         src = BOOT_SOURCE_RESERVED;
 724                 }
 725         }
 726 #endif
 727 #elif defined(CONFIG_FSL_LSCH2)
 728         /* RCW SRC NAND */
 729         val = rcw_src & RCW_SRC_NAND_MASK;
 730         if (val == RCW_SRC_NAND_VAL) {
 731                 val = rcw_src & NAND_RESERVED_MASK;
 732                 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
 733                         src = BOOT_SOURCE_IFC_NAND;
 734
 735         } else {
 736                 /* RCW SRC NOR */
 737                 val = rcw_src & RCW_SRC_NOR_MASK;
 738                 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
 739                         src = BOOT_SOURCE_IFC_NOR;
 740                 } else {
 741                         switch (rcw_src) {
 742                         case QSPI_VAL1:
 743                         case QSPI_VAL2:
 744                                 src = BOOT_SOURCE_QSPI_NOR;
 745                                 break;
 746                         case SD_VAL:
 747                                 src = BOOT_SOURCE_SD_MMC;
 748                                 break;
 749                         default:
 750                                 src = BOOT_SOURCE_RESERVED;
 751                         }
 752                 }
 753         }
 754 #endif
 755
 756         if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
 757                 src = BOOT_SOURCE_QSPI_NOR;
 758
 759         debug("%s: src 0x%x\n", __func__, src);
 760         return src;
 761 }
 762
 763 enum boot_src get_boot_src(void)
 764 {
 765         struct pt_regs regs;
 766         u32 porsr1 = 0;
 767
 768 #if defined(CONFIG_FSL_LSCH3)
 769         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 770 #elif defined(CONFIG_FSL_LSCH2)
 771         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 772 #endif
 773
 774         if (current_el() == 2) {
 775                 regs.regs[0] = SIP_SVC_RCW;
 776
 777                 smc_call(&regs);
 778                 if (!regs.regs[0])
 779                         porsr1 = regs.regs[1];
 780         }
 781
 782         if (current_el() == 3 || !porsr1) {
 783 #ifdef CONFIG_FSL_LSCH3
 784                 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 785 #elif defined(CONFIG_FSL_LSCH2)
 786                 porsr1 = in_be32(&gur->porsr1);
 787 #endif
 788         }
 789
 790         debug("%s: porsr1 0x%x\n", __func__, porsr1);
 791
 792         return __get_boot_src(porsr1);
 793 }
 794
 795 #ifdef CONFIG_ENV_IS_IN_MMC
 796 int mmc_get_env_dev(void)
 797 {
 798         enum boot_src src = get_boot_src();
 799         int dev = CONFIG_SYS_MMC_ENV_DEV;
 800
 801         switch (src) {
 802         case BOOT_SOURCE_SD_MMC:
 803                 dev = 0;
 804                 break;
 805         case BOOT_SOURCE_SD_MMC2:
 806                 dev = 1;
 807                 break;
 808         default:
 809                 break;
 810         }
 811
 812         return dev;
 813 }
 814 #endif
 815
 816 enum env_location env_get_location(enum env_operation op, int prio)
 817 {
 818         enum boot_src src = get_boot_src();
 819         enum env_location env_loc = ENVL_NOWHERE;
 820
 821         if (prio)
 822                 return ENVL_UNKNOWN;
 823
 824 #ifdef  CONFIG_ENV_IS_NOWHERE
 825         return env_loc;
 826 #endif
 827
 828         switch (src) {
 829         case BOOT_SOURCE_IFC_NOR:
 830                 env_loc = ENVL_FLASH;
 831                 break;
 832         case BOOT_SOURCE_QSPI_NOR:
 833                 /* FALLTHROUGH */
 834         case BOOT_SOURCE_XSPI_NOR:
 835                 env_loc = ENVL_SPI_FLASH;
 836                 break;
 837         case BOOT_SOURCE_IFC_NAND:
 838                 /* FALLTHROUGH */
 839         case BOOT_SOURCE_QSPI_NAND:
 840                 /* FALLTHROUGH */
 841         case BOOT_SOURCE_XSPI_NAND:
 842                 env_loc = ENVL_NAND;
 843                 break;
 844         case BOOT_SOURCE_SD_MMC:
 845                 /* FALLTHROUGH */
 846         case BOOT_SOURCE_SD_MMC2:
 847                 env_loc =  ENVL_MMC;
 848                 break;
 849         case BOOT_SOURCE_I2C1_EXTENDED:
 850                 /* FALLTHROUGH */
 851         default:
 852                 break;
 853         }
 854
 855         return env_loc;
 856 }
 857 #endif  /* CONFIG_TFABOOT */
 858
 859 u32 initiator_type(u32 cluster, int init_id)
 860 {
 861         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 862         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 863         u32 type = 0;
 864
 865         type = gur_in32(&gur->tp_ityp[idx]);
 866         if (type & TP_ITYP_AV)
 867                 return type;
 868
 869         return 0;
 870 }
 871
 872 u32 cpu_pos_mask(void)
 873 {
 874         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 875         int i = 0;
 876         u32 cluster, type, mask = 0;
 877
 878         do {
 879                 int j;
 880
 881                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 882                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 883                         type = initiator_type(cluster, j);
 884                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 885                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 886                 }
 887                 i++;
 888         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 889
 890         return mask;
 891 }
 892
 893 u32 cpu_mask(void)
 894 {
 895         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 896         int i = 0, count = 0;
 897         u32 cluster, type, mask = 0;
 898
 899         do {
 900                 int j;
 901
 902                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 903                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 904                         type = initiator_type(cluster, j);
 905                         if (type) {
 906                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 907                                         mask |= 1 << count;
 908                                 count++;
 909                         }
 910                 }
 911                 i++;
 912         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 913
 914         return mask;
 915 }
 916
 917 /*
 918  * Return the number of cores on this SOC.
 919  */
 920 int cpu_numcores(void)
 921 {
 922         return hweight32(cpu_mask());
 923 }
 924
 925 int fsl_qoriq_core_to_cluster(unsigned int core)
 926 {
 927         struct ccsr_gur __iomem *gur =
 928                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 929         int i = 0, count = 0;
 930         u32 cluster;
 931
 932         do {
 933                 int j;
 934
 935                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 936                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 937                         if (initiator_type(cluster, j)) {
 938                                 if (count == core)
 939                                         return i;
 940                                 count++;
 941                         }
 942                 }
 943                 i++;
 944         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 945
 946         return -1;      /* cannot identify the cluster */
 947 }
 948
 949 u32 fsl_qoriq_core_to_type(unsigned int core)
 950 {
 951         struct ccsr_gur __iomem *gur =
 952                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 953         int i = 0, count = 0;
 954         u32 cluster, type;
 955
 956         do {
 957                 int j;
 958
 959                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 960                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 961                         type = initiator_type(cluster, j);
 962                         if (type) {
 963                                 if (count == core)
 964                                         return type;
 965                                 count++;
 966                         }
 967                 }
 968                 i++;
 969         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 970
 971         return -1;      /* cannot identify the cluster */
 972 }
 973
 974 #ifndef CONFIG_FSL_LSCH3
 975 uint get_svr(void)
 976 {
 977         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 978
 979         return gur_in32(&gur->svr);
 980 }
 981 #endif
 982
 983 #ifdef CONFIG_DISPLAY_CPUINFO
 984 int print_cpuinfo(void)
 985 {
 986         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 987         struct sys_info sysinfo;
 988         char buf[32];
 989         unsigned int i, core;
 990         u32 type, rcw, svr = gur_in32(&gur->svr);
 991
 992         puts("SoC: ");
 993
 994         cpu_name(buf);
 995         printf(" %s (0x%x)\n", buf, svr);
 996         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 997         get_sys_info(&sysinfo);
 998         puts("Clock Configuration:");
 999         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
1000                 if (!(i % 3))
1001                         puts("\n       ");
1002                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
1003                 printf("CPU%d(%s):%-4s MHz  ", core,
1004                        type == TY_ITYP_VER_A7 ? "A7 " :
1005                        (type == TY_ITYP_VER_A53 ? "A53" :
1006                        (type == TY_ITYP_VER_A57 ? "A57" :
1007                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
1008                        strmhz(buf, sysinfo.freq_processor[core]));
1009         }
1010         /* Display platform clock as Bus frequency. */
1011         printf("\n       Bus:      %-4s MHz  ",
1012                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1013         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1014 #ifdef CONFIG_SYS_DPAA_FMAN
1015         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1016 #endif
1017 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1018         if (soc_has_dp_ddr()) {
1019                 printf("     DP-DDR:   %-4s MT/s",
1020                        strmhz(buf, sysinfo.freq_ddrbus2));
1021         }
1022 #endif
1023         puts("\n");
1024
1025         /*
1026          * Display the RCW, so that no one gets confused as to what RCW
1027          * we're actually using for this boot.
1028          */
1029         puts("Reset Configuration Word (RCW):");
1030         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1031                 rcw = gur_in32(&gur->rcwsr[i]);
1032                 if ((i % 4) == 0)
1033                         printf("\n       %08x:", i * 4);
1034                 printf(" %08x", rcw);
1035         }
1036         puts("\n");
1037
1038         return 0;
1039 }
1040 #endif
1041
1042 #ifdef CONFIG_FSL_ESDHC
1043 int cpu_mmc_init(struct bd_info *bis)
1044 {
1045         return fsl_esdhc_mmc_init(bis);
1046 }
1047 #endif
1048
1049 int cpu_eth_init(struct bd_info *bis)
1050 {
1051         int error = 0;
1052
1053 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1054         error = fsl_mc_ldpaa_init(bis);
1055 #endif
1056 #ifdef CONFIG_FMAN_ENET
1057         fm_standard_init(bis);
1058 #endif
1059         return error;
1060 }
1061
1062 static inline int check_psci(void)
1063 {
1064         unsigned int psci_ver;
1065
1066         psci_ver = sec_firmware_support_psci_version();
1067         if (psci_ver == PSCI_INVALID_VER)
1068                 return 1;
1069
1070         return 0;
1071 }
1072
1073 static void config_core_prefetch(void)
1074 {
1075         char *buf = NULL;
1076         char buffer[HWCONFIG_BUFFER_SIZE];
1077         const char *prefetch_arg = NULL;
1078         size_t arglen;
1079         unsigned int mask;
1080         struct pt_regs regs;
1081
1082         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1083                 buf = buffer;
1084         else
1085                 return;
1086
1087         prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1088                                          &arglen, buf);
1089
1090         if (prefetch_arg) {
1091                 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1092                 if (mask & 0x1) {
1093                         printf("Core0 prefetch can't be disabled\n");
1094                         return;
1095                 }
1096
1097 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1098                 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1099                 regs.regs[1] = mask;
1100                 smc_call(&regs);
1101
1102                 if (regs.regs[0])
1103                         printf("Prefetch disable config failed for mask ");
1104                 else
1105                         printf("Prefetch disable config passed for mask ");
1106                 printf("0x%x\n", mask);
1107         }
1108 }
1109
1110 #ifdef CONFIG_PCIE_ECAM_GENERIC
1111 __weak void set_ecam_icids(void)
1112 {
1113 }
1114 #endif
1115
1116 int arch_early_init_r(void)
1117 {
1118 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1119         u32 svr_dev_id;
1120         /*
1121          * erratum A009635 is valid only for LS2080A SoC and
1122          * its personalitiesi
1123          */
1124         svr_dev_id = get_svr();
1125         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1126                 erratum_a009635();
1127 #endif
1128 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1129         erratum_a009942_check_cpo();
1130 #endif
1131         if (check_psci()) {
1132                 debug("PSCI: PSCI does not exist.\n");
1133
1134                 /* if PSCI does not exist, boot secondary cores here */
1135                 if (fsl_layerscape_wake_seconday_cores())
1136                         printf("Did not wake secondary cores\n");
1137         }
1138
1139         config_core_prefetch();
1140
1141 #ifdef CONFIG_SYS_HAS_SERDES
1142         fsl_serdes_init();
1143 #endif
1144 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1145         /* some dpmacs in armv8a based freescale layerscape SOCs can be
1146          * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1147          * EC*_PMUX(rgmii) bits in RCW.
1148          * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1149          * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1150          * Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes
1151          * precedence over SerDes protocol. i.e. in LX2160A if we select serdes
1152          * protocol that configures dpmac17 as SGMII and set the EC1_PMUX as
1153          * RGMII, then the dpmac is RGMII and not SGMII.
1154          *
1155          * Therefore, even thought fsl_rgmii_init is after fsl_serdes_init
1156          * function of SOC, the dpmac will be enabled as RGMII even if it was
1157          * also enabled before as SGMII. If ECx_PMUX is not configured for
1158          * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
1159          */
1160         fsl_rgmii_init();
1161 #endif
1162 #ifdef CONFIG_FMAN_ENET
1163 #ifndef CONFIG_DM_ETH
1164         fman_enet_init();
1165 #endif
1166 #endif
1167 #ifdef CONFIG_SYS_DPAA_QBMAN
1168         setup_qbman_portals();
1169 #endif
1170 #ifdef CONFIG_PCIE_ECAM_GENERIC
1171         set_ecam_icids();
1172 #endif
1173         return 0;
1174 }
1175
1176 int timer_init(void)
1177 {
1178         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1179 #ifdef CONFIG_FSL_LSCH3
1180         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1181 #endif
1182 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1183         defined(CONFIG_ARCH_LS1028A)
1184         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1185         u32 svr_dev_id;
1186 #endif
1187 #ifdef COUNTER_FREQUENCY_REAL
1188         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1189
1190         /* Update with accurate clock frequency */
1191         if (current_el() == 3)
1192                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1193 #endif
1194
1195 #ifdef CONFIG_FSL_LSCH3
1196         /* Enable timebase for all clusters.
1197          * It is safe to do so even some clusters are not enabled.
1198          */
1199         out_le32(cltbenr, 0xf);
1200 #endif
1201
1202 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1203         defined(CONFIG_ARCH_LS1028A)
1204         /*
1205          * In certain Layerscape SoCs, the clock for each core's
1206          * has an enable bit in the PMU Physical Core Time Base Enable
1207          * Register (PCTBENR), which allows the watchdog to operate.
1208          */
1209         setbits_le32(pctbenr, 0xff);
1210         /*
1211          * For LS2080A SoC and its personalities, timer controller
1212          * offset is different
1213          */
1214         svr_dev_id = get_svr();
1215         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1216                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1217
1218 #endif
1219
1220         /* Enable clock for timer
1221          * This is a global setting.
1222          */
1223         out_le32(cntcr, 0x1);
1224
1225         return 0;
1226 }
1227
1228 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1229
1230 void __efi_runtime reset_cpu(ulong addr)
1231 {
1232 #ifdef CONFIG_ARCH_LX2160A
1233         /* clear the RST_REQ_MSK and SW_RST_REQ */
1234         out_le32(rstcr, 0x0);
1235
1236         /* initiate the sw reset request */
1237         out_le32(rstcr, 0x1);
1238 #else
1239         u32 val;
1240
1241         /* Raise RESET_REQ_B */
1242         val = scfg_in32(rstcr);
1243         val |= 0x02;
1244         scfg_out32(rstcr, val);
1245 #endif
1246 }
1247
1248 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1249
1250 void __efi_runtime EFIAPI efi_reset_system(
1251                        enum efi_reset_type reset_type,
1252                        efi_status_t reset_status,
1253                        unsigned long data_size, void *reset_data)
1254 {
1255         switch (reset_type) {
1256         case EFI_RESET_COLD:
1257         case EFI_RESET_WARM:
1258         case EFI_RESET_PLATFORM_SPECIFIC:
1259                 reset_cpu(0);
1260                 break;
1261         case EFI_RESET_SHUTDOWN:
1262                 /* Nothing we can do */
1263                 break;
1264         }
1265
1266         while (1) { }
1267 }
1268
1269 efi_status_t efi_reset_system_init(void)
1270 {
1271         return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1272 }
1273
1274 #endif
1275
1276 /*
1277  * Calculate reserved memory with given memory bank
1278  * Return aligned memory size on success
1279  * Return (ram_size + needed size) for failure
1280  */
1281 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1282 {
1283         phys_size_t ram_top = ram_size;
1284
1285 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1286         ram_top = mc_get_dram_block_size();
1287         if (ram_top > ram_size)
1288                 return ram_size + ram_top;
1289
1290         ram_top = ram_size - ram_top;
1291         /* The start address of MC reserved memory needs to be aligned. */
1292         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1293 #endif
1294
1295         return ram_size - ram_top;
1296 }
1297
1298 phys_size_t get_effective_memsize(void)
1299 {
1300         phys_size_t ea_size, rem = 0;
1301
1302         /*
1303          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1304          * first region is 2GB space at 0x8000_0000. Secure memory needs to
1305          * allocated from first region. If the memory extends to  the second
1306          * region (or the third region if applicable), Management Complex (MC)
1307          * memory should be put into the highest region, i.e. the end of DDR
1308          * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1309          * U-Boot doesn't relocate itself into higher address. Should DDR be
1310          * configured to skip the first region, this function needs to be
1311          * adjusted.
1312          */
1313         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1314                 ea_size = CONFIG_MAX_MEM_MAPPED;
1315                 rem = gd->ram_size - ea_size;
1316         } else {
1317                 ea_size = gd->ram_size;
1318         }
1319
1320 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1321         /* Check if we have enough space for secure memory */
1322         if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1323                 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1324         else
1325                 printf("Error: No enough space for secure memory.\n");
1326 #endif
1327         /* Check if we have enough memory for MC */
1328         if (rem < board_reserve_ram_top(rem)) {
1329                 /* Not enough memory in high region to reserve */
1330                 if (ea_size > board_reserve_ram_top(ea_size))
1331                         ea_size -= board_reserve_ram_top(ea_size);
1332                 else
1333                         printf("Error: No enough space for reserved memory.\n");
1334         }
1335
1336         return ea_size;
1337 }
1338
1339 #ifdef CONFIG_TFABOOT
1340 phys_size_t tfa_get_dram_size(void)
1341 {
1342         struct pt_regs regs;
1343         phys_size_t dram_size = 0;
1344
1345         regs.regs[0] = SMC_DRAM_BANK_INFO;
1346         regs.regs[1] = -1;
1347
1348         smc_call(&regs);
1349         if (regs.regs[0])
1350                 return 0;
1351
1352         dram_size = regs.regs[1];
1353         return dram_size;
1354 }
1355
1356 static int tfa_dram_init_banksize(void)
1357 {
1358         int i = 0, ret = 0;
1359         struct pt_regs regs;
1360         phys_size_t dram_size = tfa_get_dram_size();
1361
1362         debug("dram_size %llx\n", dram_size);
1363
1364         if (!dram_size)
1365                 return -EINVAL;
1366
1367         do {
1368                 regs.regs[0] = SMC_DRAM_BANK_INFO;
1369                 regs.regs[1] = i;
1370
1371                 smc_call(&regs);
1372                 if (regs.regs[0]) {
1373                         ret = -EINVAL;
1374                         break;
1375                 }
1376
1377                 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1378                       regs.regs[2]);
1379                 gd->bd->bi_dram[i].start = regs.regs[1];
1380                 gd->bd->bi_dram[i].size = regs.regs[2];
1381
1382                 dram_size -= gd->bd->bi_dram[i].size;
1383
1384                 i++;
1385         } while (dram_size);
1386
1387         if (i > 0)
1388                 ret = 0;
1389
1390 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1391         /* Assign memory for MC */
1392 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1393         if (gd->bd->bi_dram[2].size >=
1394             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1395                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1396                             gd->bd->bi_dram[2].size -
1397                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1398         } else
1399 #endif
1400         {
1401                 if (gd->bd->bi_dram[1].size >=
1402                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1403                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1404                                 gd->bd->bi_dram[1].size -
1405                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1406                 } else if (gd->bd->bi_dram[0].size >
1407                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1408                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1409                                 gd->bd->bi_dram[0].size -
1410                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1411                 }
1412         }
1413 #endif  /* CONFIG_RESV_RAM */
1414
1415         return ret;
1416 }
1417 #endif
1418
1419 int dram_init_banksize(void)
1420 {
1421 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1422         phys_size_t dp_ddr_size;
1423 #endif
1424
1425 #ifdef CONFIG_TFABOOT
1426         if (!tfa_dram_init_banksize())
1427                 return 0;
1428 #endif
1429         /*
1430          * gd->ram_size has the total size of DDR memory, less reserved secure
1431          * memory. The DDR extends from low region to high region(s) presuming
1432          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1433          * the location of secure memory. gd->arch.resv_ram tracks the location
1434          * of reserved memory for Management Complex (MC). Because gd->ram_size
1435          * is reduced by this function if secure memory is reserved, checking
1436          * gd->arch.secure_ram should be done to avoid running it repeatedly.
1437          */
1438
1439 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1440         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1441                 debug("No need to run again, skip %s\n", __func__);
1442
1443                 return 0;
1444         }
1445 #endif
1446
1447         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1448         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1449                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1450                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1451                 gd->bd->bi_dram[1].size = gd->ram_size -
1452                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
1453 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1454                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1455                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1456                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1457                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
1458                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1459                 }
1460 #endif
1461         } else {
1462                 gd->bd->bi_dram[0].size = gd->ram_size;
1463         }
1464 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1465         if (gd->bd->bi_dram[0].size >
1466                                 CONFIG_SYS_MEM_RESERVE_SECURE) {
1467                 gd->bd->bi_dram[0].size -=
1468                                 CONFIG_SYS_MEM_RESERVE_SECURE;
1469                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1470                                       gd->bd->bi_dram[0].size;
1471                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1472                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1473         }
1474 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
1475
1476 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1477         /* Assign memory for MC */
1478 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1479         if (gd->bd->bi_dram[2].size >=
1480             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1481                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1482                             gd->bd->bi_dram[2].size -
1483                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1484         } else
1485 #endif
1486         {
1487                 if (gd->bd->bi_dram[1].size >=
1488                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1489                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1490                                 gd->bd->bi_dram[1].size -
1491                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1492                 } else if (gd->bd->bi_dram[0].size >
1493                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1494                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1495                                 gd->bd->bi_dram[0].size -
1496                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1497                 }
1498         }
1499 #endif  /* CONFIG_RESV_RAM */
1500
1501 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1502 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1503 #error "This SoC shouldn't have DP DDR"
1504 #endif
1505         if (soc_has_dp_ddr()) {
1506                 /* initialize DP-DDR here */
1507                 puts("DP-DDR:  ");
1508                 /*
1509                  * DDR controller use 0 as the base address for binding.
1510                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1511                  */
1512                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1513                                           CONFIG_DP_DDR_CTRL,
1514                                           CONFIG_DP_DDR_NUM_CTRLS,
1515                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1516                                           NULL, NULL, NULL);
1517                 if (dp_ddr_size) {
1518                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1519                         gd->bd->bi_dram[2].size = dp_ddr_size;
1520                 } else {
1521                         puts("Not detected");
1522                 }
1523         }
1524 #endif
1525
1526 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1527         debug("%s is called. gd->ram_size is reduced to %lu\n",
1528               __func__, (ulong)gd->ram_size);
1529 #endif
1530
1531         return 0;
1532 }
1533
1534 #if CONFIG_IS_ENABLED(EFI_LOADER)
1535 void efi_add_known_memory(void)
1536 {
1537         int i;
1538         phys_addr_t ram_start;
1539         phys_size_t ram_size;
1540
1541         /* Add RAM */
1542         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1543 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1544 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1545 #error "This SoC shouldn't have DP DDR"
1546 #endif
1547                 if (i == 2)
1548                         continue;       /* skip DP-DDR */
1549 #endif
1550                 ram_start = gd->bd->bi_dram[i].start;
1551                 ram_size = gd->bd->bi_dram[i].size;
1552 #ifdef CONFIG_RESV_RAM
1553                 if (gd->arch.resv_ram >= ram_start &&
1554                     gd->arch.resv_ram < ram_start + ram_size)
1555                         ram_size = gd->arch.resv_ram - ram_start;
1556 #endif
1557                 efi_add_memory_map(ram_start, ram_size,
1558                                    EFI_CONVENTIONAL_MEMORY);
1559         }
1560 }
1561 #endif
1562
1563 /*
1564  * Before DDR size is known, early MMU table have DDR mapped as device memory
1565  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1566  * needs to be set for these mappings.
1567  * If a special case configures DDR with holes in the mapping, the holes need
1568  * to be marked as invalid. This is not implemented in this function.
1569  */
1570 void update_early_mmu_table(void)
1571 {
1572         if (!gd->arch.tlb_addr)
1573                 return;
1574
1575         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1576                 mmu_change_region_attr(
1577                                         CONFIG_SYS_SDRAM_BASE,
1578                                         gd->ram_size,
1579                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1580                                         PTE_BLOCK_OUTER_SHARE           |
1581                                         PTE_BLOCK_NS                    |
1582                                         PTE_TYPE_VALID);
1583         } else {
1584                 mmu_change_region_attr(
1585                                         CONFIG_SYS_SDRAM_BASE,
1586                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1587                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1588                                         PTE_BLOCK_OUTER_SHARE           |
1589                                         PTE_BLOCK_NS                    |
1590                                         PTE_TYPE_VALID);
1591 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1592 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1593 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1594 #endif
1595                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1596                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
1597                         mmu_change_region_attr(
1598                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1599                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1600                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1601                                         PTE_BLOCK_OUTER_SHARE           |
1602                                         PTE_BLOCK_NS                    |
1603                                         PTE_TYPE_VALID);
1604                         mmu_change_region_attr(
1605                                         CONFIG_SYS_DDR_BLOCK3_BASE,
1606                                         gd->ram_size -
1607                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
1608                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1609                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1610                                         PTE_BLOCK_OUTER_SHARE           |
1611                                         PTE_BLOCK_NS                    |
1612                                         PTE_TYPE_VALID);
1613                 } else
1614 #endif
1615                 {
1616                         mmu_change_region_attr(
1617                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1618                                         gd->ram_size -
1619                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1620                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1621                                         PTE_BLOCK_OUTER_SHARE           |
1622                                         PTE_BLOCK_NS                    |
1623                                         PTE_TYPE_VALID);
1624                 }
1625         }
1626 }
1627
1628 __weak int dram_init(void)
1629 {
1630         fsl_initdram();
1631 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1632         defined(CONFIG_SPL_BUILD)
1633         /* This will break-before-make MMU for DDR */
1634         update_early_mmu_table();
1635 #endif
1636
1637         return 0;
1638 }
1639
1640 #ifdef CONFIG_ARCH_MISC_INIT
1641 __weak int serdes_misc_init(void)
1642 {
1643         return 0;
1644 }
1645
1646 int arch_misc_init(void)
1647 {
1648         serdes_misc_init();
1649
1650         return 0;
1651 }
1652 #endif