1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2019 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
10 #include <fsl_ddr_sdram.h>
15 #include <linux/errno.h>
16 #include <asm/system.h>
18 #include <asm/armv8/mmu.h>
20 #include <asm/arch/fsl_serdes.h>
21 #include <asm/arch/soc.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/speed.h>
24 #include <fsl_immap.h>
25 #include <asm/arch/mp.h>
26 #include <efi_loader.h>
27 #include <fsl-mc/fsl_mc.h>
28 #ifdef CONFIG_FSL_ESDHC
29 #include <fsl_esdhc.h>
31 #include <asm/armv8/sec_firmware.h>
32 #ifdef CONFIG_SYS_FSL_DDR
35 #include <asm/arch/clock.h>
37 #include <fsl_qbman.h>
40 #include <env_internal.h>
41 #ifdef CONFIG_CHAIN_OF_TRUST
42 #include <fsl_validate.h>
45 #include <linux/mii.h>
47 DECLARE_GLOBAL_DATA_PTR;
49 static struct cpu_type cpu_type_list[] = {
50 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
51 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
52 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
53 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
54 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
55 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
56 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
57 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
58 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
59 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
60 CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
61 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
62 CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
63 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
64 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
65 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
66 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
67 CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
68 CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
69 CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
70 CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
71 CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
72 CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
73 CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
74 CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
75 CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
76 CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
77 CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
80 #define EARLY_PGTABLE_SIZE 0x5000
81 static struct mm_region early_map[] = {
82 #ifdef CONFIG_FSL_LSCH3
83 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
84 CONFIG_SYS_FSL_CCSR_SIZE,
85 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
86 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
88 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
89 SYS_FSL_OCRAM_SPACE_SIZE,
90 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
92 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
93 CONFIG_SYS_FSL_QSPI_SIZE1,
94 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
96 /* For IFC Region #1, only the first 4MB is cache-enabled */
97 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
98 CONFIG_SYS_FSL_IFC_SIZE1_1,
99 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
101 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
102 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
103 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
104 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
106 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
107 CONFIG_SYS_FSL_IFC_SIZE1,
108 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
111 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
112 CONFIG_SYS_FSL_DRAM_SIZE1,
113 #if defined(CONFIG_TFABOOT) || \
114 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
115 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
116 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
117 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
119 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
121 #ifdef CONFIG_FSL_IFC
122 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
123 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
124 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
125 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
128 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
129 CONFIG_SYS_FSL_DCSR_SIZE,
130 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
131 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
133 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
134 CONFIG_SYS_FSL_DRAM_SIZE2,
135 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
136 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
138 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
139 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
140 CONFIG_SYS_FSL_DRAM_SIZE3,
141 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
142 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
145 #elif defined(CONFIG_FSL_LSCH2)
146 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
147 CONFIG_SYS_FSL_CCSR_SIZE,
148 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
149 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
151 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
152 SYS_FSL_OCRAM_SPACE_SIZE,
153 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
155 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
156 CONFIG_SYS_FSL_DCSR_SIZE,
157 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
158 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
160 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
161 CONFIG_SYS_FSL_QSPI_SIZE,
162 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
164 #ifdef CONFIG_FSL_IFC
165 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
166 CONFIG_SYS_FSL_IFC_SIZE,
167 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
170 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
171 CONFIG_SYS_FSL_DRAM_SIZE1,
172 #if defined(CONFIG_TFABOOT) || \
173 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
174 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
175 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
176 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
178 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
180 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
181 CONFIG_SYS_FSL_DRAM_SIZE2,
182 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
183 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
186 {}, /* list terminator */
189 static struct mm_region final_map[] = {
190 #ifdef CONFIG_FSL_LSCH3
191 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
192 CONFIG_SYS_FSL_CCSR_SIZE,
193 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
194 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
196 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
197 SYS_FSL_OCRAM_SPACE_SIZE,
198 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
200 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
201 CONFIG_SYS_FSL_DRAM_SIZE1,
202 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
203 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
205 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
206 CONFIG_SYS_FSL_QSPI_SIZE1,
207 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
208 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
210 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
211 CONFIG_SYS_FSL_QSPI_SIZE2,
212 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
213 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
215 #ifdef CONFIG_FSL_IFC
216 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
217 CONFIG_SYS_FSL_IFC_SIZE2,
218 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
219 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
222 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
223 CONFIG_SYS_FSL_DCSR_SIZE,
224 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
225 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
227 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
228 CONFIG_SYS_FSL_MC_SIZE,
229 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
230 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
232 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
233 CONFIG_SYS_FSL_NI_SIZE,
234 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
235 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
237 /* For QBMAN portal, only the first 64MB is cache-enabled */
238 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
239 CONFIG_SYS_FSL_QBMAN_SIZE_1,
240 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
241 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
243 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
244 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
245 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
246 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
247 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
249 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
250 CONFIG_SYS_PCIE1_PHYS_SIZE,
251 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
252 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
254 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
255 CONFIG_SYS_PCIE2_PHYS_SIZE,
256 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
257 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
259 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
260 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
261 CONFIG_SYS_PCIE3_PHYS_SIZE,
262 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
263 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
266 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
267 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
268 CONFIG_SYS_PCIE4_PHYS_SIZE,
269 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
270 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
273 #ifdef SYS_PCIE5_PHYS_ADDR
274 { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
276 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
277 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
280 #ifdef SYS_PCIE6_PHYS_ADDR
281 { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
283 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
284 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
287 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
288 CONFIG_SYS_FSL_WRIOP1_SIZE,
289 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
290 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
292 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
293 CONFIG_SYS_FSL_AIOP1_SIZE,
294 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
295 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
297 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
298 CONFIG_SYS_FSL_PEBUF_SIZE,
299 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
300 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
302 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
303 CONFIG_SYS_FSL_DRAM_SIZE2,
304 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
305 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
307 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
308 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
309 CONFIG_SYS_FSL_DRAM_SIZE3,
310 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
311 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
314 #elif defined(CONFIG_FSL_LSCH2)
315 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
316 CONFIG_SYS_FSL_BOOTROM_SIZE,
317 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
318 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
320 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
321 CONFIG_SYS_FSL_CCSR_SIZE,
322 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
323 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
325 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
326 SYS_FSL_OCRAM_SPACE_SIZE,
327 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
329 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
330 CONFIG_SYS_FSL_DCSR_SIZE,
331 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
332 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
334 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
335 CONFIG_SYS_FSL_QSPI_SIZE,
336 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
337 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
339 #ifdef CONFIG_FSL_IFC
340 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
341 CONFIG_SYS_FSL_IFC_SIZE,
342 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
345 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
346 CONFIG_SYS_FSL_DRAM_SIZE1,
347 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
348 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
350 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
351 CONFIG_SYS_FSL_QBMAN_SIZE,
352 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
353 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
355 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
356 CONFIG_SYS_FSL_DRAM_SIZE2,
357 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
358 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
360 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
361 CONFIG_SYS_PCIE1_PHYS_SIZE,
362 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
363 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
365 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
366 CONFIG_SYS_PCIE2_PHYS_SIZE,
367 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
368 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
370 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
371 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
372 CONFIG_SYS_PCIE3_PHYS_SIZE,
373 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
374 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
377 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
378 CONFIG_SYS_FSL_DRAM_SIZE3,
379 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
380 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
383 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
384 {}, /* space holder for secure mem */
389 struct mm_region *mem_map = early_map;
391 void cpu_name(char *name)
393 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
394 unsigned int i, svr, ver;
396 svr = gur_in32(&gur->svr);
397 ver = SVR_SOC_VER(svr);
399 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
400 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
401 strcpy(name, cpu_type_list[i].name);
402 #ifdef CONFIG_ARCH_LX2160A
403 if (IS_C_PROCESSOR(svr))
407 if (IS_E_PROCESSOR(svr))
410 sprintf(name + strlen(name), " Rev%d.%d",
411 SVR_MAJ(svr), SVR_MIN(svr));
415 if (i == ARRAY_SIZE(cpu_type_list))
416 strcpy(name, "unknown");
419 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
421 * To start MMU before DDR is available, we create MMU table in SRAM.
422 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
423 * levels of translation tables here to cover 40-bit address space.
424 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
425 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
426 * Note, the debug print in cache_v8.c is not usable for debugging
427 * these early MMU tables because UART is not yet available.
429 static inline void early_mmu_setup(void)
431 unsigned int el = current_el();
433 /* global data is already setup, no allocation yet */
435 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
437 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
438 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
439 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
441 /* Create early page tables */
444 /* point TTBR to the new table */
445 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
446 get_tcr(el, NULL, NULL) &
447 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
450 set_sctlr(get_sctlr() | CR_M);
453 static void fix_pcie_mmu_map(void)
455 #ifdef CONFIG_ARCH_LS2080A
458 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
460 svr = gur_in32(&gur->svr);
461 ver = SVR_SOC_VER(svr);
463 /* Fix PCIE base and size for LS2088A */
464 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
465 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
466 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
467 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
468 switch (final_map[i].phys) {
469 case CONFIG_SYS_PCIE1_PHYS_ADDR:
470 final_map[i].phys = 0x2000000000ULL;
471 final_map[i].virt = 0x2000000000ULL;
472 final_map[i].size = 0x800000000ULL;
474 case CONFIG_SYS_PCIE2_PHYS_ADDR:
475 final_map[i].phys = 0x2800000000ULL;
476 final_map[i].virt = 0x2800000000ULL;
477 final_map[i].size = 0x800000000ULL;
479 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
480 case CONFIG_SYS_PCIE3_PHYS_ADDR:
481 final_map[i].phys = 0x3000000000ULL;
482 final_map[i].virt = 0x3000000000ULL;
483 final_map[i].size = 0x800000000ULL;
486 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
487 case CONFIG_SYS_PCIE4_PHYS_ADDR:
488 final_map[i].phys = 0x3800000000ULL;
489 final_map[i].virt = 0x3800000000ULL;
490 final_map[i].size = 0x800000000ULL;
502 * The final tables look similar to early tables, but different in detail.
503 * These tables are in DRAM. Sub tables are added to enable cache for
506 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
507 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
509 static inline void final_mmu_setup(void)
511 u64 tlb_addr_save = gd->arch.tlb_addr;
512 unsigned int el = current_el();
515 /* fix the final_map before filling in the block entries */
520 /* Update mapping for DDR to actual size */
521 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
523 * Find the entry for DDR mapping and update the address and
524 * size. Zero-sized mapping will be skipped when creating MMU
527 switch (final_map[index].virt) {
528 case CONFIG_SYS_FSL_DRAM_BASE1:
529 final_map[index].virt = gd->bd->bi_dram[0].start;
530 final_map[index].phys = gd->bd->bi_dram[0].start;
531 final_map[index].size = gd->bd->bi_dram[0].size;
533 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
534 case CONFIG_SYS_FSL_DRAM_BASE2:
535 #if (CONFIG_NR_DRAM_BANKS >= 2)
536 final_map[index].virt = gd->bd->bi_dram[1].start;
537 final_map[index].phys = gd->bd->bi_dram[1].start;
538 final_map[index].size = gd->bd->bi_dram[1].size;
540 final_map[index].size = 0;
544 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
545 case CONFIG_SYS_FSL_DRAM_BASE3:
546 #if (CONFIG_NR_DRAM_BANKS >= 3)
547 final_map[index].virt = gd->bd->bi_dram[2].start;
548 final_map[index].phys = gd->bd->bi_dram[2].start;
549 final_map[index].size = gd->bd->bi_dram[2].size;
551 final_map[index].size = 0;
560 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
561 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
564 * Only use gd->arch.secure_ram if the address is
565 * recalculated. Align to 4KB for MMU table.
567 /* put page tables in secure ram */
568 index = ARRAY_SIZE(final_map) - 2;
569 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
570 final_map[index].virt = gd->arch.secure_ram & ~0x3;
571 final_map[index].phys = final_map[index].virt;
572 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
573 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
574 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
575 tlb_addr_save = gd->arch.tlb_addr;
577 /* Use allocated (board_f.c) memory for TLB */
578 tlb_addr_save = gd->arch.tlb_allocated;
579 gd->arch.tlb_addr = tlb_addr_save;
584 /* Reset the fill ptr */
585 gd->arch.tlb_fillptr = tlb_addr_save;
587 /* Create normal system page tables */
590 /* Create emergency page tables */
591 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
592 gd->arch.tlb_emerg = gd->arch.tlb_addr;
594 gd->arch.tlb_addr = tlb_addr_save;
596 /* Disable cache and MMU */
597 dcache_disable(); /* TLBs are invalidated */
598 invalidate_icache_all();
600 /* point TTBR to the new table */
601 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
604 set_sctlr(get_sctlr() | CR_M);
607 u64 get_page_table_size(void)
612 int arch_cpu_init(void)
615 * This function is called before U-Boot relocates itself to speed up
616 * on system running. It is not necessary to run if performance is not
617 * critical. Skip if MMU is already enabled by SPL or other means.
619 if (get_sctlr() & CR_M)
623 __asm_invalidate_dcache_all();
624 __asm_invalidate_tlb_all();
626 set_sctlr(get_sctlr() | CR_C);
636 * This function is called from common/board_r.c.
637 * It recreates MMU table in main memory.
639 void enable_caches(void)
642 __asm_invalidate_tlb_all();
646 #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
648 #ifdef CONFIG_TFABOOT
649 enum boot_src __get_boot_src(u32 porsr1)
651 enum boot_src src = BOOT_SOURCE_RESERVED;
652 u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
653 #if !defined(CONFIG_NXP_LSCH3_2)
656 debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
658 #if defined(CONFIG_FSL_LSCH3)
659 #if defined(CONFIG_NXP_LSCH3_2)
661 case RCW_SRC_SDHC1_VAL:
662 src = BOOT_SOURCE_SD_MMC;
664 case RCW_SRC_SDHC2_VAL:
665 src = BOOT_SOURCE_SD_MMC2;
667 case RCW_SRC_I2C1_VAL:
668 src = BOOT_SOURCE_I2C1_EXTENDED;
670 case RCW_SRC_FLEXSPI_NAND2K_VAL:
671 src = BOOT_SOURCE_XSPI_NAND;
673 case RCW_SRC_FLEXSPI_NAND4K_VAL:
674 src = BOOT_SOURCE_XSPI_NAND;
676 case RCW_SRC_RESERVED_1_VAL:
677 src = BOOT_SOURCE_RESERVED;
679 case RCW_SRC_FLEXSPI_NOR_24B:
680 src = BOOT_SOURCE_XSPI_NOR;
683 src = BOOT_SOURCE_RESERVED;
686 val = rcw_src & RCW_SRC_TYPE_MASK;
687 if (val == RCW_SRC_NOR_VAL) {
688 val = rcw_src & NOR_TYPE_MASK;
693 src = BOOT_SOURCE_IFC_NOR;
696 src = BOOT_SOURCE_RESERVED;
699 /* RCW SRC Serial Flash */
700 val = rcw_src & RCW_SRC_SERIAL_MASK;
702 case RCW_SRC_QSPI_VAL:
703 /* RCW SRC Serial NOR (QSPI) */
704 src = BOOT_SOURCE_QSPI_NOR;
706 case RCW_SRC_SD_CARD_VAL:
707 /* RCW SRC SD Card */
708 src = BOOT_SOURCE_SD_MMC;
710 case RCW_SRC_EMMC_VAL:
712 src = BOOT_SOURCE_SD_MMC;
714 case RCW_SRC_I2C1_VAL:
715 /* RCW SRC I2C1 Extended */
716 src = BOOT_SOURCE_I2C1_EXTENDED;
719 src = BOOT_SOURCE_RESERVED;
723 #elif defined(CONFIG_FSL_LSCH2)
725 val = rcw_src & RCW_SRC_NAND_MASK;
726 if (val == RCW_SRC_NAND_VAL) {
727 val = rcw_src & NAND_RESERVED_MASK;
728 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
729 src = BOOT_SOURCE_IFC_NAND;
733 val = rcw_src & RCW_SRC_NOR_MASK;
734 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
735 src = BOOT_SOURCE_IFC_NOR;
740 src = BOOT_SOURCE_QSPI_NOR;
743 src = BOOT_SOURCE_SD_MMC;
746 src = BOOT_SOURCE_RESERVED;
752 if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
753 src = BOOT_SOURCE_QSPI_NOR;
755 debug("%s: src 0x%x\n", __func__, src);
759 enum boot_src get_boot_src(void)
764 #if defined(CONFIG_FSL_LSCH3)
765 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
766 #elif defined(CONFIG_FSL_LSCH2)
767 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
770 if (current_el() == 2) {
771 regs.regs[0] = SIP_SVC_RCW;
775 porsr1 = regs.regs[1];
778 if (current_el() == 3 || !porsr1) {
779 #ifdef CONFIG_FSL_LSCH3
780 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
781 #elif defined(CONFIG_FSL_LSCH2)
782 porsr1 = in_be32(&gur->porsr1);
786 debug("%s: porsr1 0x%x\n", __func__, porsr1);
788 return __get_boot_src(porsr1);
791 #ifdef CONFIG_ENV_IS_IN_MMC
792 int mmc_get_env_dev(void)
794 enum boot_src src = get_boot_src();
795 int dev = CONFIG_SYS_MMC_ENV_DEV;
798 case BOOT_SOURCE_SD_MMC:
801 case BOOT_SOURCE_SD_MMC2:
812 enum env_location env_get_location(enum env_operation op, int prio)
814 enum boot_src src = get_boot_src();
815 enum env_location env_loc = ENVL_NOWHERE;
820 #ifdef CONFIG_ENV_IS_NOWHERE
825 case BOOT_SOURCE_IFC_NOR:
826 env_loc = ENVL_FLASH;
828 case BOOT_SOURCE_QSPI_NOR:
830 case BOOT_SOURCE_XSPI_NOR:
831 env_loc = ENVL_SPI_FLASH;
833 case BOOT_SOURCE_IFC_NAND:
835 case BOOT_SOURCE_QSPI_NAND:
837 case BOOT_SOURCE_XSPI_NAND:
840 case BOOT_SOURCE_SD_MMC:
842 case BOOT_SOURCE_SD_MMC2:
845 case BOOT_SOURCE_I2C1_EXTENDED:
853 #endif /* CONFIG_TFABOOT */
855 u32 initiator_type(u32 cluster, int init_id)
857 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
858 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
861 type = gur_in32(&gur->tp_ityp[idx]);
862 if (type & TP_ITYP_AV)
868 u32 cpu_pos_mask(void)
870 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
872 u32 cluster, type, mask = 0;
877 cluster = gur_in32(&gur->tp_cluster[i].lower);
878 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
879 type = initiator_type(cluster, j);
880 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
881 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
884 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
891 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
892 int i = 0, count = 0;
893 u32 cluster, type, mask = 0;
898 cluster = gur_in32(&gur->tp_cluster[i].lower);
899 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
900 type = initiator_type(cluster, j);
902 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
908 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
914 * Return the number of cores on this SOC.
916 int cpu_numcores(void)
918 return hweight32(cpu_mask());
921 int fsl_qoriq_core_to_cluster(unsigned int core)
923 struct ccsr_gur __iomem *gur =
924 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
925 int i = 0, count = 0;
931 cluster = gur_in32(&gur->tp_cluster[i].lower);
932 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
933 if (initiator_type(cluster, j)) {
940 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
942 return -1; /* cannot identify the cluster */
945 u32 fsl_qoriq_core_to_type(unsigned int core)
947 struct ccsr_gur __iomem *gur =
948 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
949 int i = 0, count = 0;
955 cluster = gur_in32(&gur->tp_cluster[i].lower);
956 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
957 type = initiator_type(cluster, j);
965 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
967 return -1; /* cannot identify the cluster */
970 #ifndef CONFIG_FSL_LSCH3
973 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
975 return gur_in32(&gur->svr);
979 #ifdef CONFIG_DISPLAY_CPUINFO
980 int print_cpuinfo(void)
982 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
983 struct sys_info sysinfo;
985 unsigned int i, core;
986 u32 type, rcw, svr = gur_in32(&gur->svr);
991 printf(" %s (0x%x)\n", buf, svr);
992 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
993 get_sys_info(&sysinfo);
994 puts("Clock Configuration:");
995 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
998 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
999 printf("CPU%d(%s):%-4s MHz ", core,
1000 type == TY_ITYP_VER_A7 ? "A7 " :
1001 (type == TY_ITYP_VER_A53 ? "A53" :
1002 (type == TY_ITYP_VER_A57 ? "A57" :
1003 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
1004 strmhz(buf, sysinfo.freq_processor[core]));
1006 /* Display platform clock as Bus frequency. */
1007 printf("\n Bus: %-4s MHz ",
1008 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1009 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1010 #ifdef CONFIG_SYS_DPAA_FMAN
1011 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1013 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1014 if (soc_has_dp_ddr()) {
1015 printf(" DP-DDR: %-4s MT/s",
1016 strmhz(buf, sysinfo.freq_ddrbus2));
1022 * Display the RCW, so that no one gets confused as to what RCW
1023 * we're actually using for this boot.
1025 puts("Reset Configuration Word (RCW):");
1026 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1027 rcw = gur_in32(&gur->rcwsr[i]);
1029 printf("\n %08x:", i * 4);
1030 printf(" %08x", rcw);
1038 #ifdef CONFIG_FSL_ESDHC
1039 int cpu_mmc_init(bd_t *bis)
1041 return fsl_esdhc_mmc_init(bis);
1045 int cpu_eth_init(bd_t *bis)
1049 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1050 error = fsl_mc_ldpaa_init(bis);
1052 #ifdef CONFIG_FMAN_ENET
1053 fm_standard_init(bis);
1058 static inline int check_psci(void)
1060 unsigned int psci_ver;
1062 psci_ver = sec_firmware_support_psci_version();
1063 if (psci_ver == PSCI_INVALID_VER)
1069 static void config_core_prefetch(void)
1072 char buffer[HWCONFIG_BUFFER_SIZE];
1073 const char *prefetch_arg = NULL;
1076 struct pt_regs regs;
1078 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1083 prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1087 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1089 printf("Core0 prefetch can't be disabled\n");
1093 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1094 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1095 regs.regs[1] = mask;
1099 printf("Prefetch disable config failed for mask ");
1101 printf("Prefetch disable config passed for mask ");
1102 printf("0x%x\n", mask);
1106 #ifdef CONFIG_PCIE_ECAM_GENERIC
1107 __weak void set_ecam_icids(void)
1112 int arch_early_init_r(void)
1114 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1117 * erratum A009635 is valid only for LS2080A SoC and
1118 * its personalitiesi
1120 svr_dev_id = get_svr();
1121 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1124 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1125 erratum_a009942_check_cpo();
1128 debug("PSCI: PSCI does not exist.\n");
1130 /* if PSCI does not exist, boot secondary cores here */
1131 if (fsl_layerscape_wake_seconday_cores())
1132 printf("Did not wake secondary cores\n");
1135 config_core_prefetch();
1137 #ifdef CONFIG_SYS_HAS_SERDES
1140 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1141 /* some dpmacs in armv8a based freescale layerscape SOCs can be
1142 * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1143 * EC*_PMUX(rgmii) bits in RCW.
1144 * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1145 * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1146 * Now if a dpmac is enabled by serdes bits then it takes precedence
1147 * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
1148 * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
1149 * then the dpmac is SGMII and not RGMII.
1151 * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
1152 * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
1153 * or not? if it is (fsl_serdes_init has already enabled the dpmac),
1154 * then don't enable it.
1158 #ifdef CONFIG_FMAN_ENET
1161 #ifdef CONFIG_SYS_DPAA_QBMAN
1162 setup_qbman_portals();
1164 #ifdef CONFIG_PCIE_ECAM_GENERIC
1170 int timer_init(void)
1172 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1173 #ifdef CONFIG_FSL_LSCH3
1174 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1176 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1177 defined(CONFIG_ARCH_LS1028A)
1178 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1181 #ifdef COUNTER_FREQUENCY_REAL
1182 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1184 /* Update with accurate clock frequency */
1185 if (current_el() == 3)
1186 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1189 #ifdef CONFIG_FSL_LSCH3
1190 /* Enable timebase for all clusters.
1191 * It is safe to do so even some clusters are not enabled.
1193 out_le32(cltbenr, 0xf);
1196 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1197 defined(CONFIG_ARCH_LS1028A)
1199 * In certain Layerscape SoCs, the clock for each core's
1200 * has an enable bit in the PMU Physical Core Time Base Enable
1201 * Register (PCTBENR), which allows the watchdog to operate.
1203 setbits_le32(pctbenr, 0xff);
1205 * For LS2080A SoC and its personalities, timer controller
1206 * offset is different
1208 svr_dev_id = get_svr();
1209 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1210 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1214 /* Enable clock for timer
1215 * This is a global setting.
1217 out_le32(cntcr, 0x1);
1222 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1224 void __efi_runtime reset_cpu(ulong addr)
1228 #ifdef CONFIG_ARCH_LX2160A
1229 val = in_le32(rstcr);
1231 out_le32(rstcr, val);
1233 /* Raise RESET_REQ_B */
1234 val = scfg_in32(rstcr);
1236 scfg_out32(rstcr, val);
1240 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1242 void __efi_runtime EFIAPI efi_reset_system(
1243 enum efi_reset_type reset_type,
1244 efi_status_t reset_status,
1245 unsigned long data_size, void *reset_data)
1247 switch (reset_type) {
1248 case EFI_RESET_COLD:
1249 case EFI_RESET_WARM:
1250 case EFI_RESET_PLATFORM_SPECIFIC:
1253 case EFI_RESET_SHUTDOWN:
1254 /* Nothing we can do */
1261 efi_status_t efi_reset_system_init(void)
1263 return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1269 * Calculate reserved memory with given memory bank
1270 * Return aligned memory size on success
1271 * Return (ram_size + needed size) for failure
1273 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1275 phys_size_t ram_top = ram_size;
1277 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1278 ram_top = mc_get_dram_block_size();
1279 if (ram_top > ram_size)
1280 return ram_size + ram_top;
1282 ram_top = ram_size - ram_top;
1283 /* The start address of MC reserved memory needs to be aligned. */
1284 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1287 return ram_size - ram_top;
1290 phys_size_t get_effective_memsize(void)
1292 phys_size_t ea_size, rem = 0;
1295 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1296 * first region is 2GB space at 0x8000_0000. Secure memory needs to
1297 * allocated from first region. If the memory extends to the second
1298 * region (or the third region if applicable), Management Complex (MC)
1299 * memory should be put into the highest region, i.e. the end of DDR
1300 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1301 * U-Boot doesn't relocate itself into higher address. Should DDR be
1302 * configured to skip the first region, this function needs to be
1305 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1306 ea_size = CONFIG_MAX_MEM_MAPPED;
1307 rem = gd->ram_size - ea_size;
1309 ea_size = gd->ram_size;
1312 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1313 /* Check if we have enough space for secure memory */
1314 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1315 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1317 printf("Error: No enough space for secure memory.\n");
1319 /* Check if we have enough memory for MC */
1320 if (rem < board_reserve_ram_top(rem)) {
1321 /* Not enough memory in high region to reserve */
1322 if (ea_size > board_reserve_ram_top(ea_size))
1323 ea_size -= board_reserve_ram_top(ea_size);
1325 printf("Error: No enough space for reserved memory.\n");
1331 #ifdef CONFIG_TFABOOT
1332 phys_size_t tfa_get_dram_size(void)
1334 struct pt_regs regs;
1335 phys_size_t dram_size = 0;
1337 regs.regs[0] = SMC_DRAM_BANK_INFO;
1344 dram_size = regs.regs[1];
1348 static int tfa_dram_init_banksize(void)
1351 struct pt_regs regs;
1352 phys_size_t dram_size = tfa_get_dram_size();
1354 debug("dram_size %llx\n", dram_size);
1360 regs.regs[0] = SMC_DRAM_BANK_INFO;
1369 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1371 gd->bd->bi_dram[i].start = regs.regs[1];
1372 gd->bd->bi_dram[i].size = regs.regs[2];
1374 dram_size -= gd->bd->bi_dram[i].size;
1377 } while (dram_size);
1382 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1383 /* Assign memory for MC */
1384 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1385 if (gd->bd->bi_dram[2].size >=
1386 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1387 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1388 gd->bd->bi_dram[2].size -
1389 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1393 if (gd->bd->bi_dram[1].size >=
1394 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1395 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1396 gd->bd->bi_dram[1].size -
1397 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1398 } else if (gd->bd->bi_dram[0].size >
1399 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1400 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1401 gd->bd->bi_dram[0].size -
1402 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1405 #endif /* CONFIG_RESV_RAM */
1411 int dram_init_banksize(void)
1413 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1414 phys_size_t dp_ddr_size;
1417 #ifdef CONFIG_TFABOOT
1418 if (!tfa_dram_init_banksize())
1422 * gd->ram_size has the total size of DDR memory, less reserved secure
1423 * memory. The DDR extends from low region to high region(s) presuming
1424 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1425 * the location of secure memory. gd->arch.resv_ram tracks the location
1426 * of reserved memory for Management Complex (MC). Because gd->ram_size
1427 * is reduced by this function if secure memory is reserved, checking
1428 * gd->arch.secure_ram should be done to avoid running it repeatedly.
1431 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1432 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1433 debug("No need to run again, skip %s\n", __func__);
1439 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1440 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1441 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1442 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1443 gd->bd->bi_dram[1].size = gd->ram_size -
1444 CONFIG_SYS_DDR_BLOCK1_SIZE;
1445 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1446 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1447 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1448 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1449 CONFIG_SYS_DDR_BLOCK2_SIZE;
1450 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1454 gd->bd->bi_dram[0].size = gd->ram_size;
1456 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1457 if (gd->bd->bi_dram[0].size >
1458 CONFIG_SYS_MEM_RESERVE_SECURE) {
1459 gd->bd->bi_dram[0].size -=
1460 CONFIG_SYS_MEM_RESERVE_SECURE;
1461 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1462 gd->bd->bi_dram[0].size;
1463 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1464 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1466 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
1468 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1469 /* Assign memory for MC */
1470 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1471 if (gd->bd->bi_dram[2].size >=
1472 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1473 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1474 gd->bd->bi_dram[2].size -
1475 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1479 if (gd->bd->bi_dram[1].size >=
1480 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1481 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1482 gd->bd->bi_dram[1].size -
1483 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1484 } else if (gd->bd->bi_dram[0].size >
1485 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1486 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1487 gd->bd->bi_dram[0].size -
1488 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1491 #endif /* CONFIG_RESV_RAM */
1493 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1494 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1495 #error "This SoC shouldn't have DP DDR"
1497 if (soc_has_dp_ddr()) {
1498 /* initialize DP-DDR here */
1501 * DDR controller use 0 as the base address for binding.
1502 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1504 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1506 CONFIG_DP_DDR_NUM_CTRLS,
1507 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1510 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1511 gd->bd->bi_dram[2].size = dp_ddr_size;
1513 puts("Not detected");
1518 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1519 debug("%s is called. gd->ram_size is reduced to %lu\n",
1520 __func__, (ulong)gd->ram_size);
1526 #if CONFIG_IS_ENABLED(EFI_LOADER)
1527 void efi_add_known_memory(void)
1530 phys_addr_t ram_start, start;
1531 phys_size_t ram_size;
1535 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1536 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1537 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1538 #error "This SoC shouldn't have DP DDR"
1541 continue; /* skip DP-DDR */
1543 ram_start = gd->bd->bi_dram[i].start;
1544 ram_size = gd->bd->bi_dram[i].size;
1545 #ifdef CONFIG_RESV_RAM
1546 if (gd->arch.resv_ram >= ram_start &&
1547 gd->arch.resv_ram < ram_start + ram_size)
1548 ram_size = gd->arch.resv_ram - ram_start;
1550 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1551 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1553 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1560 * Before DDR size is known, early MMU table have DDR mapped as device memory
1561 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1562 * needs to be set for these mappings.
1563 * If a special case configures DDR with holes in the mapping, the holes need
1564 * to be marked as invalid. This is not implemented in this function.
1566 void update_early_mmu_table(void)
1568 if (!gd->arch.tlb_addr)
1571 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1572 mmu_change_region_attr(
1573 CONFIG_SYS_SDRAM_BASE,
1575 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1576 PTE_BLOCK_OUTER_SHARE |
1580 mmu_change_region_attr(
1581 CONFIG_SYS_SDRAM_BASE,
1582 CONFIG_SYS_DDR_BLOCK1_SIZE,
1583 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1584 PTE_BLOCK_OUTER_SHARE |
1587 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1588 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1589 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1591 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1592 CONFIG_SYS_DDR_BLOCK2_SIZE) {
1593 mmu_change_region_attr(
1594 CONFIG_SYS_DDR_BLOCK2_BASE,
1595 CONFIG_SYS_DDR_BLOCK2_SIZE,
1596 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1597 PTE_BLOCK_OUTER_SHARE |
1600 mmu_change_region_attr(
1601 CONFIG_SYS_DDR_BLOCK3_BASE,
1603 CONFIG_SYS_DDR_BLOCK1_SIZE -
1604 CONFIG_SYS_DDR_BLOCK2_SIZE,
1605 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1606 PTE_BLOCK_OUTER_SHARE |
1612 mmu_change_region_attr(
1613 CONFIG_SYS_DDR_BLOCK2_BASE,
1615 CONFIG_SYS_DDR_BLOCK1_SIZE,
1616 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1617 PTE_BLOCK_OUTER_SHARE |
1624 __weak int dram_init(void)
1627 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1628 defined(CONFIG_SPL_BUILD)
1629 /* This will break-before-make MMU for DDR */
1630 update_early_mmu_table();
1636 #ifdef CONFIG_ARCH_MISC_INIT
1637 __weak int serdes_misc_init(void)
1642 int arch_misc_init(void)