1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2020 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
10 #include <fsl_ddr_sdram.h>
16 #include <asm/cache.h>
17 #include <asm/global_data.h>
19 #include <asm/ptrace.h>
20 #include <linux/errno.h>
21 #include <asm/system.h>
23 #include <asm/armv8/mmu.h>
25 #include <asm/arch/fsl_serdes.h>
26 #include <asm/arch/soc.h>
27 #include <asm/arch/cpu.h>
28 #include <asm/arch/speed.h>
29 #include <fsl_immap.h>
30 #include <asm/arch/mp.h>
31 #include <efi_loader.h>
32 #include <fsl-mc/fsl_mc.h>
33 #ifdef CONFIG_FSL_ESDHC
34 #include <fsl_esdhc.h>
36 #include <asm/armv8/sec_firmware.h>
37 #ifdef CONFIG_SYS_FSL_DDR
40 #include <asm/arch/clock.h>
42 #include <fsl_qbman.h>
45 #include <env_internal.h>
46 #ifdef CONFIG_CHAIN_OF_TRUST
47 #include <fsl_validate.h>
50 #include <linux/mii.h>
52 DECLARE_GLOBAL_DATA_PTR;
54 static struct cpu_type cpu_type_list[] = {
55 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
56 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
57 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
58 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
59 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
60 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
61 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
62 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
63 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
64 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
65 CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
66 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
67 CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
68 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
69 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
70 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
71 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
72 CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
73 CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
74 CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
75 CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
76 CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
77 CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
78 CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
79 CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
80 CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
81 CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
82 CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
83 CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
84 CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
85 CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
88 #define EARLY_PGTABLE_SIZE 0x5000
89 static struct mm_region early_map[] = {
90 #ifdef CONFIG_FSL_LSCH3
91 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
92 CONFIG_SYS_FSL_CCSR_SIZE,
93 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
94 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
96 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
97 SYS_FSL_OCRAM_SPACE_SIZE,
98 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
100 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
101 CONFIG_SYS_FSL_QSPI_SIZE1,
102 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
103 #ifdef CONFIG_FSL_IFC
104 /* For IFC Region #1, only the first 4MB is cache-enabled */
105 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
106 CONFIG_SYS_FSL_IFC_SIZE1_1,
107 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
109 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
110 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
111 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
112 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
114 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
115 CONFIG_SYS_FSL_IFC_SIZE1,
116 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
119 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
120 CONFIG_SYS_FSL_DRAM_SIZE1,
121 #if defined(CONFIG_TFABOOT) || \
122 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
123 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
124 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
125 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
127 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
129 #ifdef CONFIG_FSL_IFC
130 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
131 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
132 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
133 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
136 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
137 CONFIG_SYS_FSL_DCSR_SIZE,
138 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
139 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
141 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
142 CONFIG_SYS_FSL_DRAM_SIZE2,
143 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
144 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
146 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
147 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
148 CONFIG_SYS_FSL_DRAM_SIZE3,
149 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
150 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
153 #elif defined(CONFIG_FSL_LSCH2)
154 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
155 CONFIG_SYS_FSL_CCSR_SIZE,
156 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
157 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
159 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
160 SYS_FSL_OCRAM_SPACE_SIZE,
161 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
163 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
164 CONFIG_SYS_FSL_DCSR_SIZE,
165 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
166 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
168 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
169 CONFIG_SYS_FSL_QSPI_SIZE,
170 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
172 #ifdef CONFIG_FSL_IFC
173 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
174 CONFIG_SYS_FSL_IFC_SIZE,
175 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
178 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
179 CONFIG_SYS_FSL_DRAM_SIZE1,
180 #if defined(CONFIG_TFABOOT) || \
181 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
182 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
183 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
184 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
186 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
188 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
189 CONFIG_SYS_FSL_DRAM_SIZE2,
190 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
191 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
194 {}, /* list terminator */
197 static struct mm_region final_map[] = {
198 #ifdef CONFIG_FSL_LSCH3
199 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
200 CONFIG_SYS_FSL_CCSR_SIZE,
201 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
202 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
204 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
205 SYS_FSL_OCRAM_SPACE_SIZE,
206 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
208 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
209 CONFIG_SYS_FSL_DRAM_SIZE1,
210 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
211 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
213 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
214 CONFIG_SYS_FSL_QSPI_SIZE1,
215 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
216 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
218 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
219 CONFIG_SYS_FSL_QSPI_SIZE2,
220 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
221 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
223 #ifdef CONFIG_FSL_IFC
224 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
225 CONFIG_SYS_FSL_IFC_SIZE2,
226 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
227 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
230 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
231 CONFIG_SYS_FSL_DCSR_SIZE,
232 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
233 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
235 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
236 CONFIG_SYS_FSL_MC_SIZE,
237 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
238 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
240 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
241 CONFIG_SYS_FSL_NI_SIZE,
242 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
243 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
245 /* For QBMAN portal, only the first 64MB is cache-enabled */
246 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
247 CONFIG_SYS_FSL_QBMAN_SIZE_1,
248 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
249 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
251 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
252 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
253 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
254 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
255 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
257 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
258 CONFIG_SYS_PCIE1_PHYS_SIZE,
259 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
260 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
262 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
263 CONFIG_SYS_PCIE2_PHYS_SIZE,
264 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
265 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
267 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
268 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
269 CONFIG_SYS_PCIE3_PHYS_SIZE,
270 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
271 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
274 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
275 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
276 CONFIG_SYS_PCIE4_PHYS_SIZE,
277 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
278 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
281 #ifdef SYS_PCIE5_PHYS_ADDR
282 { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
284 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
285 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
288 #ifdef SYS_PCIE6_PHYS_ADDR
289 { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
291 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
292 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
295 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
296 CONFIG_SYS_FSL_WRIOP1_SIZE,
297 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
298 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
300 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
301 CONFIG_SYS_FSL_AIOP1_SIZE,
302 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
303 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
305 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
306 CONFIG_SYS_FSL_PEBUF_SIZE,
307 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
308 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
310 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
311 CONFIG_SYS_FSL_DRAM_SIZE2,
312 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
313 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
315 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
316 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
317 CONFIG_SYS_FSL_DRAM_SIZE3,
318 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
319 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
322 #elif defined(CONFIG_FSL_LSCH2)
323 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
324 CONFIG_SYS_FSL_BOOTROM_SIZE,
325 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
326 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
328 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
329 CONFIG_SYS_FSL_CCSR_SIZE,
330 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
331 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
333 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
334 SYS_FSL_OCRAM_SPACE_SIZE,
335 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
337 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
338 CONFIG_SYS_FSL_DCSR_SIZE,
339 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
340 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
342 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
343 CONFIG_SYS_FSL_QSPI_SIZE,
344 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
345 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
347 #ifdef CONFIG_FSL_IFC
348 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
349 CONFIG_SYS_FSL_IFC_SIZE,
350 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
353 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
354 CONFIG_SYS_FSL_DRAM_SIZE1,
355 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
356 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
358 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
359 CONFIG_SYS_FSL_QBMAN_SIZE,
360 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
361 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
363 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
364 CONFIG_SYS_FSL_DRAM_SIZE2,
365 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
366 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
368 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
369 CONFIG_SYS_PCIE1_PHYS_SIZE,
370 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
371 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
373 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
374 CONFIG_SYS_PCIE2_PHYS_SIZE,
375 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
376 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
378 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
379 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
380 CONFIG_SYS_PCIE3_PHYS_SIZE,
381 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
382 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
385 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
386 CONFIG_SYS_FSL_DRAM_SIZE3,
387 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
388 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
391 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
392 {}, /* space holder for secure mem */
397 struct mm_region *mem_map = early_map;
399 void cpu_name(char *name)
401 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
402 unsigned int i, svr, ver;
404 svr = gur_in32(&gur->svr);
405 ver = SVR_SOC_VER(svr);
407 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
408 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
409 strcpy(name, cpu_type_list[i].name);
410 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
411 if (IS_C_PROCESSOR(svr))
415 if (IS_E_PROCESSOR(svr))
418 sprintf(name + strlen(name), " Rev%d.%d",
419 SVR_MAJ(svr), SVR_MIN(svr));
423 if (i == ARRAY_SIZE(cpu_type_list))
424 strcpy(name, "unknown");
427 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
429 * To start MMU before DDR is available, we create MMU table in SRAM.
430 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
431 * levels of translation tables here to cover 40-bit address space.
432 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
433 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
434 * Note, the debug print in cache_v8.c is not usable for debugging
435 * these early MMU tables because UART is not yet available.
437 static inline void early_mmu_setup(void)
439 unsigned int el = current_el();
441 /* global data is already setup, no allocation yet */
443 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
445 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
446 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
447 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
449 /* Create early page tables */
452 /* point TTBR to the new table */
453 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
454 get_tcr(el, NULL, NULL) &
455 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
458 set_sctlr(get_sctlr() | CR_M);
461 static void fix_pcie_mmu_map(void)
463 #ifdef CONFIG_ARCH_LS2080A
466 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
468 svr = gur_in32(&gur->svr);
469 ver = SVR_SOC_VER(svr);
471 /* Fix PCIE base and size for LS2088A */
472 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
473 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
474 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
475 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
476 switch (final_map[i].phys) {
477 case CONFIG_SYS_PCIE1_PHYS_ADDR:
478 final_map[i].phys = 0x2000000000ULL;
479 final_map[i].virt = 0x2000000000ULL;
480 final_map[i].size = 0x800000000ULL;
482 case CONFIG_SYS_PCIE2_PHYS_ADDR:
483 final_map[i].phys = 0x2800000000ULL;
484 final_map[i].virt = 0x2800000000ULL;
485 final_map[i].size = 0x800000000ULL;
487 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
488 case CONFIG_SYS_PCIE3_PHYS_ADDR:
489 final_map[i].phys = 0x3000000000ULL;
490 final_map[i].virt = 0x3000000000ULL;
491 final_map[i].size = 0x800000000ULL;
494 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
495 case CONFIG_SYS_PCIE4_PHYS_ADDR:
496 final_map[i].phys = 0x3800000000ULL;
497 final_map[i].virt = 0x3800000000ULL;
498 final_map[i].size = 0x800000000ULL;
510 * The final tables look similar to early tables, but different in detail.
511 * These tables are in DRAM. Sub tables are added to enable cache for
514 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
515 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
517 static inline void final_mmu_setup(void)
519 u64 tlb_addr_save = gd->arch.tlb_addr;
520 unsigned int el = current_el();
523 /* fix the final_map before filling in the block entries */
528 /* Update mapping for DDR to actual size */
529 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
531 * Find the entry for DDR mapping and update the address and
532 * size. Zero-sized mapping will be skipped when creating MMU
535 switch (final_map[index].virt) {
536 case CONFIG_SYS_FSL_DRAM_BASE1:
537 final_map[index].virt = gd->bd->bi_dram[0].start;
538 final_map[index].phys = gd->bd->bi_dram[0].start;
539 final_map[index].size = gd->bd->bi_dram[0].size;
541 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
542 case CONFIG_SYS_FSL_DRAM_BASE2:
543 #if (CONFIG_NR_DRAM_BANKS >= 2)
544 final_map[index].virt = gd->bd->bi_dram[1].start;
545 final_map[index].phys = gd->bd->bi_dram[1].start;
546 final_map[index].size = gd->bd->bi_dram[1].size;
548 final_map[index].size = 0;
552 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
553 case CONFIG_SYS_FSL_DRAM_BASE3:
554 #if (CONFIG_NR_DRAM_BANKS >= 3)
555 final_map[index].virt = gd->bd->bi_dram[2].start;
556 final_map[index].phys = gd->bd->bi_dram[2].start;
557 final_map[index].size = gd->bd->bi_dram[2].size;
559 final_map[index].size = 0;
568 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
569 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
572 * Only use gd->arch.secure_ram if the address is
573 * recalculated. Align to 4KB for MMU table.
575 /* put page tables in secure ram */
576 index = ARRAY_SIZE(final_map) - 2;
577 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
578 final_map[index].virt = gd->arch.secure_ram & ~0x3;
579 final_map[index].phys = final_map[index].virt;
580 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
581 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
582 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
583 tlb_addr_save = gd->arch.tlb_addr;
585 /* Use allocated (board_f.c) memory for TLB */
586 tlb_addr_save = gd->arch.tlb_allocated;
587 gd->arch.tlb_addr = tlb_addr_save;
592 /* Reset the fill ptr */
593 gd->arch.tlb_fillptr = tlb_addr_save;
595 /* Create normal system page tables */
598 /* Create emergency page tables */
599 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
600 gd->arch.tlb_emerg = gd->arch.tlb_addr;
602 gd->arch.tlb_addr = tlb_addr_save;
604 /* Disable cache and MMU */
605 dcache_disable(); /* TLBs are invalidated */
606 invalidate_icache_all();
608 /* point TTBR to the new table */
609 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
612 set_sctlr(get_sctlr() | CR_M);
615 u64 get_page_table_size(void)
620 int arch_cpu_init(void)
623 * This function is called before U-Boot relocates itself to speed up
624 * on system running. It is not necessary to run if performance is not
625 * critical. Skip if MMU is already enabled by SPL or other means.
627 if (get_sctlr() & CR_M)
631 __asm_invalidate_dcache_all();
632 __asm_invalidate_tlb_all();
634 set_sctlr(get_sctlr() | CR_C);
644 * This function is called from common/board_r.c.
645 * It recreates MMU table in main memory.
647 void enable_caches(void)
650 __asm_invalidate_tlb_all();
654 #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
656 #ifdef CONFIG_TFABOOT
657 enum boot_src __get_boot_src(u32 porsr1)
659 enum boot_src src = BOOT_SOURCE_RESERVED;
660 u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
661 #if !defined(CONFIG_NXP_LSCH3_2)
664 debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
666 #if defined(CONFIG_FSL_LSCH3)
667 #if defined(CONFIG_NXP_LSCH3_2)
669 case RCW_SRC_SDHC1_VAL:
670 src = BOOT_SOURCE_SD_MMC;
672 case RCW_SRC_SDHC2_VAL:
673 src = BOOT_SOURCE_SD_MMC2;
675 case RCW_SRC_I2C1_VAL:
676 src = BOOT_SOURCE_I2C1_EXTENDED;
678 case RCW_SRC_FLEXSPI_NAND2K_VAL:
679 src = BOOT_SOURCE_XSPI_NAND;
681 case RCW_SRC_FLEXSPI_NAND4K_VAL:
682 src = BOOT_SOURCE_XSPI_NAND;
684 case RCW_SRC_RESERVED_1_VAL:
685 src = BOOT_SOURCE_RESERVED;
687 case RCW_SRC_FLEXSPI_NOR_24B:
688 src = BOOT_SOURCE_XSPI_NOR;
691 src = BOOT_SOURCE_RESERVED;
694 val = rcw_src & RCW_SRC_TYPE_MASK;
695 if (val == RCW_SRC_NOR_VAL) {
696 val = rcw_src & NOR_TYPE_MASK;
701 src = BOOT_SOURCE_IFC_NOR;
704 src = BOOT_SOURCE_RESERVED;
707 /* RCW SRC Serial Flash */
708 val = rcw_src & RCW_SRC_SERIAL_MASK;
710 case RCW_SRC_QSPI_VAL:
711 /* RCW SRC Serial NOR (QSPI) */
712 src = BOOT_SOURCE_QSPI_NOR;
714 case RCW_SRC_SD_CARD_VAL:
715 /* RCW SRC SD Card */
716 src = BOOT_SOURCE_SD_MMC;
718 case RCW_SRC_EMMC_VAL:
720 src = BOOT_SOURCE_SD_MMC;
722 case RCW_SRC_I2C1_VAL:
723 /* RCW SRC I2C1 Extended */
724 src = BOOT_SOURCE_I2C1_EXTENDED;
727 src = BOOT_SOURCE_RESERVED;
731 #elif defined(CONFIG_FSL_LSCH2)
733 val = rcw_src & RCW_SRC_NAND_MASK;
734 if (val == RCW_SRC_NAND_VAL) {
735 val = rcw_src & NAND_RESERVED_MASK;
736 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
737 src = BOOT_SOURCE_IFC_NAND;
741 val = rcw_src & RCW_SRC_NOR_MASK;
742 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
743 src = BOOT_SOURCE_IFC_NOR;
748 src = BOOT_SOURCE_QSPI_NOR;
751 src = BOOT_SOURCE_SD_MMC;
754 src = BOOT_SOURCE_RESERVED;
760 if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
761 src = BOOT_SOURCE_QSPI_NOR;
763 debug("%s: src 0x%x\n", __func__, src);
767 enum boot_src get_boot_src(void)
772 #if defined(CONFIG_FSL_LSCH3)
773 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
774 #elif defined(CONFIG_FSL_LSCH2)
775 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
778 if (current_el() == 2) {
779 regs.regs[0] = SIP_SVC_RCW;
783 porsr1 = regs.regs[1];
786 if (current_el() == 3 || !porsr1) {
787 #ifdef CONFIG_FSL_LSCH3
788 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
789 #elif defined(CONFIG_FSL_LSCH2)
790 porsr1 = in_be32(&gur->porsr1);
794 debug("%s: porsr1 0x%x\n", __func__, porsr1);
796 return __get_boot_src(porsr1);
799 #ifdef CONFIG_ENV_IS_IN_MMC
800 int mmc_get_env_dev(void)
802 enum boot_src src = get_boot_src();
803 int dev = CONFIG_SYS_MMC_ENV_DEV;
806 case BOOT_SOURCE_SD_MMC:
809 case BOOT_SOURCE_SD_MMC2:
820 enum env_location env_get_location(enum env_operation op, int prio)
822 enum boot_src src = get_boot_src();
823 enum env_location env_loc = ENVL_NOWHERE;
828 #ifdef CONFIG_ENV_IS_NOWHERE
833 case BOOT_SOURCE_IFC_NOR:
834 env_loc = ENVL_FLASH;
836 case BOOT_SOURCE_QSPI_NOR:
838 case BOOT_SOURCE_XSPI_NOR:
839 env_loc = ENVL_SPI_FLASH;
841 case BOOT_SOURCE_IFC_NAND:
843 case BOOT_SOURCE_QSPI_NAND:
845 case BOOT_SOURCE_XSPI_NAND:
848 case BOOT_SOURCE_SD_MMC:
850 case BOOT_SOURCE_SD_MMC2:
853 case BOOT_SOURCE_I2C1_EXTENDED:
861 #endif /* CONFIG_TFABOOT */
863 u32 initiator_type(u32 cluster, int init_id)
865 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
866 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
869 type = gur_in32(&gur->tp_ityp[idx]);
870 if (type & TP_ITYP_AV)
876 u32 cpu_pos_mask(void)
878 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
880 u32 cluster, type, mask = 0;
885 cluster = gur_in32(&gur->tp_cluster[i].lower);
886 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
887 type = initiator_type(cluster, j);
888 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
889 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
892 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
899 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
900 int i = 0, count = 0;
901 u32 cluster, type, mask = 0;
906 cluster = gur_in32(&gur->tp_cluster[i].lower);
907 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
908 type = initiator_type(cluster, j);
910 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
916 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
922 * Return the number of cores on this SOC.
924 int cpu_numcores(void)
926 return hweight32(cpu_mask());
929 int fsl_qoriq_core_to_cluster(unsigned int core)
931 struct ccsr_gur __iomem *gur =
932 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
933 int i = 0, count = 0;
939 cluster = gur_in32(&gur->tp_cluster[i].lower);
940 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
941 if (initiator_type(cluster, j)) {
948 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
950 return -1; /* cannot identify the cluster */
953 u32 fsl_qoriq_core_to_type(unsigned int core)
955 struct ccsr_gur __iomem *gur =
956 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
957 int i = 0, count = 0;
963 cluster = gur_in32(&gur->tp_cluster[i].lower);
964 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
965 type = initiator_type(cluster, j);
973 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
975 return -1; /* cannot identify the cluster */
978 #ifndef CONFIG_FSL_LSCH3
981 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
983 return gur_in32(&gur->svr);
987 #ifdef CONFIG_DISPLAY_CPUINFO
988 int print_cpuinfo(void)
990 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
991 struct sys_info sysinfo;
993 unsigned int i, core;
994 u32 type, rcw, svr = gur_in32(&gur->svr);
999 printf(" %s (0x%x)\n", buf, svr);
1000 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
1001 get_sys_info(&sysinfo);
1002 puts("Clock Configuration:");
1003 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
1006 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
1007 printf("CPU%d(%s):%-4s MHz ", core,
1008 type == TY_ITYP_VER_A7 ? "A7 " :
1009 (type == TY_ITYP_VER_A53 ? "A53" :
1010 (type == TY_ITYP_VER_A57 ? "A57" :
1011 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
1012 strmhz(buf, sysinfo.freq_processor[core]));
1014 /* Display platform clock as Bus frequency. */
1015 printf("\n Bus: %-4s MHz ",
1016 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1017 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1018 #ifdef CONFIG_SYS_DPAA_FMAN
1019 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1021 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1022 if (soc_has_dp_ddr()) {
1023 printf(" DP-DDR: %-4s MT/s",
1024 strmhz(buf, sysinfo.freq_ddrbus2));
1030 * Display the RCW, so that no one gets confused as to what RCW
1031 * we're actually using for this boot.
1033 puts("Reset Configuration Word (RCW):");
1034 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1035 rcw = gur_in32(&gur->rcwsr[i]);
1037 printf("\n %08x:", i * 4);
1038 printf(" %08x", rcw);
1046 #ifdef CONFIG_FSL_ESDHC
1047 int cpu_mmc_init(struct bd_info *bis)
1049 return fsl_esdhc_mmc_init(bis);
1053 int cpu_eth_init(struct bd_info *bis)
1057 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1058 error = fsl_mc_ldpaa_init(bis);
1060 #ifdef CONFIG_FMAN_ENET
1061 fm_standard_init(bis);
1066 int check_psci(void)
1068 unsigned int psci_ver;
1070 psci_ver = sec_firmware_support_psci_version();
1071 if (psci_ver == PSCI_INVALID_VER)
1077 static void config_core_prefetch(void)
1080 char buffer[HWCONFIG_BUFFER_SIZE];
1081 const char *prefetch_arg = NULL;
1084 struct pt_regs regs;
1086 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1091 prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1095 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1097 printf("Core0 prefetch can't be disabled\n");
1101 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1102 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1103 regs.regs[1] = mask;
1107 printf("Prefetch disable config failed for mask ");
1109 printf("Prefetch disable config passed for mask ");
1110 printf("0x%x\n", mask);
1114 #ifdef CONFIG_PCIE_ECAM_GENERIC
1115 __weak void set_ecam_icids(void)
1120 int arch_early_init_r(void)
1122 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1125 * erratum A009635 is valid only for LS2080A SoC and
1126 * its personalitiesi
1128 svr_dev_id = get_svr();
1129 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1132 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1133 erratum_a009942_check_cpo();
1136 debug("PSCI: PSCI does not exist.\n");
1138 /* if PSCI does not exist, boot secondary cores here */
1139 if (fsl_layerscape_wake_seconday_cores())
1140 printf("Did not wake secondary cores\n");
1143 config_core_prefetch();
1145 #ifdef CONFIG_SYS_HAS_SERDES
1148 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1149 /* some dpmacs in armv8a based freescale layerscape SOCs can be
1150 * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
1151 * EC*_PMUX(rgmii) bits in RCW.
1152 * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1153 * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1154 * Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes
1155 * precedence over SerDes protocol. i.e. in LX2160A if we select serdes
1156 * protocol that configures dpmac17 as SGMII and set the EC1_PMUX as
1157 * RGMII, then the dpmac is RGMII and not SGMII.
1159 * Therefore, even thought fsl_rgmii_init is after fsl_serdes_init
1160 * function of SOC, the dpmac will be enabled as RGMII even if it was
1161 * also enabled before as SGMII. If ECx_PMUX is not configured for
1162 * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
1166 #ifdef CONFIG_FMAN_ENET
1167 #ifndef CONFIG_DM_ETH
1171 #ifdef CONFIG_SYS_DPAA_QBMAN
1172 setup_qbman_portals();
1174 #ifdef CONFIG_PCIE_ECAM_GENERIC
1180 int timer_init(void)
1182 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1183 #ifdef CONFIG_FSL_LSCH3
1184 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1186 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1187 defined(CONFIG_ARCH_LS1028A)
1188 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1191 #ifdef COUNTER_FREQUENCY_REAL
1192 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1194 /* Update with accurate clock frequency */
1195 if (current_el() == 3)
1196 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1199 #ifdef CONFIG_FSL_LSCH3
1200 /* Enable timebase for all clusters.
1201 * It is safe to do so even some clusters are not enabled.
1203 out_le32(cltbenr, 0xf);
1206 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1207 defined(CONFIG_ARCH_LS1028A)
1209 * In certain Layerscape SoCs, the clock for each core's
1210 * has an enable bit in the PMU Physical Core Time Base Enable
1211 * Register (PCTBENR), which allows the watchdog to operate.
1213 setbits_le32(pctbenr, 0xff);
1215 * For LS2080A SoC and its personalities, timer controller
1216 * offset is different
1218 svr_dev_id = get_svr();
1219 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1220 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1224 /* Enable clock for timer
1225 * This is a global setting.
1227 out_le32(cntcr, 0x1);
1232 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1234 void __efi_runtime reset_cpu(void)
1236 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
1237 /* clear the RST_REQ_MSK and SW_RST_REQ */
1238 out_le32(rstcr, 0x0);
1240 /* initiate the sw reset request */
1241 out_le32(rstcr, 0x1);
1245 /* Raise RESET_REQ_B */
1246 val = scfg_in32(rstcr);
1248 scfg_out32(rstcr, val);
1252 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1254 void __efi_runtime EFIAPI efi_reset_system(
1255 enum efi_reset_type reset_type,
1256 efi_status_t reset_status,
1257 unsigned long data_size, void *reset_data)
1259 switch (reset_type) {
1260 case EFI_RESET_COLD:
1261 case EFI_RESET_WARM:
1262 case EFI_RESET_PLATFORM_SPECIFIC:
1265 case EFI_RESET_SHUTDOWN:
1266 /* Nothing we can do */
1273 efi_status_t efi_reset_system_init(void)
1275 return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1281 * Calculate reserved memory with given memory bank
1282 * Return aligned memory size on success
1283 * Return (ram_size + needed size) for failure
1285 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1287 phys_size_t ram_top = ram_size;
1289 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1290 ram_top = mc_get_dram_block_size();
1291 if (ram_top > ram_size)
1292 return ram_size + ram_top;
1294 ram_top = ram_size - ram_top;
1295 /* The start address of MC reserved memory needs to be aligned. */
1296 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1299 return ram_size - ram_top;
1302 phys_size_t get_effective_memsize(void)
1304 phys_size_t ea_size, rem = 0;
1307 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1308 * first region is 2GB space at 0x8000_0000. Secure memory needs to
1309 * allocated from first region. If the memory extends to the second
1310 * region (or the third region if applicable), Management Complex (MC)
1311 * memory should be put into the highest region, i.e. the end of DDR
1312 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1313 * U-Boot doesn't relocate itself into higher address. Should DDR be
1314 * configured to skip the first region, this function needs to be
1317 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1318 ea_size = CONFIG_MAX_MEM_MAPPED;
1319 rem = gd->ram_size - ea_size;
1321 ea_size = gd->ram_size;
1324 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1325 /* Check if we have enough space for secure memory */
1326 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1327 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1329 printf("Error: No enough space for secure memory.\n");
1331 /* Check if we have enough memory for MC */
1332 if (rem < board_reserve_ram_top(rem)) {
1333 /* Not enough memory in high region to reserve */
1334 if (ea_size > board_reserve_ram_top(ea_size))
1335 ea_size -= board_reserve_ram_top(ea_size);
1337 printf("Error: No enough space for reserved memory.\n");
1343 #ifdef CONFIG_TFABOOT
1344 phys_size_t tfa_get_dram_size(void)
1346 struct pt_regs regs;
1347 phys_size_t dram_size = 0;
1349 regs.regs[0] = SMC_DRAM_BANK_INFO;
1356 dram_size = regs.regs[1];
1360 static int tfa_dram_init_banksize(void)
1363 struct pt_regs regs;
1364 phys_size_t dram_size = tfa_get_dram_size();
1366 debug("dram_size %llx\n", dram_size);
1372 regs.regs[0] = SMC_DRAM_BANK_INFO;
1381 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1383 gd->bd->bi_dram[i].start = regs.regs[1];
1384 gd->bd->bi_dram[i].size = regs.regs[2];
1386 dram_size -= gd->bd->bi_dram[i].size;
1389 } while (dram_size);
1394 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1395 /* Assign memory for MC */
1396 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1397 if (gd->bd->bi_dram[2].size >=
1398 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1399 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1400 gd->bd->bi_dram[2].size -
1401 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1405 if (gd->bd->bi_dram[1].size >=
1406 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1407 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1408 gd->bd->bi_dram[1].size -
1409 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1410 } else if (gd->bd->bi_dram[0].size >
1411 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1412 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1413 gd->bd->bi_dram[0].size -
1414 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1417 #endif /* CONFIG_RESV_RAM */
1423 int dram_init_banksize(void)
1425 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1426 phys_size_t dp_ddr_size;
1429 #ifdef CONFIG_TFABOOT
1430 if (!tfa_dram_init_banksize())
1434 * gd->ram_size has the total size of DDR memory, less reserved secure
1435 * memory. The DDR extends from low region to high region(s) presuming
1436 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1437 * the location of secure memory. gd->arch.resv_ram tracks the location
1438 * of reserved memory for Management Complex (MC). Because gd->ram_size
1439 * is reduced by this function if secure memory is reserved, checking
1440 * gd->arch.secure_ram should be done to avoid running it repeatedly.
1443 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1444 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1445 debug("No need to run again, skip %s\n", __func__);
1451 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1452 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1453 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1454 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1455 gd->bd->bi_dram[1].size = gd->ram_size -
1456 CONFIG_SYS_DDR_BLOCK1_SIZE;
1457 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1458 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1459 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1460 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1461 CONFIG_SYS_DDR_BLOCK2_SIZE;
1462 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1466 gd->bd->bi_dram[0].size = gd->ram_size;
1468 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1469 if (gd->bd->bi_dram[0].size >
1470 CONFIG_SYS_MEM_RESERVE_SECURE) {
1471 gd->bd->bi_dram[0].size -=
1472 CONFIG_SYS_MEM_RESERVE_SECURE;
1473 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1474 gd->bd->bi_dram[0].size;
1475 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1476 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1478 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
1480 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1481 /* Assign memory for MC */
1482 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1483 if (gd->bd->bi_dram[2].size >=
1484 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1485 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1486 gd->bd->bi_dram[2].size -
1487 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1491 if (gd->bd->bi_dram[1].size >=
1492 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1493 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1494 gd->bd->bi_dram[1].size -
1495 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1496 } else if (gd->bd->bi_dram[0].size >
1497 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1498 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1499 gd->bd->bi_dram[0].size -
1500 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1503 #endif /* CONFIG_RESV_RAM */
1505 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1506 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1507 #error "This SoC shouldn't have DP DDR"
1509 if (soc_has_dp_ddr()) {
1510 /* initialize DP-DDR here */
1513 * DDR controller use 0 as the base address for binding.
1514 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1516 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1518 CONFIG_DP_DDR_NUM_CTRLS,
1519 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1522 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1523 gd->bd->bi_dram[2].size = dp_ddr_size;
1525 puts("Not detected");
1530 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1531 debug("%s is called. gd->ram_size is reduced to %lu\n",
1532 __func__, (ulong)gd->ram_size);
1538 #if CONFIG_IS_ENABLED(EFI_LOADER)
1539 void efi_add_known_memory(void)
1542 phys_addr_t ram_start;
1543 phys_size_t ram_size;
1546 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1547 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1548 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1549 #error "This SoC shouldn't have DP DDR"
1552 continue; /* skip DP-DDR */
1554 ram_start = gd->bd->bi_dram[i].start;
1555 ram_size = gd->bd->bi_dram[i].size;
1556 #ifdef CONFIG_RESV_RAM
1557 if (gd->arch.resv_ram >= ram_start &&
1558 gd->arch.resv_ram < ram_start + ram_size)
1559 ram_size = gd->arch.resv_ram - ram_start;
1561 efi_add_memory_map(ram_start, ram_size,
1562 EFI_CONVENTIONAL_MEMORY);
1568 * Before DDR size is known, early MMU table have DDR mapped as device memory
1569 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1570 * needs to be set for these mappings.
1571 * If a special case configures DDR with holes in the mapping, the holes need
1572 * to be marked as invalid. This is not implemented in this function.
1574 void update_early_mmu_table(void)
1576 if (!gd->arch.tlb_addr)
1579 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1580 mmu_change_region_attr(
1581 CONFIG_SYS_SDRAM_BASE,
1583 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1584 PTE_BLOCK_OUTER_SHARE |
1588 mmu_change_region_attr(
1589 CONFIG_SYS_SDRAM_BASE,
1590 CONFIG_SYS_DDR_BLOCK1_SIZE,
1591 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1592 PTE_BLOCK_OUTER_SHARE |
1595 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1596 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1597 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1599 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1600 CONFIG_SYS_DDR_BLOCK2_SIZE) {
1601 mmu_change_region_attr(
1602 CONFIG_SYS_DDR_BLOCK2_BASE,
1603 CONFIG_SYS_DDR_BLOCK2_SIZE,
1604 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1605 PTE_BLOCK_OUTER_SHARE |
1608 mmu_change_region_attr(
1609 CONFIG_SYS_DDR_BLOCK3_BASE,
1611 CONFIG_SYS_DDR_BLOCK1_SIZE -
1612 CONFIG_SYS_DDR_BLOCK2_SIZE,
1613 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1614 PTE_BLOCK_OUTER_SHARE |
1620 mmu_change_region_attr(
1621 CONFIG_SYS_DDR_BLOCK2_BASE,
1623 CONFIG_SYS_DDR_BLOCK1_SIZE,
1624 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1625 PTE_BLOCK_OUTER_SHARE |
1632 __weak int dram_init(void)
1635 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1636 defined(CONFIG_SPL_BUILD)
1637 /* This will break-before-make MMU for DDR */
1638 update_early_mmu_table();
1644 #ifdef CONFIG_ARCH_MISC_INIT
1645 __weak int serdes_misc_init(void)
1650 int arch_misc_init(void)