4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1 if !DM_I2C
20 select SYS_I2C_MXC_I2C2 if !DM_I2C
25 select ARMV8_SET_SMPEN
29 select SYS_FSL_HAS_CCI400
34 select SYS_FSL_DDR_VER_50
35 select SYS_FSL_HAS_DDR3
36 select SYS_FSL_HAS_DDR4
37 select SYS_FSL_HAS_SEC
38 select SYS_FSL_SEC_COMPAT_5
41 select ARCH_EARLY_INIT_R
42 select BOARD_EARLY_INIT_F
44 select SYS_FSL_ERRATUM_A008997
45 select SYS_FSL_ERRATUM_A009007
46 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
48 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
49 select SYS_FSL_ERRATUM_A050382
50 select RESV_RAM if GIC_V3_ITS
55 select ARMV8_SET_SMPEN
56 select ARM_ERRATA_855873 if !TFABOOT
63 select SYS_FSL_DDR_VER_50
64 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
65 select SYS_FSL_ERRATUM_A008997
66 select SYS_FSL_ERRATUM_A009007
67 select SYS_FSL_ERRATUM_A009008
68 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
69 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
70 select SYS_FSL_ERRATUM_A009798
71 select SYS_FSL_ERRATUM_A009929
72 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
73 select SYS_FSL_ERRATUM_A010315
74 select SYS_FSL_ERRATUM_A010539
75 select SYS_FSL_HAS_DDR3
76 select SYS_FSL_HAS_DDR4
77 select ARCH_EARLY_INIT_R
78 select BOARD_EARLY_INIT_F
79 select SYS_I2C_MXC if !DM_I2C
80 select SYS_I2C_MXC_I2C1 if !DM_I2C
81 select SYS_I2C_MXC_I2C2 if !DM_I2C
82 select SYS_I2C_MXC_I2C3 if !DM_I2C
83 select SYS_I2C_MXC_I2C4 if !DM_I2C
88 select ARMV8_SET_SMPEN
95 select SYS_FSL_DDR_VER_50
96 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
97 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
98 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
99 select SYS_FSL_ERRATUM_A008997
100 select SYS_FSL_ERRATUM_A009007
101 select SYS_FSL_ERRATUM_A009008
102 select SYS_FSL_ERRATUM_A009798
103 select SYS_FSL_ERRATUM_A009801
104 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
105 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
106 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
107 select SYS_FSL_ERRATUM_A010539
108 select SYS_FSL_HAS_DDR4
109 select SYS_FSL_SRDS_2
110 select ARCH_EARLY_INIT_R
111 select BOARD_EARLY_INIT_F
112 select SYS_I2C_MXC if !DM_I2C
113 select SYS_I2C_MXC_I2C1 if !DM_I2C
114 select SYS_I2C_MXC_I2C2 if !DM_I2C
115 select SYS_I2C_MXC_I2C3 if !DM_I2C
116 select SYS_I2C_MXC_I2C4 if !DM_I2C
122 select ARMV8_SET_SMPEN
123 select ARM_ERRATA_855873 if !TFABOOT
124 select FSL_LAYERSCAPE
126 select SYS_FSL_SRDS_1
127 select SYS_HAS_SERDES
129 select SYS_FSL_DDR_LE
130 select SYS_FSL_DDR_VER_50
133 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
134 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
135 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
136 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
137 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
138 select SYS_FSL_ERRATUM_A009007
139 select SYS_FSL_HAS_CCI400
140 select SYS_FSL_HAS_DDR4
141 select SYS_FSL_HAS_RGMII
142 select SYS_FSL_HAS_SEC
143 select SYS_FSL_SEC_COMPAT_5
144 select SYS_FSL_SEC_LE
145 select SYS_FSL_SRDS_1
146 select SYS_FSL_SRDS_2
149 select FSL_TZPC_BP147
150 select ARCH_EARLY_INIT_R
151 select BOARD_EARLY_INIT_F
153 select SYS_I2C_MXC_I2C1 if !TFABOOT
154 select SYS_I2C_MXC_I2C2 if !TFABOOT
155 select SYS_I2C_MXC_I2C3 if !TFABOOT
156 select SYS_I2C_MXC_I2C4 if !TFABOOT
157 select RESV_RAM if GIC_V3_ITS
163 select ARMV8_SET_SMPEN
164 select ARM_ERRATA_826974
165 select ARM_ERRATA_828024
166 select ARM_ERRATA_829520
167 select ARM_ERRATA_833471
168 select FSL_LAYERSCAPE
170 select SYS_FSL_SRDS_1
171 select SYS_HAS_SERDES
173 select SYS_FSL_DDR_LE
174 select SYS_FSL_DDR_VER_50
175 select SYS_FSL_HAS_CCN504
176 select SYS_FSL_HAS_DP_DDR
177 select SYS_FSL_HAS_SEC
178 select SYS_FSL_HAS_DDR4
179 select SYS_FSL_SEC_COMPAT_5
180 select SYS_FSL_SEC_LE
181 select SYS_FSL_SRDS_2
185 select FSL_TZPC_BP147
186 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
187 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
188 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
189 select SYS_FSL_ERRATUM_A008585
190 select SYS_FSL_ERRATUM_A008997
191 select SYS_FSL_ERRATUM_A009007
192 select SYS_FSL_ERRATUM_A009008
193 select SYS_FSL_ERRATUM_A009635
194 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
195 select SYS_FSL_ERRATUM_A009798
196 select SYS_FSL_ERRATUM_A009801
197 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
198 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
199 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
200 select SYS_FSL_ERRATUM_A009203
201 select ARCH_EARLY_INIT_R
202 select BOARD_EARLY_INIT_F
204 select SYS_I2C_MXC_I2C1 if !TFABOOT
205 select SYS_I2C_MXC_I2C2 if !TFABOOT
206 select SYS_I2C_MXC_I2C3 if !TFABOOT
207 select SYS_I2C_MXC_I2C4 if !TFABOOT
208 select RESV_RAM if GIC_V3_ITS
209 imply DISTRO_DEFAULTS
214 select ARMV8_SET_SMPEN
217 select SYS_HAS_SERDES
218 select SYS_FSL_SRDS_1
219 select SYS_FSL_SRDS_2
220 select SYS_NXP_SRDS_3
222 select SYS_FSL_DDR_LE
223 select SYS_FSL_DDR_VER_50
226 select SYS_FSL_ERRATUM_A050106
227 select SYS_FSL_HAS_RGMII
228 select SYS_FSL_HAS_SEC
229 select SYS_FSL_HAS_CCN508
230 select SYS_FSL_HAS_DDR4
231 select SYS_FSL_SEC_COMPAT_5
232 select SYS_FSL_SEC_LE
233 select ARCH_EARLY_INIT_R
234 select BOARD_EARLY_INIT_F
236 select RESV_RAM if GIC_V3_ITS
237 imply DISTRO_DEFAULTS
244 select SYS_FSL_HAS_CCI400
245 select SYS_FSL_HAS_SEC
246 select SYS_FSL_SEC_COMPAT_5
247 select SYS_FSL_SEC_BE
250 select ARCH_MISC_INIT
256 menu "Layerscape architecture"
257 depends on FSL_LSCH2 || FSL_LSCH3
259 config FSL_LAYERSCAPE
262 config HAS_FEATURE_GIC64K_ALIGN
264 default y if ARCH_LS1043A
266 config HAS_FEATURE_ENHANCED_MSI
268 default y if ARCH_LS1043A
270 menu "Layerscape PPA"
272 bool "FSL Layerscape PPA firmware support"
273 depends on !ARMV8_PSCI
274 select ARMV8_SEC_FIRMWARE_SUPPORT
275 select SEC_FIRMWARE_ARMV8_PSCI
276 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
278 The FSL Primary Protected Application (PPA) is a software component
279 which is loaded during boot stage, and then remains resident in RAM
280 and runs in the TrustZone after boot.
283 config SPL_FSL_LS_PPA
284 bool "FSL Layerscape PPA firmware support for SPL build"
285 depends on !ARMV8_PSCI
286 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
287 select SEC_FIRMWARE_ARMV8_PSCI
288 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
290 The FSL Primary Protected Application (PPA) is a software component
291 which is loaded during boot stage, and then remains resident in RAM
292 and runs in the TrustZone after boot. This is to load PPA during SPL
293 stage instead of the RAM version of U-Boot. Once PPA is initialized,
294 the rest of U-Boot (including RAM version) runs at EL2.
296 prompt "FSL Layerscape PPA firmware loading-media select"
297 depends on FSL_LS_PPA
298 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
299 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
300 default SYS_LS_PPA_FW_IN_XIP
302 config SYS_LS_PPA_FW_IN_XIP
305 Say Y here if the PPA firmware locate at XIP flash, such
306 as NOR or QSPI flash.
308 config SYS_LS_PPA_FW_IN_MMC
309 bool "eMMC or SD Card"
311 Say Y here if the PPA firmware locate at eMMC/SD card.
313 config SYS_LS_PPA_FW_IN_NAND
316 Say Y here if the PPA firmware locate at NAND flash.
320 config LS_PPA_ESBC_HDR_SIZE
321 hex "Length of PPA ESBC header"
322 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
325 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
326 NAND to memory to validate PPA image.
330 config SYS_FSL_ERRATUM_A008997
331 bool "Workaround for USB PHY erratum A008997"
333 config SYS_FSL_ERRATUM_A009007
336 Workaround for USB PHY erratum A009007
338 config SYS_FSL_ERRATUM_A009008
339 bool "Workaround for USB PHY erratum A009008"
341 config SYS_FSL_ERRATUM_A009798
342 bool "Workaround for USB PHY erratum A009798"
344 config SYS_FSL_ERRATUM_A050106
345 bool "Workaround for USB PHY erratum A050106"
347 USB3.0 Receiver needs to enable fixed equalization
348 for each of PHY instances in an SOC. This is similar
349 to erratum A-009007, but this one is for LX2160A,
350 and the register value is different.
352 config SYS_FSL_ERRATUM_A010315
353 bool "Workaround for PCIe erratum A010315"
355 config SYS_FSL_ERRATUM_A010539
356 bool "Workaround for PIN MUX erratum A010539"
359 int "Maximum number of CPUs permitted for Layerscape"
360 default 2 if ARCH_LS1028A
361 default 4 if ARCH_LS1043A
362 default 4 if ARCH_LS1046A
363 default 16 if ARCH_LS2080A
364 default 8 if ARCH_LS1088A
365 default 16 if ARCH_LX2160A
368 Set this number to the maximum number of possible CPUs in the SoC.
369 SoCs may have multiple clusters with each cluster may have multiple
370 ports. If some ports are reserved but higher ports are used for
371 cores, count the reserved ports. This will allocate enough memory
372 in spin table to properly handle all cores.
375 bool "Fan controller"
377 Enable the EMC2305 fan controller for configuration of fan
383 Enable Freescale Secure Boot feature
386 bool "Init the QSPI AHB bus"
388 The default setting for QSPI AHB bus just support 3bytes addressing.
389 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
390 bus for those flashes to support the full QSPI flash size.
392 config FSPI_AHB_EN_4BYTE
393 bool "Enable 4-byte Fast Read command for AHB mode"
396 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
397 But some FlexSPI flash sizes are up to 64MBytes.
398 This flag enables fast read command for AHB mode and modifies required
399 LUT to support full FlexSPI flash.
401 config SYS_CCI400_OFFSET
402 hex "Offset for CCI400 base"
403 depends on SYS_FSL_HAS_CCI400
404 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
405 default 0x180000 if FSL_LSCH2
407 Offset for CCI400 base
408 CCI400 base addr = CCSRBAR + CCI400_OFFSET
410 config SYS_FSL_IFC_BANK_COUNT
411 int "Maximum banks of Integrated flash controller"
412 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
413 default 4 if ARCH_LS1043A
414 default 4 if ARCH_LS1046A
415 default 8 if ARCH_LS2080A || ARCH_LS1088A
417 config SYS_FSL_HAS_CCI400
420 config SYS_FSL_HAS_CCN504
423 config SYS_FSL_HAS_CCN508
426 config SYS_FSL_HAS_DP_DDR
429 config SYS_FSL_SRDS_1
432 config SYS_FSL_SRDS_2
435 config SYS_NXP_SRDS_3
438 config SYS_HAS_SERDES
450 config FSL_TZPC_BP147
454 menu "Layerscape clock tree configuration"
455 depends on FSL_LSCH2 || FSL_LSCH3
458 bool "Enable clock tree initialization"
461 config CLUSTER_CLK_FREQ
462 int "Reference clock of core cluster"
463 depends on ARCH_LS1012A
466 This number is the reference clock frequency of core PLL.
467 For most platforms, the core PLL and Platform PLL have the same
468 reference clock, but for some platforms, LS1012A for instance,
469 they are provided sepatately.
471 config SYS_FSL_PCLK_DIV
472 int "Platform clock divider"
473 default 1 if ARCH_LS1028A
474 default 1 if ARCH_LS1043A
475 default 1 if ARCH_LS1046A
476 default 1 if ARCH_LS1088A
479 This is the divider that is used to derive Platform clock from
480 Platform PLL, in another word:
481 Platform_clk = Platform_PLL_freq / this_divider
483 config SYS_FSL_DSPI_CLK_DIV
484 int "DSPI clock divider"
485 default 1 if ARCH_LS1043A
488 This is the divider that is used to derive DSPI clock from Platform
489 clock, in another word DSPI_clk = Platform_clk / this_divider.
491 config SYS_FSL_DUART_CLK_DIV
492 int "DUART clock divider"
493 default 1 if ARCH_LS1043A
494 default 4 if ARCH_LX2160A
497 This is the divider that is used to derive DUART clock from Platform
498 clock, in another word DUART_clk = Platform_clk / this_divider.
500 config SYS_FSL_I2C_CLK_DIV
501 int "I2C clock divider"
502 default 1 if ARCH_LS1043A
503 default 4 if ARCH_LS1012A
504 default 4 if ARCH_LS1028A
505 default 8 if ARCH_LX2160A
506 default 8 if ARCH_LS1088A
509 This is the divider that is used to derive I2C clock from Platform
510 clock, in another word I2C_clk = Platform_clk / this_divider.
512 config SYS_FSL_IFC_CLK_DIV
513 int "IFC clock divider"
514 default 1 if ARCH_LS1043A
515 default 4 if ARCH_LS1012A
516 default 4 if ARCH_LS1028A
517 default 8 if ARCH_LX2160A
518 default 8 if ARCH_LS1088A
521 This is the divider that is used to derive IFC clock from Platform
522 clock, in another word IFC_clk = Platform_clk / this_divider.
524 config SYS_FSL_LPUART_CLK_DIV
525 int "LPUART clock divider"
526 default 1 if ARCH_LS1043A
529 This is the divider that is used to derive LPUART clock from Platform
530 clock, in another word LPUART_clk = Platform_clk / this_divider.
532 config SYS_FSL_SDHC_CLK_DIV
533 int "SDHC clock divider"
534 default 1 if ARCH_LS1043A
535 default 1 if ARCH_LS1012A
538 This is the divider that is used to derive SDHC clock from Platform
539 clock, in another word SDHC_clk = Platform_clk / this_divider.
541 config SYS_FSL_QMAN_CLK_DIV
542 int "QMAN clock divider"
543 default 1 if ARCH_LS1043A
546 This is the divider that is used to derive QMAN clock from Platform
547 clock, in another word QMAN_clk = Platform_clk / this_divider.
553 Reserve memory from the top, tracked by gd->arch.resv_ram. This
554 reserved RAM can be used by special driver that resides in memory
555 after U-Boot exits. It's up to implementation to allocate and allow
556 access to this reserved memory. For example, the reserved RAM can
557 be at the high end of physical memory. The reserve RAM may be
558 excluded from memory bank(s) passed to OS, or marked as reserved.
563 Ethernet controller 1, this is connected to
564 MAC17 for LX2160A or to MAC3 for other SoCs
565 Provides DPAA2 capabilities
570 Ethernet controller 2, this is connected to
571 MAC18 for LX2160A or to MAC4 for other SoCs
572 Provides DPAA2 capabilities
574 config SYS_FSL_ERRATUM_A008336
577 config SYS_FSL_ERRATUM_A008514
580 config SYS_FSL_ERRATUM_A008585
583 config SYS_FSL_ERRATUM_A008850
586 config SYS_FSL_ERRATUM_A009203
589 config SYS_FSL_ERRATUM_A009635
592 config SYS_FSL_ERRATUM_A009660
595 config SYS_FSL_ERRATUM_A009929
598 config SYS_FSL_ERRATUM_A050382
601 config SYS_FSL_HAS_RGMII
603 depends on SYS_FSL_EC1 || SYS_FSL_EC2
606 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
608 config HAS_FSL_XHCI_USB
610 default y if ARCH_LS1043A || ARCH_LS1046A
612 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
613 pins, select it when the pins are assigned to USB.