7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F
32 select ARMV8_SET_SMPEN
36 select SYS_FSL_DDR_VER_50
37 select SYS_FSL_ERRATUM_A008336
38 select SYS_FSL_ERRATUM_A008511
39 select SYS_FSL_ERRATUM_A008850
40 select SYS_FSL_ERRATUM_A009801
41 select SYS_FSL_ERRATUM_A009803
42 select SYS_FSL_ERRATUM_A009942
43 select SYS_FSL_ERRATUM_A010165
44 select SYS_FSL_ERRATUM_A010539
45 select SYS_FSL_HAS_DDR4
47 select ARCH_EARLY_INIT_R
48 select BOARD_EARLY_INIT_F
52 select ARMV8_SET_SMPEN
53 select ARM_ERRATA_826974
54 select ARM_ERRATA_828024
55 select ARM_ERRATA_829520
56 select ARM_ERRATA_833471
60 select SYS_FSL_DDR_VER_50
61 select SYS_FSL_HAS_DP_DDR
62 select SYS_FSL_HAS_SEC
63 select SYS_FSL_HAS_DDR4
64 select SYS_FSL_SEC_COMPAT_5
69 select SYS_FSL_ERRATUM_A008336
70 select SYS_FSL_ERRATUM_A008511
71 select SYS_FSL_ERRATUM_A008514
72 select SYS_FSL_ERRATUM_A008585
73 select SYS_FSL_ERRATUM_A009635
74 select SYS_FSL_ERRATUM_A009663
75 select SYS_FSL_ERRATUM_A009801
76 select SYS_FSL_ERRATUM_A009803
77 select SYS_FSL_ERRATUM_A009942
78 select SYS_FSL_ERRATUM_A010165
79 select SYS_FSL_ERRATUM_A009203
80 select ARCH_EARLY_INIT_R
81 select BOARD_EARLY_INIT_F
85 select SYS_FSL_HAS_SEC
86 select SYS_FSL_SEC_COMPAT_5
97 bool "Management Complex network"
98 depends on ARCH_LS2080A
102 Enable Management Complex (MC) network
104 menu "Layerscape architecture"
105 depends on FSL_LSCH2 || FSL_LSCH3
107 config FSL_PCIE_COMPAT
108 string "PCIe compatible of Kernel DT"
109 depends on PCIE_LAYERSCAPE
110 default "fsl,ls1012a-pcie" if ARCH_LS1012A
111 default "fsl,ls1043a-pcie" if ARCH_LS1043A
112 default "fsl,ls1046a-pcie" if ARCH_LS1046A
113 default "fsl,ls2080a-pcie" if ARCH_LS2080A
115 This compatible is used to find pci controller node in Kernel DT
118 config HAS_FEATURE_GIC64K_ALIGN
120 default y if ARCH_LS1043A
122 config HAS_FEATURE_ENHANCED_MSI
124 default y if ARCH_LS1043A
126 menu "Layerscape PPA"
128 bool "FSL Layerscape PPA firmware support"
129 depends on !ARMV8_PSCI
130 select ARMV8_SEC_FIRMWARE_SUPPORT
131 select SEC_FIRMWARE_ARMV8_PSCI
132 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
134 The FSL Primary Protected Application (PPA) is a software component
135 which is loaded during boot stage, and then remains resident in RAM
136 and runs in the TrustZone after boot.
139 config SPL_FSL_LS_PPA
140 bool "FSL Layerscape PPA firmware support for SPL build"
141 depends on !ARMV8_PSCI
142 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
143 select SEC_FIRMWARE_ARMV8_PSCI
144 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
146 The FSL Primary Protected Application (PPA) is a software component
147 which is loaded during boot stage, and then remains resident in RAM
148 and runs in the TrustZone after boot. This is to load PPA during SPL
149 stage instead of the RAM version of U-Boot. Once PPA is initialized,
150 the rest of U-Boot (including RAM version) runs at EL2.
152 prompt "FSL Layerscape PPA firmware loading-media select"
153 depends on FSL_LS_PPA
154 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
155 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
156 default SYS_LS_PPA_FW_IN_XIP
158 config SYS_LS_PPA_FW_IN_XIP
161 Say Y here if the PPA firmware locate at XIP flash, such
162 as NOR or QSPI flash.
164 config SYS_LS_PPA_FW_IN_MMC
165 bool "eMMC or SD Card"
167 Say Y here if the PPA firmware locate at eMMC/SD card.
169 config SYS_LS_PPA_FW_IN_NAND
172 Say Y here if the PPA firmware locate at NAND flash.
176 config SYS_LS_PPA_FW_ADDR
177 hex "Address of PPA firmware loading from"
178 depends on FSL_LS_PPA
179 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
180 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
181 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
182 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
183 default 0x400000 if SYS_LS_PPA_FW_IN_MMC
184 default 0x400000 if SYS_LS_PPA_FW_IN_NAND
187 If the PPA firmware locate at XIP flash, such as NOR or
188 QSPI flash, this address is a directly memory-mapped.
189 If it is in a serial accessed flash, such as NAND and SD
190 card, it is a byte offset.
192 config SYS_LS_PPA_ESBC_ADDR
193 hex "hdr address of PPA firmware loading from"
194 depends on FSL_LS_PPA && CHAIN_OF_TRUST
195 default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
196 default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
197 default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
198 default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
199 default 0x700000 if SYS_LS_PPA_FW_IN_MMC
200 default 0x700000 if SYS_LS_PPA_FW_IN_NAND
202 If the PPA header firmware locate at XIP flash, such as NOR or
203 QSPI flash, this address is a directly memory-mapped.
204 If it is in a serial accessed flash, such as NAND and SD
205 card, it is a byte offset.
207 config LS_PPA_ESBC_HDR_SIZE
208 hex "Length of PPA ESBC header"
209 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
212 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
213 NAND to memory to validate PPA image.
217 config SYS_FSL_ERRATUM_A010315
218 bool "Workaround for PCIe erratum A010315"
220 config SYS_FSL_ERRATUM_A010539
221 bool "Workaround for PIN MUX erratum A010539"
224 int "Maximum number of CPUs permitted for Layerscape"
225 default 4 if ARCH_LS1043A
226 default 4 if ARCH_LS1046A
227 default 16 if ARCH_LS2080A
230 Set this number to the maximum number of possible CPUs in the SoC.
231 SoCs may have multiple clusters with each cluster may have multiple
232 ports. If some ports are reserved but higher ports are used for
233 cores, count the reserved ports. This will allocate enough memory
234 in spin table to properly handle all cores.
239 Enable Freescale Secure Boot feature
242 bool "Init the QSPI AHB bus"
244 The default setting for QSPI AHB bus just support 3bytes addressing.
245 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
246 bus for those flashes to support the full QSPI flash size.
248 config SYS_FSL_IFC_BANK_COUNT
249 int "Maximum banks of Integrated flash controller"
250 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
251 default 4 if ARCH_LS1043A
252 default 4 if ARCH_LS1046A
253 default 8 if ARCH_LS2080A
255 config SYS_FSL_HAS_DP_DDR
258 config SYS_FSL_SRDS_1
261 config SYS_FSL_SRDS_2
264 config SYS_HAS_SERDES
275 menu "Layerscape clock tree configuration"
276 depends on FSL_LSCH2 || FSL_LSCH3
279 bool "Enable clock tree initialization"
282 config CLUSTER_CLK_FREQ
283 int "Reference clock of core cluster"
284 depends on ARCH_LS1012A
287 This number is the reference clock frequency of core PLL.
288 For most platforms, the core PLL and Platform PLL have the same
289 reference clock, but for some platforms, LS1012A for instance,
290 they are provided sepatately.
292 config SYS_FSL_PCLK_DIV
293 int "Platform clock divider"
294 default 1 if ARCH_LS1043A
295 default 1 if ARCH_LS1046A
298 This is the divider that is used to derive Platform clock from
299 Platform PLL, in another word:
300 Platform_clk = Platform_PLL_freq / this_divider
302 config SYS_FSL_DSPI_CLK_DIV
303 int "DSPI clock divider"
304 default 1 if ARCH_LS1043A
307 This is the divider that is used to derive DSPI clock from Platform
308 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
310 config SYS_FSL_DUART_CLK_DIV
311 int "DUART clock divider"
312 default 1 if ARCH_LS1043A
315 This is the divider that is used to derive DUART clock from Platform
316 clock, in another word DUART_clk = Platform_clk / this_divider.
318 config SYS_FSL_I2C_CLK_DIV
319 int "I2C clock divider"
320 default 1 if ARCH_LS1043A
323 This is the divider that is used to derive I2C clock from Platform
324 clock, in another word I2C_clk = Platform_clk / this_divider.
326 config SYS_FSL_IFC_CLK_DIV
327 int "IFC clock divider"
328 default 1 if ARCH_LS1043A
331 This is the divider that is used to derive IFC clock from Platform
332 clock, in another word IFC_clk = Platform_clk / this_divider.
334 config SYS_FSL_LPUART_CLK_DIV
335 int "LPUART clock divider"
336 default 1 if ARCH_LS1043A
339 This is the divider that is used to derive LPUART clock from Platform
340 clock, in another word LPUART_clk = Platform_clk / this_divider.
342 config SYS_FSL_SDHC_CLK_DIV
343 int "SDHC clock divider"
344 default 1 if ARCH_LS1043A
345 default 1 if ARCH_LS1012A
348 This is the divider that is used to derive SDHC clock from Platform
349 clock, in another word SDHC_clk = Platform_clk / this_divider.
355 Reserve memory from the top, tracked by gd->arch.resv_ram. This
356 reserved RAM can be used by special driver that resides in memory
357 after U-Boot exits. It's up to implementation to allocate and allow
358 access to this reserved memory. For example, the reserved RAM can
359 be at the high end of physical memory. The reserve RAM may be
360 excluded from memory bank(s) passed to OS, or marked as reserved.
362 config SYS_FSL_ERRATUM_A008336
365 config SYS_FSL_ERRATUM_A008514
368 config SYS_FSL_ERRATUM_A008585
371 config SYS_FSL_ERRATUM_A008850
374 config SYS_FSL_ERRATUM_A009203
377 config SYS_FSL_ERRATUM_A009635
380 config SYS_FSL_ERRATUM_A009660
383 config SYS_FSL_ERRATUM_A009929
386 config SYS_MC_RSV_MEM_ALIGN
387 hex "Management Complex reserved memory alignment"
391 Reserved memory needs to be aligned for MC to use. Default value