4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1 if !DM_I2C
20 select SYS_I2C_MXC_I2C2 if !DM_I2C
25 select ARMV8_SET_SMPEN
29 select SYS_FSL_HAS_CCI400
34 select SYS_FSL_DDR_VER_50
35 select SYS_FSL_HAS_DDR3
36 select SYS_FSL_HAS_DDR4
37 select SYS_FSL_HAS_SEC
38 select SYS_FSL_SEC_COMPAT_5
41 select ARCH_EARLY_INIT_R
42 select BOARD_EARLY_INIT_F
44 select SYS_FSL_ERRATUM_A008997
45 select SYS_FSL_ERRATUM_A009007
46 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
48 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
49 select SYS_FSL_ERRATUM_A050382
50 select SYS_FSL_ERRATUM_A011334
51 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
52 select RESV_RAM if GIC_V3_ITS
57 select ARMV8_SET_SMPEN
58 select ARM_ERRATA_855873 if !TFABOOT
61 select HAS_FSL_XHCI_USB if USB_HOST
66 select SYS_FSL_DDR_VER_50
67 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
68 select SYS_FSL_ERRATUM_A008997
69 select SYS_FSL_ERRATUM_A009007
70 select SYS_FSL_ERRATUM_A009008
71 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
72 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
73 select SYS_FSL_ERRATUM_A009798
74 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
75 select SYS_FSL_ERRATUM_A010315
76 select SYS_FSL_ERRATUM_A010539
77 select SYS_FSL_HAS_DDR3
78 select SYS_FSL_HAS_DDR4
79 select ARCH_EARLY_INIT_R
80 select BOARD_EARLY_INIT_F
82 select SYS_I2C_MXC_I2C1 if !DM_I2C
83 select SYS_I2C_MXC_I2C2 if !DM_I2C
84 select SYS_I2C_MXC_I2C3 if !DM_I2C
85 select SYS_I2C_MXC_I2C4 if !DM_I2C
91 select ARMV8_SET_SMPEN
94 select HAS_FSL_XHCI_USB if USB_HOST
99 select SYS_FSL_DDR_VER_50
100 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
101 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
102 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
103 select SYS_FSL_ERRATUM_A008997
104 select SYS_FSL_ERRATUM_A009007
105 select SYS_FSL_ERRATUM_A009008
106 select SYS_FSL_ERRATUM_A009798
107 select SYS_FSL_ERRATUM_A009801
108 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
109 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
110 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
111 select SYS_FSL_ERRATUM_A010539
112 select SYS_FSL_HAS_DDR4
113 select SYS_FSL_SRDS_2
114 select ARCH_EARLY_INIT_R
115 select BOARD_EARLY_INIT_F
117 select SYS_I2C_MXC_I2C1 if !DM_I2C
118 select SYS_I2C_MXC_I2C2 if !DM_I2C
119 select SYS_I2C_MXC_I2C3 if !DM_I2C
120 select SYS_I2C_MXC_I2C4 if !DM_I2C
127 select ARMV8_SET_SMPEN
128 select ARM_ERRATA_855873 if !TFABOOT
129 select FSL_LAYERSCAPE
131 select SYS_FSL_SRDS_1
132 select SYS_HAS_SERDES
134 select SYS_FSL_DDR_LE
135 select SYS_FSL_DDR_VER_50
138 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
139 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
140 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
141 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
142 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
143 select SYS_FSL_ERRATUM_A009007
144 select SYS_FSL_HAS_CCI400
145 select SYS_FSL_HAS_DDR4
146 select SYS_FSL_HAS_RGMII
147 select SYS_FSL_HAS_SEC
148 select SYS_FSL_SEC_COMPAT_5
149 select SYS_FSL_SEC_LE
150 select SYS_FSL_SRDS_1
151 select SYS_FSL_SRDS_2
154 select FSL_TZPC_BP147
155 select ARCH_EARLY_INIT_R
156 select BOARD_EARLY_INIT_F
158 select SYS_I2C_MXC_I2C1 if !TFABOOT
159 select SYS_I2C_MXC_I2C2 if !TFABOOT
160 select SYS_I2C_MXC_I2C3 if !TFABOOT
161 select SYS_I2C_MXC_I2C4 if !TFABOOT
162 select RESV_RAM if GIC_V3_ITS
169 select ARMV8_SET_SMPEN
170 select ARM_ERRATA_826974
171 select ARM_ERRATA_828024
172 select ARM_ERRATA_829520
173 select ARM_ERRATA_833471
174 select FSL_LAYERSCAPE
176 select SYS_FSL_SRDS_1
177 select SYS_HAS_SERDES
179 select SYS_FSL_DDR_LE
180 select SYS_FSL_DDR_VER_50
181 select SYS_FSL_HAS_CCN504
182 select SYS_FSL_HAS_DP_DDR
183 select SYS_FSL_HAS_SEC
184 select SYS_FSL_HAS_DDR4
185 select SYS_FSL_SEC_COMPAT_5
186 select SYS_FSL_SEC_LE
187 select SYS_FSL_SRDS_2
191 select FSL_TZPC_BP147
192 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
193 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
194 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
195 select SYS_FSL_ERRATUM_A008585
196 select SYS_FSL_ERRATUM_A008997
197 select SYS_FSL_ERRATUM_A009007
198 select SYS_FSL_ERRATUM_A009008
199 select SYS_FSL_ERRATUM_A009635
200 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
201 select SYS_FSL_ERRATUM_A009798
202 select SYS_FSL_ERRATUM_A009801
203 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
204 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
205 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
206 select SYS_FSL_ERRATUM_A009203
207 select ARCH_EARLY_INIT_R
208 select BOARD_EARLY_INIT_F
210 select SYS_I2C_MXC_I2C1 if !TFABOOT
211 select SYS_I2C_MXC_I2C2 if !TFABOOT
212 select SYS_I2C_MXC_I2C3 if !TFABOOT
213 select SYS_I2C_MXC_I2C4 if !TFABOOT
214 select RESV_RAM if GIC_V3_ITS
215 imply DISTRO_DEFAULTS
221 select ARMV8_SET_SMPEN
224 select SYS_HAS_SERDES
225 select SYS_FSL_SRDS_1
226 select SYS_FSL_SRDS_2
228 select SYS_FSL_DDR_LE
229 select SYS_FSL_DDR_VER_50
232 select SYS_FSL_ERRATUM_A050204
233 select SYS_FSL_ERRATUM_A011334
234 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
235 select SYS_FSL_HAS_RGMII
236 select SYS_FSL_HAS_SEC
237 select SYS_FSL_HAS_CCN508
238 select SYS_FSL_HAS_DDR4
239 select SYS_FSL_SEC_COMPAT_5
240 select SYS_FSL_SEC_LE
241 select ARCH_EARLY_INIT_R
242 select BOARD_EARLY_INIT_F
244 select RESV_RAM if GIC_V3_ITS
245 imply DISTRO_DEFAULTS
252 select ARMV8_SET_SMPEN
254 select HAS_FSL_XHCI_USB if USB_HOST
256 select SYS_HAS_SERDES
257 select SYS_FSL_SRDS_1
258 select SYS_FSL_SRDS_2
259 select SYS_NXP_SRDS_3
261 select SYS_FSL_DDR_LE
262 select SYS_FSL_DDR_VER_50
265 select SYS_FSL_ERRATUM_A050204
266 select SYS_FSL_ERRATUM_A011334
267 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
268 select SYS_FSL_HAS_RGMII
269 select SYS_FSL_HAS_SEC
270 select SYS_FSL_HAS_CCN508
271 select SYS_FSL_HAS_DDR4
272 select SYS_FSL_SEC_COMPAT_5
273 select SYS_FSL_SEC_LE
274 select ARCH_EARLY_INIT_R
275 select BOARD_EARLY_INIT_F
277 select RESV_RAM if GIC_V3_ITS
278 imply DISTRO_DEFAULTS
286 select SYS_FSL_HAS_CCI400
287 select SYS_FSL_HAS_SEC
288 select SYS_FSL_SEC_COMPAT_5
289 select SYS_FSL_SEC_BE
292 select ARCH_MISC_INIT
298 menu "Layerscape architecture"
299 depends on FSL_LSCH2 || FSL_LSCH3
301 config FSL_LAYERSCAPE
304 config HAS_FEATURE_GIC64K_ALIGN
306 default y if ARCH_LS1043A
308 config HAS_FEATURE_ENHANCED_MSI
310 default y if ARCH_LS1043A
312 menu "Layerscape PPA"
314 bool "FSL Layerscape PPA firmware support"
315 depends on !ARMV8_PSCI
316 select ARMV8_SEC_FIRMWARE_SUPPORT
317 select SEC_FIRMWARE_ARMV8_PSCI
318 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
320 The FSL Primary Protected Application (PPA) is a software component
321 which is loaded during boot stage, and then remains resident in RAM
322 and runs in the TrustZone after boot.
325 config SPL_FSL_LS_PPA
326 bool "FSL Layerscape PPA firmware support for SPL build"
327 depends on !ARMV8_PSCI
328 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
329 select SEC_FIRMWARE_ARMV8_PSCI
330 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
332 The FSL Primary Protected Application (PPA) is a software component
333 which is loaded during boot stage, and then remains resident in RAM
334 and runs in the TrustZone after boot. This is to load PPA during SPL
335 stage instead of the RAM version of U-Boot. Once PPA is initialized,
336 the rest of U-Boot (including RAM version) runs at EL2.
338 prompt "FSL Layerscape PPA firmware loading-media select"
339 depends on FSL_LS_PPA
340 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
341 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
342 default SYS_LS_PPA_FW_IN_XIP
344 config SYS_LS_PPA_FW_IN_XIP
347 Say Y here if the PPA firmware locate at XIP flash, such
348 as NOR or QSPI flash.
350 config SYS_LS_PPA_FW_IN_MMC
351 bool "eMMC or SD Card"
353 Say Y here if the PPA firmware locate at eMMC/SD card.
355 config SYS_LS_PPA_FW_IN_NAND
358 Say Y here if the PPA firmware locate at NAND flash.
362 config LS_PPA_ESBC_HDR_SIZE
363 hex "Length of PPA ESBC header"
364 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
367 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
368 NAND to memory to validate PPA image.
372 config SYS_FSL_ERRATUM_A008997
373 bool "Workaround for USB PHY erratum A008997"
375 config SYS_FSL_ERRATUM_A009007
378 Workaround for USB PHY erratum A009007
380 config SYS_FSL_ERRATUM_A009008
381 bool "Workaround for USB PHY erratum A009008"
383 config SYS_FSL_ERRATUM_A009798
384 bool "Workaround for USB PHY erratum A009798"
386 config SYS_FSL_ERRATUM_A050204
387 bool "Workaround for USB PHY erratum A050204"
389 USB3.0 Receiver needs to enable fixed equalization
390 for each of PHY instances in an SOC. This is similar
391 to erratum A-009007, but this one is for LX2160A and LX2162A,
392 and the register value is different.
394 config SYS_FSL_ERRATUM_A010315
395 bool "Workaround for PCIe erratum A010315"
397 config SYS_FSL_ERRATUM_A010539
398 bool "Workaround for PIN MUX erratum A010539"
401 int "Maximum number of CPUs permitted for Layerscape"
402 default 2 if ARCH_LS1028A
403 default 4 if ARCH_LS1043A
404 default 4 if ARCH_LS1046A
405 default 16 if ARCH_LS2080A
406 default 8 if ARCH_LS1088A
407 default 16 if ARCH_LX2160A
408 default 16 if ARCH_LX2162A
411 Set this number to the maximum number of possible CPUs in the SoC.
412 SoCs may have multiple clusters with each cluster may have multiple
413 ports. If some ports are reserved but higher ports are used for
414 cores, count the reserved ports. This will allocate enough memory
415 in spin table to properly handle all cores.
418 bool "Fan controller"
420 Enable the EMC2305 fan controller for configuration of fan
426 Enable Freescale Secure Boot feature
429 bool "Init the QSPI AHB bus"
431 The default setting for QSPI AHB bus just support 3bytes addressing.
432 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
433 bus for those flashes to support the full QSPI flash size.
435 config FSPI_AHB_EN_4BYTE
436 bool "Enable 4-byte Fast Read command for AHB mode"
439 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
440 But some FlexSPI flash sizes are up to 64MBytes.
441 This flag enables fast read command for AHB mode and modifies required
442 LUT to support full FlexSPI flash.
444 config SYS_CCI400_OFFSET
445 hex "Offset for CCI400 base"
446 depends on SYS_FSL_HAS_CCI400
447 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
448 default 0x180000 if FSL_LSCH2
450 Offset for CCI400 base
451 CCI400 base addr = CCSRBAR + CCI400_OFFSET
453 config SYS_FSL_IFC_BANK_COUNT
454 int "Maximum banks of Integrated flash controller"
455 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
456 default 4 if ARCH_LS1043A
457 default 4 if ARCH_LS1046A
458 default 8 if ARCH_LS2080A || ARCH_LS1088A
460 config SYS_FSL_HAS_CCI400
463 config SYS_FSL_HAS_CCN504
466 config SYS_FSL_HAS_CCN508
469 config SYS_FSL_HAS_DP_DDR
472 config SYS_FSL_SRDS_1
475 config SYS_FSL_SRDS_2
478 config SYS_NXP_SRDS_3
481 config SYS_HAS_SERDES
493 config FSL_TZPC_BP147
497 menu "Layerscape clock tree configuration"
498 depends on FSL_LSCH2 || FSL_LSCH3
501 bool "Enable clock tree initialization"
504 config CLUSTER_CLK_FREQ
505 int "Reference clock of core cluster"
506 depends on ARCH_LS1012A
509 This number is the reference clock frequency of core PLL.
510 For most platforms, the core PLL and Platform PLL have the same
511 reference clock, but for some platforms, LS1012A for instance,
512 they are provided sepatately.
514 config SYS_FSL_PCLK_DIV
515 int "Platform clock divider"
516 default 1 if ARCH_LS1028A
517 default 1 if ARCH_LS1043A
518 default 1 if ARCH_LS1046A
519 default 1 if ARCH_LS1088A
522 This is the divider that is used to derive Platform clock from
523 Platform PLL, in another word:
524 Platform_clk = Platform_PLL_freq / this_divider
526 config SYS_FSL_DSPI_CLK_DIV
527 int "DSPI clock divider"
528 default 1 if ARCH_LS1043A
531 This is the divider that is used to derive DSPI clock from Platform
532 clock, in another word DSPI_clk = Platform_clk / this_divider.
534 config SYS_FSL_DUART_CLK_DIV
535 int "DUART clock divider"
536 default 1 if ARCH_LS1043A
537 default 4 if ARCH_LX2160A
538 default 4 if ARCH_LX2162A
541 This is the divider that is used to derive DUART clock from Platform
542 clock, in another word DUART_clk = Platform_clk / this_divider.
544 config SYS_FSL_I2C_CLK_DIV
545 int "I2C clock divider"
546 default 1 if ARCH_LS1043A
547 default 4 if ARCH_LS1012A
548 default 4 if ARCH_LS1028A
549 default 8 if ARCH_LX2160A
550 default 8 if ARCH_LX2162A
551 default 8 if ARCH_LS1088A
554 This is the divider that is used to derive I2C clock from Platform
555 clock, in another word I2C_clk = Platform_clk / this_divider.
557 config SYS_FSL_IFC_CLK_DIV
558 int "IFC clock divider"
559 default 1 if ARCH_LS1043A
560 default 4 if ARCH_LS1012A
561 default 4 if ARCH_LS1028A
562 default 8 if ARCH_LX2160A
563 default 8 if ARCH_LX2162A
564 default 8 if ARCH_LS1088A
567 This is the divider that is used to derive IFC clock from Platform
568 clock, in another word IFC_clk = Platform_clk / this_divider.
570 config SYS_FSL_LPUART_CLK_DIV
571 int "LPUART clock divider"
572 default 1 if ARCH_LS1043A
575 This is the divider that is used to derive LPUART clock from Platform
576 clock, in another word LPUART_clk = Platform_clk / this_divider.
578 config SYS_FSL_SDHC_CLK_DIV
579 int "SDHC clock divider"
580 default 1 if ARCH_LS1043A
581 default 1 if ARCH_LS1012A
584 This is the divider that is used to derive SDHC clock from Platform
585 clock, in another word SDHC_clk = Platform_clk / this_divider.
587 config SYS_FSL_QMAN_CLK_DIV
588 int "QMAN clock divider"
589 default 1 if ARCH_LS1043A
592 This is the divider that is used to derive QMAN clock from Platform
593 clock, in another word QMAN_clk = Platform_clk / this_divider.
599 Reserve memory from the top, tracked by gd->arch.resv_ram. This
600 reserved RAM can be used by special driver that resides in memory
601 after U-Boot exits. It's up to implementation to allocate and allow
602 access to this reserved memory. For example, the reserved RAM can
603 be at the high end of physical memory. The reserve RAM may be
604 excluded from memory bank(s) passed to OS, or marked as reserved.
609 Ethernet controller 1, this is connected to
610 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
611 Provides DPAA2 capabilities
616 Ethernet controller 2, this is connected to
617 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
618 Provides DPAA2 capabilities
620 config SYS_FSL_ERRATUM_A008336
623 config SYS_FSL_ERRATUM_A008514
626 config SYS_FSL_ERRATUM_A008585
629 config SYS_FSL_ERRATUM_A008850
632 config SYS_FSL_ERRATUM_A009203
635 config SYS_FSL_ERRATUM_A009635
638 config SYS_FSL_ERRATUM_A009660
641 config SYS_FSL_ERRATUM_A050382
644 config SYS_FSL_HAS_RGMII
646 depends on SYS_FSL_EC1 || SYS_FSL_EC2
649 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
651 config HAS_FSL_XHCI_USB
654 For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
655 pins, select it when the pins are assigned to USB.
657 config SYS_FSL_BOOTROM_BASE
662 config SYS_FSL_BOOTROM_SIZE