4 select ARM_ERRATA_855873 if !TFABOOT
10 select SYS_FSL_ERRATUM_A010315
11 select SYS_FSL_ERRATUM_A009798
12 select SYS_FSL_ERRATUM_A008997
13 select SYS_FSL_ERRATUM_A009007
14 select SYS_FSL_ERRATUM_A009008
15 select ARCH_EARLY_INIT_R
16 select BOARD_EARLY_INIT_F
18 select SYS_I2C_MXC_I2C1
19 select SYS_I2C_MXC_I2C2
24 select ARMV8_SET_SMPEN
25 select ARM_ERRATA_855873 if !TFABOOT
31 select SYS_FSL_DDR_VER_50
32 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
33 select SYS_FSL_ERRATUM_A008997
34 select SYS_FSL_ERRATUM_A009007
35 select SYS_FSL_ERRATUM_A009008
36 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
37 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
38 select SYS_FSL_ERRATUM_A009798
39 select SYS_FSL_ERRATUM_A009929
40 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
41 select SYS_FSL_ERRATUM_A010315
42 select SYS_FSL_ERRATUM_A010539
43 select SYS_FSL_HAS_DDR3
44 select SYS_FSL_HAS_DDR4
45 select ARCH_EARLY_INIT_R
46 select BOARD_EARLY_INIT_F
48 select SYS_I2C_MXC_I2C1
49 select SYS_I2C_MXC_I2C2
50 select SYS_I2C_MXC_I2C3
51 select SYS_I2C_MXC_I2C4
58 select ARMV8_SET_SMPEN
64 select SYS_FSL_DDR_VER_50
65 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
66 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
67 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
68 select SYS_FSL_ERRATUM_A008997
69 select SYS_FSL_ERRATUM_A009007
70 select SYS_FSL_ERRATUM_A009008
71 select SYS_FSL_ERRATUM_A009798
72 select SYS_FSL_ERRATUM_A009801
73 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
74 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
75 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
76 select SYS_FSL_ERRATUM_A010539
77 select SYS_FSL_HAS_DDR4
79 select ARCH_EARLY_INIT_R
80 select BOARD_EARLY_INIT_F
82 select SYS_I2C_MXC_I2C1
83 select SYS_I2C_MXC_I2C2
84 select SYS_I2C_MXC_I2C3
85 select SYS_I2C_MXC_I2C4
91 select ARMV8_SET_SMPEN
92 select ARM_ERRATA_855873
98 select SYS_FSL_DDR_VER_50
101 select SYS_FSL_ERRATUM_A009803
102 select SYS_FSL_ERRATUM_A009942
103 select SYS_FSL_ERRATUM_A010165
104 select SYS_FSL_ERRATUM_A008511
105 select SYS_FSL_ERRATUM_A008850
106 select SYS_FSL_ERRATUM_A009007
107 select SYS_FSL_HAS_CCI400
108 select SYS_FSL_HAS_DDR4
109 select SYS_FSL_HAS_RGMII
110 select SYS_FSL_HAS_SEC
111 select SYS_FSL_SEC_COMPAT_5
112 select SYS_FSL_SEC_LE
113 select SYS_FSL_SRDS_1
114 select SYS_FSL_SRDS_2
116 select ARCH_EARLY_INIT_R
117 select BOARD_EARLY_INIT_F
119 select SYS_I2C_MXC_I2C1
120 select SYS_I2C_MXC_I2C2
121 select SYS_I2C_MXC_I2C3
122 select SYS_I2C_MXC_I2C4
128 select ARMV8_SET_SMPEN
129 select ARM_ERRATA_826974
130 select ARM_ERRATA_828024
131 select ARM_ERRATA_829520
132 select ARM_ERRATA_833471
134 select SYS_FSL_SRDS_1
135 select SYS_HAS_SERDES
137 select SYS_FSL_DDR_LE
138 select SYS_FSL_DDR_VER_50
139 select SYS_FSL_HAS_CCN504
140 select SYS_FSL_HAS_DP_DDR
141 select SYS_FSL_HAS_SEC
142 select SYS_FSL_HAS_DDR4
143 select SYS_FSL_SEC_COMPAT_5
144 select SYS_FSL_SEC_LE
145 select SYS_FSL_SRDS_2
148 select SYS_FSL_ERRATUM_A008336
149 select SYS_FSL_ERRATUM_A008511
150 select SYS_FSL_ERRATUM_A008514
151 select SYS_FSL_ERRATUM_A008585
152 select SYS_FSL_ERRATUM_A008997
153 select SYS_FSL_ERRATUM_A009007
154 select SYS_FSL_ERRATUM_A009008
155 select SYS_FSL_ERRATUM_A009635
156 select SYS_FSL_ERRATUM_A009663
157 select SYS_FSL_ERRATUM_A009798
158 select SYS_FSL_ERRATUM_A009801
159 select SYS_FSL_ERRATUM_A009803
160 select SYS_FSL_ERRATUM_A009942
161 select SYS_FSL_ERRATUM_A010165
162 select SYS_FSL_ERRATUM_A009203
163 select ARCH_EARLY_INIT_R
164 select BOARD_EARLY_INIT_F
166 select SYS_I2C_MXC_I2C1
167 select SYS_I2C_MXC_I2C2
168 select SYS_I2C_MXC_I2C3
169 select SYS_I2C_MXC_I2C4
170 imply DISTRO_DEFAULTS
175 select SYS_FSL_HAS_CCI400
176 select SYS_FSL_HAS_SEC
177 select SYS_FSL_SEC_COMPAT_5
178 select SYS_FSL_SEC_BE
187 bool "Management Complex network"
188 depends on ARCH_LS2080A || ARCH_LS1088A
192 Enable Management Complex (MC) network
194 menu "Layerscape architecture"
195 depends on FSL_LSCH2 || FSL_LSCH3
197 config FSL_PCIE_COMPAT
198 string "PCIe compatible of Kernel DT"
199 depends on PCIE_LAYERSCAPE
200 default "fsl,ls1012a-pcie" if ARCH_LS1012A
201 default "fsl,ls1043a-pcie" if ARCH_LS1043A
202 default "fsl,ls1046a-pcie" if ARCH_LS1046A
203 default "fsl,ls2080a-pcie" if ARCH_LS2080A
204 default "fsl,ls1088a-pcie" if ARCH_LS1088A
206 This compatible is used to find pci controller node in Kernel DT
209 config HAS_FEATURE_GIC64K_ALIGN
211 default y if ARCH_LS1043A
213 config HAS_FEATURE_ENHANCED_MSI
215 default y if ARCH_LS1043A
217 menu "Layerscape PPA"
219 bool "FSL Layerscape PPA firmware support"
220 depends on !ARMV8_PSCI
221 select ARMV8_SEC_FIRMWARE_SUPPORT
222 select SEC_FIRMWARE_ARMV8_PSCI
223 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
225 The FSL Primary Protected Application (PPA) is a software component
226 which is loaded during boot stage, and then remains resident in RAM
227 and runs in the TrustZone after boot.
230 config SPL_FSL_LS_PPA
231 bool "FSL Layerscape PPA firmware support for SPL build"
232 depends on !ARMV8_PSCI
233 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
234 select SEC_FIRMWARE_ARMV8_PSCI
235 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
237 The FSL Primary Protected Application (PPA) is a software component
238 which is loaded during boot stage, and then remains resident in RAM
239 and runs in the TrustZone after boot. This is to load PPA during SPL
240 stage instead of the RAM version of U-Boot. Once PPA is initialized,
241 the rest of U-Boot (including RAM version) runs at EL2.
243 prompt "FSL Layerscape PPA firmware loading-media select"
244 depends on FSL_LS_PPA
245 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
246 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
247 default SYS_LS_PPA_FW_IN_XIP
249 config SYS_LS_PPA_FW_IN_XIP
252 Say Y here if the PPA firmware locate at XIP flash, such
253 as NOR or QSPI flash.
255 config SYS_LS_PPA_FW_IN_MMC
256 bool "eMMC or SD Card"
258 Say Y here if the PPA firmware locate at eMMC/SD card.
260 config SYS_LS_PPA_FW_IN_NAND
263 Say Y here if the PPA firmware locate at NAND flash.
267 config LS_PPA_ESBC_HDR_SIZE
268 hex "Length of PPA ESBC header"
269 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
272 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
273 NAND to memory to validate PPA image.
277 config SYS_FSL_ERRATUM_A008997
278 bool "Workaround for USB PHY erratum A008997"
280 config SYS_FSL_ERRATUM_A009007
283 Workaround for USB PHY erratum A009007
285 config SYS_FSL_ERRATUM_A009008
286 bool "Workaround for USB PHY erratum A009008"
288 config SYS_FSL_ERRATUM_A009798
289 bool "Workaround for USB PHY erratum A009798"
291 config SYS_FSL_ERRATUM_A010315
292 bool "Workaround for PCIe erratum A010315"
294 config SYS_FSL_ERRATUM_A010539
295 bool "Workaround for PIN MUX erratum A010539"
298 int "Maximum number of CPUs permitted for Layerscape"
299 default 4 if ARCH_LS1043A
300 default 4 if ARCH_LS1046A
301 default 16 if ARCH_LS2080A
302 default 8 if ARCH_LS1088A
305 Set this number to the maximum number of possible CPUs in the SoC.
306 SoCs may have multiple clusters with each cluster may have multiple
307 ports. If some ports are reserved but higher ports are used for
308 cores, count the reserved ports. This will allocate enough memory
309 in spin table to properly handle all cores.
314 Enable Freescale Secure Boot feature
317 bool "Init the QSPI AHB bus"
319 The default setting for QSPI AHB bus just support 3bytes addressing.
320 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
321 bus for those flashes to support the full QSPI flash size.
323 config SYS_CCI400_OFFSET
324 hex "Offset for CCI400 base"
325 depends on SYS_FSL_HAS_CCI400
326 default 0x3090000 if ARCH_LS1088A
327 default 0x180000 if FSL_LSCH2
329 Offset for CCI400 base
330 CCI400 base addr = CCSRBAR + CCI400_OFFSET
332 config SYS_FSL_IFC_BANK_COUNT
333 int "Maximum banks of Integrated flash controller"
334 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
335 default 4 if ARCH_LS1043A
336 default 4 if ARCH_LS1046A
337 default 8 if ARCH_LS2080A || ARCH_LS1088A
339 config SYS_FSL_HAS_CCI400
342 config SYS_FSL_HAS_CCN504
345 config SYS_FSL_HAS_DP_DDR
348 config SYS_FSL_SRDS_1
351 config SYS_FSL_SRDS_2
354 config SYS_NXP_SRDS_3
357 config SYS_HAS_SERDES
368 menu "Layerscape clock tree configuration"
369 depends on FSL_LSCH2 || FSL_LSCH3
372 bool "Enable clock tree initialization"
375 config CLUSTER_CLK_FREQ
376 int "Reference clock of core cluster"
377 depends on ARCH_LS1012A
380 This number is the reference clock frequency of core PLL.
381 For most platforms, the core PLL and Platform PLL have the same
382 reference clock, but for some platforms, LS1012A for instance,
383 they are provided sepatately.
385 config SYS_FSL_PCLK_DIV
386 int "Platform clock divider"
387 default 1 if ARCH_LS1043A
388 default 1 if ARCH_LS1046A
389 default 1 if ARCH_LS1088A
392 This is the divider that is used to derive Platform clock from
393 Platform PLL, in another word:
394 Platform_clk = Platform_PLL_freq / this_divider
396 config SYS_FSL_DSPI_CLK_DIV
397 int "DSPI clock divider"
398 default 1 if ARCH_LS1043A
401 This is the divider that is used to derive DSPI clock from Platform
402 clock, in another word DSPI_clk = Platform_clk / this_divider.
404 config SYS_FSL_DUART_CLK_DIV
405 int "DUART clock divider"
406 default 1 if ARCH_LS1043A
409 This is the divider that is used to derive DUART clock from Platform
410 clock, in another word DUART_clk = Platform_clk / this_divider.
412 config SYS_FSL_I2C_CLK_DIV
413 int "I2C clock divider"
414 default 1 if ARCH_LS1043A
417 This is the divider that is used to derive I2C clock from Platform
418 clock, in another word I2C_clk = Platform_clk / this_divider.
420 config SYS_FSL_IFC_CLK_DIV
421 int "IFC clock divider"
422 default 1 if ARCH_LS1043A
425 This is the divider that is used to derive IFC clock from Platform
426 clock, in another word IFC_clk = Platform_clk / this_divider.
428 config SYS_FSL_LPUART_CLK_DIV
429 int "LPUART clock divider"
430 default 1 if ARCH_LS1043A
433 This is the divider that is used to derive LPUART clock from Platform
434 clock, in another word LPUART_clk = Platform_clk / this_divider.
436 config SYS_FSL_SDHC_CLK_DIV
437 int "SDHC clock divider"
438 default 1 if ARCH_LS1043A
439 default 1 if ARCH_LS1012A
442 This is the divider that is used to derive SDHC clock from Platform
443 clock, in another word SDHC_clk = Platform_clk / this_divider.
445 config SYS_FSL_QMAN_CLK_DIV
446 int "QMAN clock divider"
447 default 1 if ARCH_LS1043A
450 This is the divider that is used to derive QMAN clock from Platform
451 clock, in another word QMAN_clk = Platform_clk / this_divider.
457 Reserve memory from the top, tracked by gd->arch.resv_ram. This
458 reserved RAM can be used by special driver that resides in memory
459 after U-Boot exits. It's up to implementation to allocate and allow
460 access to this reserved memory. For example, the reserved RAM can
461 be at the high end of physical memory. The reserve RAM may be
462 excluded from memory bank(s) passed to OS, or marked as reserved.
467 Ethernet controller 1, this is connected to MAC3.
468 Provides DPAA2 capabilities
473 Ethernet controller 2, this is connected to MAC4.
474 Provides DPAA2 capabilities
476 config SYS_FSL_ERRATUM_A008336
479 config SYS_FSL_ERRATUM_A008514
482 config SYS_FSL_ERRATUM_A008585
485 config SYS_FSL_ERRATUM_A008850
488 config SYS_FSL_ERRATUM_A009203
491 config SYS_FSL_ERRATUM_A009635
494 config SYS_FSL_ERRATUM_A009660
497 config SYS_FSL_ERRATUM_A009929
501 config SYS_FSL_HAS_RGMII
503 depends on SYS_FSL_EC1 || SYS_FSL_EC2
506 config SYS_MC_RSV_MEM_ALIGN
507 hex "Management Complex reserved memory alignment"
509 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A
511 Reserved memory needs to be aligned for MC to use. Default value
515 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
517 config HAS_FSL_XHCI_USB
519 default y if ARCH_LS1043A || ARCH_LS1046A
521 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
522 pins, select it when the pins are assigned to USB.
525 bool "Support for booting from TFA"
528 Enabling this will make a U-Boot binary that is capable of being