4 select ARM_ERRATA_855873 if !TFABOOT
10 select SYS_FSL_ERRATUM_A010315
11 select SYS_FSL_ERRATUM_A009798
12 select SYS_FSL_ERRATUM_A008997
13 select SYS_FSL_ERRATUM_A009007
14 select SYS_FSL_ERRATUM_A009008
15 select ARCH_EARLY_INIT_R
16 select BOARD_EARLY_INIT_F
18 select SYS_I2C_MXC_I2C1
19 select SYS_I2C_MXC_I2C2
24 select ARMV8_SET_SMPEN
25 select ARM_ERRATA_855873 if !TFABOOT
31 select SYS_FSL_DDR_VER_50
32 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
33 select SYS_FSL_ERRATUM_A008997
34 select SYS_FSL_ERRATUM_A009007
35 select SYS_FSL_ERRATUM_A009008
36 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
37 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
38 select SYS_FSL_ERRATUM_A009798
39 select SYS_FSL_ERRATUM_A009929
40 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
41 select SYS_FSL_ERRATUM_A010315
42 select SYS_FSL_ERRATUM_A010539
43 select SYS_FSL_HAS_DDR3
44 select SYS_FSL_HAS_DDR4
45 select ARCH_EARLY_INIT_R
46 select BOARD_EARLY_INIT_F
48 select SYS_I2C_MXC_I2C1
49 select SYS_I2C_MXC_I2C2
50 select SYS_I2C_MXC_I2C3
51 select SYS_I2C_MXC_I2C4
58 select ARMV8_SET_SMPEN
64 select SYS_FSL_DDR_VER_50
65 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
66 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
67 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
68 select SYS_FSL_ERRATUM_A008997
69 select SYS_FSL_ERRATUM_A009007
70 select SYS_FSL_ERRATUM_A009008
71 select SYS_FSL_ERRATUM_A009798
72 select SYS_FSL_ERRATUM_A009801
73 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
74 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
75 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
76 select SYS_FSL_ERRATUM_A010539
77 select SYS_FSL_HAS_DDR4
79 select ARCH_EARLY_INIT_R
80 select BOARD_EARLY_INIT_F
82 select SYS_I2C_MXC_I2C1
83 select SYS_I2C_MXC_I2C2
84 select SYS_I2C_MXC_I2C3
85 select SYS_I2C_MXC_I2C4
91 select ARMV8_SET_SMPEN
92 select ARM_ERRATA_855873 if !TFABOOT
98 select SYS_FSL_DDR_VER_50
101 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
102 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
103 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
104 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
105 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
106 select SYS_FSL_ERRATUM_A009007
107 select SYS_FSL_HAS_CCI400
108 select SYS_FSL_HAS_DDR4
109 select SYS_FSL_HAS_RGMII
110 select SYS_FSL_HAS_SEC
111 select SYS_FSL_SEC_COMPAT_5
112 select SYS_FSL_SEC_LE
113 select SYS_FSL_SRDS_1
114 select SYS_FSL_SRDS_2
117 select FSL_TZPC_BP147
118 select ARCH_EARLY_INIT_R
119 select BOARD_EARLY_INIT_F
121 select SYS_I2C_MXC_I2C1
122 select SYS_I2C_MXC_I2C2
123 select SYS_I2C_MXC_I2C3
124 select SYS_I2C_MXC_I2C4
130 select ARMV8_SET_SMPEN
131 select ARM_ERRATA_826974
132 select ARM_ERRATA_828024
133 select ARM_ERRATA_829520
134 select ARM_ERRATA_833471
136 select SYS_FSL_SRDS_1
137 select SYS_HAS_SERDES
139 select SYS_FSL_DDR_LE
140 select SYS_FSL_DDR_VER_50
141 select SYS_FSL_HAS_CCN504
142 select SYS_FSL_HAS_DP_DDR
143 select SYS_FSL_HAS_SEC
144 select SYS_FSL_HAS_DDR4
145 select SYS_FSL_SEC_COMPAT_5
146 select SYS_FSL_SEC_LE
147 select SYS_FSL_SRDS_2
151 select FSL_TZPC_BP147
152 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
153 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
154 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
155 select SYS_FSL_ERRATUM_A008585
156 select SYS_FSL_ERRATUM_A008997
157 select SYS_FSL_ERRATUM_A009007
158 select SYS_FSL_ERRATUM_A009008
159 select SYS_FSL_ERRATUM_A009635
160 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
161 select SYS_FSL_ERRATUM_A009798
162 select SYS_FSL_ERRATUM_A009801
163 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
164 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
165 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
166 select SYS_FSL_ERRATUM_A009203
167 select ARCH_EARLY_INIT_R
168 select BOARD_EARLY_INIT_F
170 select SYS_I2C_MXC_I2C1
171 select SYS_I2C_MXC_I2C2
172 select SYS_I2C_MXC_I2C3
173 select SYS_I2C_MXC_I2C4
174 imply DISTRO_DEFAULTS
179 select ARMV8_SET_SMPEN
182 select SYS_HAS_SERDES
183 select SYS_FSL_SRDS_1
184 select SYS_FSL_SRDS_2
185 select SYS_NXP_SRDS_3
187 select SYS_FSL_DDR_LE
188 select SYS_FSL_DDR_VER_50
191 select SYS_FSL_HAS_RGMII
192 select SYS_FSL_HAS_SEC
193 select SYS_FSL_HAS_CCN508
194 select SYS_FSL_HAS_DDR4
195 select SYS_FSL_SEC_COMPAT_5
196 select SYS_FSL_SEC_LE
197 select ARCH_EARLY_INIT_R
198 select BOARD_EARLY_INIT_F
200 select SYS_I2C_MXC_I2C1
201 select SYS_I2C_MXC_I2C2
202 select SYS_I2C_MXC_I2C3
203 select SYS_I2C_MXC_I2C4
204 select SYS_I2C_MXC_I2C5
205 select SYS_I2C_MXC_I2C6
206 select SYS_I2C_MXC_I2C7
207 select SYS_I2C_MXC_I2C8
208 imply DISTRO_DEFAULTS
215 select SYS_FSL_HAS_CCI400
216 select SYS_FSL_HAS_SEC
217 select SYS_FSL_SEC_COMPAT_5
218 select SYS_FSL_SEC_BE
227 bool "Management Complex network"
228 depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
232 Enable Management Complex (MC) network
234 menu "Layerscape architecture"
235 depends on FSL_LSCH2 || FSL_LSCH3
237 config FSL_PCIE_COMPAT
238 string "PCIe compatible of Kernel DT"
239 depends on PCIE_LAYERSCAPE
240 default "fsl,ls1012a-pcie" if ARCH_LS1012A
241 default "fsl,ls1043a-pcie" if ARCH_LS1043A
242 default "fsl,ls1046a-pcie" if ARCH_LS1046A
243 default "fsl,ls2080a-pcie" if ARCH_LS2080A
244 default "fsl,ls1088a-pcie" if ARCH_LS1088A
245 default "fsl,lx2160a-pcie" if ARCH_LX2160A
247 This compatible is used to find pci controller node in Kernel DT
250 config HAS_FEATURE_GIC64K_ALIGN
252 default y if ARCH_LS1043A
254 config HAS_FEATURE_ENHANCED_MSI
256 default y if ARCH_LS1043A
258 menu "Layerscape PPA"
260 bool "FSL Layerscape PPA firmware support"
261 depends on !ARMV8_PSCI
262 select ARMV8_SEC_FIRMWARE_SUPPORT
263 select SEC_FIRMWARE_ARMV8_PSCI
264 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
266 The FSL Primary Protected Application (PPA) is a software component
267 which is loaded during boot stage, and then remains resident in RAM
268 and runs in the TrustZone after boot.
271 config SPL_FSL_LS_PPA
272 bool "FSL Layerscape PPA firmware support for SPL build"
273 depends on !ARMV8_PSCI
274 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
275 select SEC_FIRMWARE_ARMV8_PSCI
276 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
278 The FSL Primary Protected Application (PPA) is a software component
279 which is loaded during boot stage, and then remains resident in RAM
280 and runs in the TrustZone after boot. This is to load PPA during SPL
281 stage instead of the RAM version of U-Boot. Once PPA is initialized,
282 the rest of U-Boot (including RAM version) runs at EL2.
284 prompt "FSL Layerscape PPA firmware loading-media select"
285 depends on FSL_LS_PPA
286 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
287 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
288 default SYS_LS_PPA_FW_IN_XIP
290 config SYS_LS_PPA_FW_IN_XIP
293 Say Y here if the PPA firmware locate at XIP flash, such
294 as NOR or QSPI flash.
296 config SYS_LS_PPA_FW_IN_MMC
297 bool "eMMC or SD Card"
299 Say Y here if the PPA firmware locate at eMMC/SD card.
301 config SYS_LS_PPA_FW_IN_NAND
304 Say Y here if the PPA firmware locate at NAND flash.
308 config LS_PPA_ESBC_HDR_SIZE
309 hex "Length of PPA ESBC header"
310 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
313 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
314 NAND to memory to validate PPA image.
318 config SYS_FSL_ERRATUM_A008997
319 bool "Workaround for USB PHY erratum A008997"
321 config SYS_FSL_ERRATUM_A009007
324 Workaround for USB PHY erratum A009007
326 config SYS_FSL_ERRATUM_A009008
327 bool "Workaround for USB PHY erratum A009008"
329 config SYS_FSL_ERRATUM_A009798
330 bool "Workaround for USB PHY erratum A009798"
332 config SYS_FSL_ERRATUM_A010315
333 bool "Workaround for PCIe erratum A010315"
335 config SYS_FSL_ERRATUM_A010539
336 bool "Workaround for PIN MUX erratum A010539"
339 int "Maximum number of CPUs permitted for Layerscape"
340 default 4 if ARCH_LS1043A
341 default 4 if ARCH_LS1046A
342 default 16 if ARCH_LS2080A
343 default 8 if ARCH_LS1088A
344 default 16 if ARCH_LX2160A
347 Set this number to the maximum number of possible CPUs in the SoC.
348 SoCs may have multiple clusters with each cluster may have multiple
349 ports. If some ports are reserved but higher ports are used for
350 cores, count the reserved ports. This will allocate enough memory
351 in spin table to properly handle all cores.
354 bool "Fan controller"
356 Enable the EMC2305 fan controller for configuration of fan
362 Enable Freescale Secure Boot feature
365 bool "Init the QSPI AHB bus"
367 The default setting for QSPI AHB bus just support 3bytes addressing.
368 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
369 bus for those flashes to support the full QSPI flash size.
371 config SYS_CCI400_OFFSET
372 hex "Offset for CCI400 base"
373 depends on SYS_FSL_HAS_CCI400
374 default 0x3090000 if ARCH_LS1088A
375 default 0x180000 if FSL_LSCH2
377 Offset for CCI400 base
378 CCI400 base addr = CCSRBAR + CCI400_OFFSET
380 config SYS_FSL_IFC_BANK_COUNT
381 int "Maximum banks of Integrated flash controller"
382 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
383 default 4 if ARCH_LS1043A
384 default 4 if ARCH_LS1046A
385 default 8 if ARCH_LS2080A || ARCH_LS1088A
387 config SYS_FSL_HAS_CCI400
390 config SYS_FSL_HAS_CCN504
393 config SYS_FSL_HAS_CCN508
396 config SYS_FSL_HAS_DP_DDR
399 config SYS_FSL_SRDS_1
402 config SYS_FSL_SRDS_2
405 config SYS_NXP_SRDS_3
408 config SYS_HAS_SERDES
420 config FSL_TZPC_BP147
424 menu "Layerscape clock tree configuration"
425 depends on FSL_LSCH2 || FSL_LSCH3
428 bool "Enable clock tree initialization"
431 config CLUSTER_CLK_FREQ
432 int "Reference clock of core cluster"
433 depends on ARCH_LS1012A
436 This number is the reference clock frequency of core PLL.
437 For most platforms, the core PLL and Platform PLL have the same
438 reference clock, but for some platforms, LS1012A for instance,
439 they are provided sepatately.
441 config SYS_FSL_PCLK_DIV
442 int "Platform clock divider"
443 default 1 if ARCH_LS1043A
444 default 1 if ARCH_LS1046A
445 default 1 if ARCH_LS1088A
448 This is the divider that is used to derive Platform clock from
449 Platform PLL, in another word:
450 Platform_clk = Platform_PLL_freq / this_divider
452 config SYS_FSL_DSPI_CLK_DIV
453 int "DSPI clock divider"
454 default 1 if ARCH_LS1043A
457 This is the divider that is used to derive DSPI clock from Platform
458 clock, in another word DSPI_clk = Platform_clk / this_divider.
460 config SYS_FSL_DUART_CLK_DIV
461 int "DUART clock divider"
462 default 1 if ARCH_LS1043A
463 default 4 if ARCH_LX2160A
466 This is the divider that is used to derive DUART clock from Platform
467 clock, in another word DUART_clk = Platform_clk / this_divider.
469 config SYS_FSL_I2C_CLK_DIV
470 int "I2C clock divider"
471 default 1 if ARCH_LS1043A
474 This is the divider that is used to derive I2C clock from Platform
475 clock, in another word I2C_clk = Platform_clk / this_divider.
477 config SYS_FSL_IFC_CLK_DIV
478 int "IFC clock divider"
479 default 1 if ARCH_LS1043A
482 This is the divider that is used to derive IFC clock from Platform
483 clock, in another word IFC_clk = Platform_clk / this_divider.
485 config SYS_FSL_LPUART_CLK_DIV
486 int "LPUART clock divider"
487 default 1 if ARCH_LS1043A
490 This is the divider that is used to derive LPUART clock from Platform
491 clock, in another word LPUART_clk = Platform_clk / this_divider.
493 config SYS_FSL_SDHC_CLK_DIV
494 int "SDHC clock divider"
495 default 1 if ARCH_LS1043A
496 default 1 if ARCH_LS1012A
499 This is the divider that is used to derive SDHC clock from Platform
500 clock, in another word SDHC_clk = Platform_clk / this_divider.
502 config SYS_FSL_QMAN_CLK_DIV
503 int "QMAN clock divider"
504 default 1 if ARCH_LS1043A
507 This is the divider that is used to derive QMAN clock from Platform
508 clock, in another word QMAN_clk = Platform_clk / this_divider.
514 Reserve memory from the top, tracked by gd->arch.resv_ram. This
515 reserved RAM can be used by special driver that resides in memory
516 after U-Boot exits. It's up to implementation to allocate and allow
517 access to this reserved memory. For example, the reserved RAM can
518 be at the high end of physical memory. The reserve RAM may be
519 excluded from memory bank(s) passed to OS, or marked as reserved.
524 Ethernet controller 1, this is connected to
525 MAC17 for LX2160A or to MAC3 for other SoCs
526 Provides DPAA2 capabilities
531 Ethernet controller 2, this is connected to
532 MAC18 for LX2160A or to MAC4 for other SoCs
533 Provides DPAA2 capabilities
535 config SYS_FSL_ERRATUM_A008336
538 config SYS_FSL_ERRATUM_A008514
541 config SYS_FSL_ERRATUM_A008585
544 config SYS_FSL_ERRATUM_A008850
547 config SYS_FSL_ERRATUM_A009203
550 config SYS_FSL_ERRATUM_A009635
553 config SYS_FSL_ERRATUM_A009660
556 config SYS_FSL_ERRATUM_A009929
560 config SYS_FSL_HAS_RGMII
562 depends on SYS_FSL_EC1 || SYS_FSL_EC2
565 config SYS_MC_RSV_MEM_ALIGN
566 hex "Management Complex reserved memory alignment"
568 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
570 Reserved memory needs to be aligned for MC to use. Default value
574 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
576 config HAS_FSL_XHCI_USB
578 default y if ARCH_LS1043A || ARCH_LS1046A
580 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
581 pins, select it when the pins are assigned to USB.
584 bool "Support for booting from TFA"
587 Enabling this will make a U-Boot binary that is capable of being