4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1
20 select SYS_I2C_MXC_I2C2
25 select ARMV8_SET_SMPEN
28 select SYS_FSL_HAS_CCI400
33 select SYS_FSL_DDR_VER_50
34 select SYS_FSL_HAS_DDR3
35 select SYS_FSL_HAS_DDR4
36 select SYS_FSL_HAS_SEC
37 select SYS_FSL_SEC_COMPAT_5
40 select ARCH_EARLY_INIT_R
41 select BOARD_EARLY_INIT_F
43 select SYS_FSL_ERRATUM_A008997
44 select SYS_FSL_ERRATUM_A009007
45 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
46 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
48 select SYS_FSL_ERRATUM_A050382
53 select ARMV8_SET_SMPEN
54 select ARM_ERRATA_855873 if !TFABOOT
61 select SYS_FSL_DDR_VER_50
62 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
63 select SYS_FSL_ERRATUM_A008997
64 select SYS_FSL_ERRATUM_A009007
65 select SYS_FSL_ERRATUM_A009008
66 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
67 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
68 select SYS_FSL_ERRATUM_A009798
69 select SYS_FSL_ERRATUM_A009929
70 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
71 select SYS_FSL_ERRATUM_A010315
72 select SYS_FSL_ERRATUM_A010539
73 select SYS_FSL_HAS_DDR3
74 select SYS_FSL_HAS_DDR4
75 select ARCH_EARLY_INIT_R
76 select BOARD_EARLY_INIT_F
78 select SYS_I2C_MXC_I2C1
79 select SYS_I2C_MXC_I2C2
80 select SYS_I2C_MXC_I2C3
81 select SYS_I2C_MXC_I2C4
86 select ARMV8_SET_SMPEN
93 select SYS_FSL_DDR_VER_50
94 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
95 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
96 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
97 select SYS_FSL_ERRATUM_A008997
98 select SYS_FSL_ERRATUM_A009007
99 select SYS_FSL_ERRATUM_A009008
100 select SYS_FSL_ERRATUM_A009798
101 select SYS_FSL_ERRATUM_A009801
102 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
103 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
104 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
105 select SYS_FSL_ERRATUM_A010539
106 select SYS_FSL_HAS_DDR4
107 select SYS_FSL_SRDS_2
108 select ARCH_EARLY_INIT_R
109 select BOARD_EARLY_INIT_F
111 select SYS_I2C_MXC_I2C1
112 select SYS_I2C_MXC_I2C2
113 select SYS_I2C_MXC_I2C3
114 select SYS_I2C_MXC_I2C4
120 select ARMV8_SET_SMPEN
121 select ARM_ERRATA_855873 if !TFABOOT
122 select FSL_LAYERSCAPE
124 select SYS_FSL_SRDS_1
125 select SYS_HAS_SERDES
127 select SYS_FSL_DDR_LE
128 select SYS_FSL_DDR_VER_50
131 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
132 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
133 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
134 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
135 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
136 select SYS_FSL_ERRATUM_A009007
137 select SYS_FSL_HAS_CCI400
138 select SYS_FSL_HAS_DDR4
139 select SYS_FSL_HAS_RGMII
140 select SYS_FSL_HAS_SEC
141 select SYS_FSL_SEC_COMPAT_5
142 select SYS_FSL_SEC_LE
143 select SYS_FSL_SRDS_1
144 select SYS_FSL_SRDS_2
147 select FSL_TZPC_BP147
148 select ARCH_EARLY_INIT_R
149 select BOARD_EARLY_INIT_F
151 select SYS_I2C_MXC_I2C1 if !TFABOOT
152 select SYS_I2C_MXC_I2C2 if !TFABOOT
153 select SYS_I2C_MXC_I2C3 if !TFABOOT
154 select SYS_I2C_MXC_I2C4 if !TFABOOT
160 select ARMV8_SET_SMPEN
161 select ARM_ERRATA_826974
162 select ARM_ERRATA_828024
163 select ARM_ERRATA_829520
164 select ARM_ERRATA_833471
165 select FSL_LAYERSCAPE
167 select SYS_FSL_SRDS_1
168 select SYS_HAS_SERDES
170 select SYS_FSL_DDR_LE
171 select SYS_FSL_DDR_VER_50
172 select SYS_FSL_HAS_CCN504
173 select SYS_FSL_HAS_DP_DDR
174 select SYS_FSL_HAS_SEC
175 select SYS_FSL_HAS_DDR4
176 select SYS_FSL_SEC_COMPAT_5
177 select SYS_FSL_SEC_LE
178 select SYS_FSL_SRDS_2
182 select FSL_TZPC_BP147
183 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
184 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
185 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
186 select SYS_FSL_ERRATUM_A008585
187 select SYS_FSL_ERRATUM_A008997
188 select SYS_FSL_ERRATUM_A009007
189 select SYS_FSL_ERRATUM_A009008
190 select SYS_FSL_ERRATUM_A009635
191 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
192 select SYS_FSL_ERRATUM_A009798
193 select SYS_FSL_ERRATUM_A009801
194 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
195 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
196 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
197 select SYS_FSL_ERRATUM_A009203
198 select ARCH_EARLY_INIT_R
199 select BOARD_EARLY_INIT_F
201 select SYS_I2C_MXC_I2C1 if !TFABOOT
202 select SYS_I2C_MXC_I2C2 if !TFABOOT
203 select SYS_I2C_MXC_I2C3 if !TFABOOT
204 select SYS_I2C_MXC_I2C4 if !TFABOOT
205 imply DISTRO_DEFAULTS
210 select ARMV8_SET_SMPEN
213 select SYS_HAS_SERDES
214 select SYS_FSL_SRDS_1
215 select SYS_FSL_SRDS_2
216 select SYS_NXP_SRDS_3
218 select SYS_FSL_DDR_LE
219 select SYS_FSL_DDR_VER_50
222 select SYS_FSL_HAS_RGMII
223 select SYS_FSL_HAS_SEC
224 select SYS_FSL_HAS_CCN508
225 select SYS_FSL_HAS_DDR4
226 select SYS_FSL_SEC_COMPAT_5
227 select SYS_FSL_SEC_LE
228 select ARCH_EARLY_INIT_R
229 select BOARD_EARLY_INIT_F
231 imply DISTRO_DEFAULTS
238 select SYS_FSL_HAS_CCI400
239 select SYS_FSL_HAS_SEC
240 select SYS_FSL_SEC_COMPAT_5
241 select SYS_FSL_SEC_BE
249 menu "Layerscape architecture"
250 depends on FSL_LSCH2 || FSL_LSCH3
252 config FSL_LAYERSCAPE
255 config FSL_PCIE_COMPAT
256 string "PCIe compatible of Kernel DT"
257 depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
258 default "fsl,ls1012a-pcie" if ARCH_LS1012A
259 default "fsl,ls1028a-pcie" if ARCH_LS1028A
260 default "fsl,ls1043a-pcie" if ARCH_LS1043A
261 default "fsl,ls1046a-pcie" if ARCH_LS1046A
262 default "fsl,ls2080a-pcie" if ARCH_LS2080A
263 default "fsl,ls1088a-pcie" if ARCH_LS1088A
264 default "fsl,lx2160a-pcie" if ARCH_LX2160A
266 This compatible is used to find pci controller node in Kernel DT
269 config HAS_FEATURE_GIC64K_ALIGN
271 default y if ARCH_LS1043A
273 config HAS_FEATURE_ENHANCED_MSI
275 default y if ARCH_LS1043A
277 menu "Layerscape PPA"
279 bool "FSL Layerscape PPA firmware support"
280 depends on !ARMV8_PSCI
281 select ARMV8_SEC_FIRMWARE_SUPPORT
282 select SEC_FIRMWARE_ARMV8_PSCI
283 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
285 The FSL Primary Protected Application (PPA) is a software component
286 which is loaded during boot stage, and then remains resident in RAM
287 and runs in the TrustZone after boot.
290 config SPL_FSL_LS_PPA
291 bool "FSL Layerscape PPA firmware support for SPL build"
292 depends on !ARMV8_PSCI
293 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
294 select SEC_FIRMWARE_ARMV8_PSCI
295 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
297 The FSL Primary Protected Application (PPA) is a software component
298 which is loaded during boot stage, and then remains resident in RAM
299 and runs in the TrustZone after boot. This is to load PPA during SPL
300 stage instead of the RAM version of U-Boot. Once PPA is initialized,
301 the rest of U-Boot (including RAM version) runs at EL2.
303 prompt "FSL Layerscape PPA firmware loading-media select"
304 depends on FSL_LS_PPA
305 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
306 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
307 default SYS_LS_PPA_FW_IN_XIP
309 config SYS_LS_PPA_FW_IN_XIP
312 Say Y here if the PPA firmware locate at XIP flash, such
313 as NOR or QSPI flash.
315 config SYS_LS_PPA_FW_IN_MMC
316 bool "eMMC or SD Card"
318 Say Y here if the PPA firmware locate at eMMC/SD card.
320 config SYS_LS_PPA_FW_IN_NAND
323 Say Y here if the PPA firmware locate at NAND flash.
327 config LS_PPA_ESBC_HDR_SIZE
328 hex "Length of PPA ESBC header"
329 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
332 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
333 NAND to memory to validate PPA image.
337 config SYS_FSL_ERRATUM_A008997
338 bool "Workaround for USB PHY erratum A008997"
340 config SYS_FSL_ERRATUM_A009007
343 Workaround for USB PHY erratum A009007
345 config SYS_FSL_ERRATUM_A009008
346 bool "Workaround for USB PHY erratum A009008"
348 config SYS_FSL_ERRATUM_A009798
349 bool "Workaround for USB PHY erratum A009798"
351 config SYS_FSL_ERRATUM_A010315
352 bool "Workaround for PCIe erratum A010315"
354 config SYS_FSL_ERRATUM_A010539
355 bool "Workaround for PIN MUX erratum A010539"
358 int "Maximum number of CPUs permitted for Layerscape"
359 default 2 if ARCH_LS1028A
360 default 4 if ARCH_LS1043A
361 default 4 if ARCH_LS1046A
362 default 16 if ARCH_LS2080A
363 default 8 if ARCH_LS1088A
364 default 16 if ARCH_LX2160A
367 Set this number to the maximum number of possible CPUs in the SoC.
368 SoCs may have multiple clusters with each cluster may have multiple
369 ports. If some ports are reserved but higher ports are used for
370 cores, count the reserved ports. This will allocate enough memory
371 in spin table to properly handle all cores.
374 bool "Fan controller"
376 Enable the EMC2305 fan controller for configuration of fan
382 Enable Freescale Secure Boot feature
385 bool "Init the QSPI AHB bus"
387 The default setting for QSPI AHB bus just support 3bytes addressing.
388 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
389 bus for those flashes to support the full QSPI flash size.
391 config SYS_CCI400_OFFSET
392 hex "Offset for CCI400 base"
393 depends on SYS_FSL_HAS_CCI400
394 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
395 default 0x180000 if FSL_LSCH2
397 Offset for CCI400 base
398 CCI400 base addr = CCSRBAR + CCI400_OFFSET
400 config SYS_FSL_IFC_BANK_COUNT
401 int "Maximum banks of Integrated flash controller"
402 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
403 default 4 if ARCH_LS1043A
404 default 4 if ARCH_LS1046A
405 default 8 if ARCH_LS2080A || ARCH_LS1088A
407 config SYS_FSL_HAS_CCI400
410 config SYS_FSL_HAS_CCN504
413 config SYS_FSL_HAS_CCN508
416 config SYS_FSL_HAS_DP_DDR
419 config SYS_FSL_SRDS_1
422 config SYS_FSL_SRDS_2
425 config SYS_NXP_SRDS_3
428 config SYS_HAS_SERDES
440 config FSL_TZPC_BP147
444 menu "Layerscape clock tree configuration"
445 depends on FSL_LSCH2 || FSL_LSCH3
448 bool "Enable clock tree initialization"
451 config CLUSTER_CLK_FREQ
452 int "Reference clock of core cluster"
453 depends on ARCH_LS1012A
456 This number is the reference clock frequency of core PLL.
457 For most platforms, the core PLL and Platform PLL have the same
458 reference clock, but for some platforms, LS1012A for instance,
459 they are provided sepatately.
461 config SYS_FSL_PCLK_DIV
462 int "Platform clock divider"
463 default 1 if ARCH_LS1028A
464 default 1 if ARCH_LS1043A
465 default 1 if ARCH_LS1046A
466 default 1 if ARCH_LS1088A
469 This is the divider that is used to derive Platform clock from
470 Platform PLL, in another word:
471 Platform_clk = Platform_PLL_freq / this_divider
473 config SYS_FSL_DSPI_CLK_DIV
474 int "DSPI clock divider"
475 default 1 if ARCH_LS1043A
478 This is the divider that is used to derive DSPI clock from Platform
479 clock, in another word DSPI_clk = Platform_clk / this_divider.
481 config SYS_FSL_DUART_CLK_DIV
482 int "DUART clock divider"
483 default 1 if ARCH_LS1043A
484 default 4 if ARCH_LX2160A
487 This is the divider that is used to derive DUART clock from Platform
488 clock, in another word DUART_clk = Platform_clk / this_divider.
490 config SYS_FSL_I2C_CLK_DIV
491 int "I2C clock divider"
492 default 1 if ARCH_LS1043A
493 default 4 if ARCH_LS1012A
494 default 4 if ARCH_LS1028A
495 default 8 if ARCH_LX2160A
496 default 8 if ARCH_LS1088A
499 This is the divider that is used to derive I2C clock from Platform
500 clock, in another word I2C_clk = Platform_clk / this_divider.
502 config SYS_FSL_IFC_CLK_DIV
503 int "IFC clock divider"
504 default 1 if ARCH_LS1043A
505 default 4 if ARCH_LS1012A
506 default 4 if ARCH_LS1028A
507 default 8 if ARCH_LX2160A
508 default 8 if ARCH_LS1088A
511 This is the divider that is used to derive IFC clock from Platform
512 clock, in another word IFC_clk = Platform_clk / this_divider.
514 config SYS_FSL_LPUART_CLK_DIV
515 int "LPUART clock divider"
516 default 1 if ARCH_LS1043A
519 This is the divider that is used to derive LPUART clock from Platform
520 clock, in another word LPUART_clk = Platform_clk / this_divider.
522 config SYS_FSL_SDHC_CLK_DIV
523 int "SDHC clock divider"
524 default 1 if ARCH_LS1043A
525 default 1 if ARCH_LS1012A
528 This is the divider that is used to derive SDHC clock from Platform
529 clock, in another word SDHC_clk = Platform_clk / this_divider.
531 config SYS_FSL_QMAN_CLK_DIV
532 int "QMAN clock divider"
533 default 1 if ARCH_LS1043A
536 This is the divider that is used to derive QMAN clock from Platform
537 clock, in another word QMAN_clk = Platform_clk / this_divider.
543 Reserve memory from the top, tracked by gd->arch.resv_ram. This
544 reserved RAM can be used by special driver that resides in memory
545 after U-Boot exits. It's up to implementation to allocate and allow
546 access to this reserved memory. For example, the reserved RAM can
547 be at the high end of physical memory. The reserve RAM may be
548 excluded from memory bank(s) passed to OS, or marked as reserved.
553 Ethernet controller 1, this is connected to
554 MAC17 for LX2160A or to MAC3 for other SoCs
555 Provides DPAA2 capabilities
560 Ethernet controller 2, this is connected to
561 MAC18 for LX2160A or to MAC4 for other SoCs
562 Provides DPAA2 capabilities
564 config SYS_FSL_ERRATUM_A008336
567 config SYS_FSL_ERRATUM_A008514
570 config SYS_FSL_ERRATUM_A008585
573 config SYS_FSL_ERRATUM_A008850
576 config SYS_FSL_ERRATUM_A009203
579 config SYS_FSL_ERRATUM_A009635
582 config SYS_FSL_ERRATUM_A009660
585 config SYS_FSL_ERRATUM_A009929
588 config SYS_FSL_ERRATUM_A050382
591 config SYS_FSL_HAS_RGMII
593 depends on SYS_FSL_EC1 || SYS_FSL_EC2
596 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
598 config HAS_FSL_XHCI_USB
600 default y if ARCH_LS1043A || ARCH_LS1046A
602 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
603 pins, select it when the pins are assigned to USB.