4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1
20 select SYS_I2C_MXC_I2C2
25 select ARMV8_SET_SMPEN
28 select SYS_FSL_HAS_CCI400
33 select SYS_FSL_DDR_VER_50
34 select SYS_FSL_HAS_DDR3
35 select SYS_FSL_HAS_DDR4
36 select SYS_FSL_HAS_SEC
37 select SYS_FSL_SEC_COMPAT_5
40 select ARCH_EARLY_INIT_R
41 select BOARD_EARLY_INIT_F
43 select SYS_FSL_ERRATUM_A008997
44 select SYS_FSL_ERRATUM_A009007
45 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
46 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
48 select SYS_FSL_ERRATUM_A050382
53 select ARMV8_SET_SMPEN
54 select ARM_ERRATA_855873 if !TFABOOT
61 select SYS_FSL_DDR_VER_50
62 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
63 select SYS_FSL_ERRATUM_A008997
64 select SYS_FSL_ERRATUM_A009007
65 select SYS_FSL_ERRATUM_A009008
66 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
67 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
68 select SYS_FSL_ERRATUM_A009798
69 select SYS_FSL_ERRATUM_A009929
70 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
71 select SYS_FSL_ERRATUM_A010315
72 select SYS_FSL_ERRATUM_A010539
73 select SYS_FSL_HAS_DDR3
74 select SYS_FSL_HAS_DDR4
75 select ARCH_EARLY_INIT_R
76 select BOARD_EARLY_INIT_F
78 select SYS_I2C_MXC_I2C1
79 select SYS_I2C_MXC_I2C2
80 select SYS_I2C_MXC_I2C3
81 select SYS_I2C_MXC_I2C4
86 select ARMV8_SET_SMPEN
93 select SYS_FSL_DDR_VER_50
94 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
95 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
96 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
97 select SYS_FSL_ERRATUM_A008997
98 select SYS_FSL_ERRATUM_A009007
99 select SYS_FSL_ERRATUM_A009008
100 select SYS_FSL_ERRATUM_A009798
101 select SYS_FSL_ERRATUM_A009801
102 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
103 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
104 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
105 select SYS_FSL_ERRATUM_A010539
106 select SYS_FSL_HAS_DDR4
107 select SYS_FSL_SRDS_2
108 select ARCH_EARLY_INIT_R
109 select BOARD_EARLY_INIT_F
111 select SYS_I2C_MXC_I2C1
112 select SYS_I2C_MXC_I2C2
113 select SYS_I2C_MXC_I2C3
114 select SYS_I2C_MXC_I2C4
120 select ARMV8_SET_SMPEN
121 select ARM_ERRATA_855873 if !TFABOOT
122 select FSL_LAYERSCAPE
124 select SYS_FSL_SRDS_1
125 select SYS_HAS_SERDES
127 select SYS_FSL_DDR_LE
128 select SYS_FSL_DDR_VER_50
131 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
132 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
133 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
134 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
135 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
136 select SYS_FSL_ERRATUM_A009007
137 select SYS_FSL_HAS_CCI400
138 select SYS_FSL_HAS_DDR4
139 select SYS_FSL_HAS_RGMII
140 select SYS_FSL_HAS_SEC
141 select SYS_FSL_SEC_COMPAT_5
142 select SYS_FSL_SEC_LE
143 select SYS_FSL_SRDS_1
144 select SYS_FSL_SRDS_2
147 select FSL_TZPC_BP147
148 select ARCH_EARLY_INIT_R
149 select BOARD_EARLY_INIT_F
151 select SYS_I2C_MXC_I2C1 if !TFABOOT
152 select SYS_I2C_MXC_I2C2 if !TFABOOT
153 select SYS_I2C_MXC_I2C3 if !TFABOOT
154 select SYS_I2C_MXC_I2C4 if !TFABOOT
160 select ARMV8_SET_SMPEN
161 select ARM_ERRATA_826974
162 select ARM_ERRATA_828024
163 select ARM_ERRATA_829520
164 select ARM_ERRATA_833471
165 select FSL_LAYERSCAPE
167 select SYS_FSL_SRDS_1
168 select SYS_HAS_SERDES
170 select SYS_FSL_DDR_LE
171 select SYS_FSL_DDR_VER_50
172 select SYS_FSL_HAS_CCN504
173 select SYS_FSL_HAS_DP_DDR
174 select SYS_FSL_HAS_SEC
175 select SYS_FSL_HAS_DDR4
176 select SYS_FSL_SEC_COMPAT_5
177 select SYS_FSL_SEC_LE
178 select SYS_FSL_SRDS_2
182 select FSL_TZPC_BP147
183 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
184 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
185 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
186 select SYS_FSL_ERRATUM_A008585
187 select SYS_FSL_ERRATUM_A008997
188 select SYS_FSL_ERRATUM_A009007
189 select SYS_FSL_ERRATUM_A009008
190 select SYS_FSL_ERRATUM_A009635
191 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
192 select SYS_FSL_ERRATUM_A009798
193 select SYS_FSL_ERRATUM_A009801
194 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
195 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
196 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
197 select SYS_FSL_ERRATUM_A009203
198 select ARCH_EARLY_INIT_R
199 select BOARD_EARLY_INIT_F
201 select SYS_I2C_MXC_I2C1 if !TFABOOT
202 select SYS_I2C_MXC_I2C2 if !TFABOOT
203 select SYS_I2C_MXC_I2C3 if !TFABOOT
204 select SYS_I2C_MXC_I2C4 if !TFABOOT
205 imply DISTRO_DEFAULTS
210 select ARMV8_SET_SMPEN
213 select SYS_HAS_SERDES
214 select SYS_FSL_SRDS_1
215 select SYS_FSL_SRDS_2
216 select SYS_NXP_SRDS_3
218 select SYS_FSL_DDR_LE
219 select SYS_FSL_DDR_VER_50
222 select SYS_FSL_ERRATUM_A050106
223 select SYS_FSL_HAS_RGMII
224 select SYS_FSL_HAS_SEC
225 select SYS_FSL_HAS_CCN508
226 select SYS_FSL_HAS_DDR4
227 select SYS_FSL_SEC_COMPAT_5
228 select SYS_FSL_SEC_LE
229 select ARCH_EARLY_INIT_R
230 select BOARD_EARLY_INIT_F
232 imply DISTRO_DEFAULTS
239 select SYS_FSL_HAS_CCI400
240 select SYS_FSL_HAS_SEC
241 select SYS_FSL_SEC_COMPAT_5
242 select SYS_FSL_SEC_BE
250 menu "Layerscape architecture"
251 depends on FSL_LSCH2 || FSL_LSCH3
253 config FSL_LAYERSCAPE
256 config HAS_FEATURE_GIC64K_ALIGN
258 default y if ARCH_LS1043A
260 config HAS_FEATURE_ENHANCED_MSI
262 default y if ARCH_LS1043A
264 menu "Layerscape PPA"
266 bool "FSL Layerscape PPA firmware support"
267 depends on !ARMV8_PSCI
268 select ARMV8_SEC_FIRMWARE_SUPPORT
269 select SEC_FIRMWARE_ARMV8_PSCI
270 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
272 The FSL Primary Protected Application (PPA) is a software component
273 which is loaded during boot stage, and then remains resident in RAM
274 and runs in the TrustZone after boot.
277 config SPL_FSL_LS_PPA
278 bool "FSL Layerscape PPA firmware support for SPL build"
279 depends on !ARMV8_PSCI
280 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
281 select SEC_FIRMWARE_ARMV8_PSCI
282 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
284 The FSL Primary Protected Application (PPA) is a software component
285 which is loaded during boot stage, and then remains resident in RAM
286 and runs in the TrustZone after boot. This is to load PPA during SPL
287 stage instead of the RAM version of U-Boot. Once PPA is initialized,
288 the rest of U-Boot (including RAM version) runs at EL2.
290 prompt "FSL Layerscape PPA firmware loading-media select"
291 depends on FSL_LS_PPA
292 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
293 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
294 default SYS_LS_PPA_FW_IN_XIP
296 config SYS_LS_PPA_FW_IN_XIP
299 Say Y here if the PPA firmware locate at XIP flash, such
300 as NOR or QSPI flash.
302 config SYS_LS_PPA_FW_IN_MMC
303 bool "eMMC or SD Card"
305 Say Y here if the PPA firmware locate at eMMC/SD card.
307 config SYS_LS_PPA_FW_IN_NAND
310 Say Y here if the PPA firmware locate at NAND flash.
314 config LS_PPA_ESBC_HDR_SIZE
315 hex "Length of PPA ESBC header"
316 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
319 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
320 NAND to memory to validate PPA image.
324 config SYS_FSL_ERRATUM_A008997
325 bool "Workaround for USB PHY erratum A008997"
327 config SYS_FSL_ERRATUM_A009007
330 Workaround for USB PHY erratum A009007
332 config SYS_FSL_ERRATUM_A009008
333 bool "Workaround for USB PHY erratum A009008"
335 config SYS_FSL_ERRATUM_A009798
336 bool "Workaround for USB PHY erratum A009798"
338 config SYS_FSL_ERRATUM_A050106
339 bool "Workaround for USB PHY erratum A050106"
341 USB3.0 Receiver needs to enable fixed equalization
342 for each of PHY instances in an SOC. This is similar
343 to erratum A-009007, but this one is for LX2160A,
344 and the register value is different.
346 config SYS_FSL_ERRATUM_A010315
347 bool "Workaround for PCIe erratum A010315"
349 config SYS_FSL_ERRATUM_A010539
350 bool "Workaround for PIN MUX erratum A010539"
353 int "Maximum number of CPUs permitted for Layerscape"
354 default 2 if ARCH_LS1028A
355 default 4 if ARCH_LS1043A
356 default 4 if ARCH_LS1046A
357 default 16 if ARCH_LS2080A
358 default 8 if ARCH_LS1088A
359 default 16 if ARCH_LX2160A
362 Set this number to the maximum number of possible CPUs in the SoC.
363 SoCs may have multiple clusters with each cluster may have multiple
364 ports. If some ports are reserved but higher ports are used for
365 cores, count the reserved ports. This will allocate enough memory
366 in spin table to properly handle all cores.
369 bool "Fan controller"
371 Enable the EMC2305 fan controller for configuration of fan
377 Enable Freescale Secure Boot feature
380 bool "Init the QSPI AHB bus"
382 The default setting for QSPI AHB bus just support 3bytes addressing.
383 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
384 bus for those flashes to support the full QSPI flash size.
386 config FSPI_AHB_EN_4BYTE
387 bool "Enable 4-byte Fast Read command for AHB mode"
390 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
391 But some FlexSPI flash sizes are up to 64MBytes.
392 This flag enables fast read command for AHB mode and modifies required
393 LUT to support full FlexSPI flash.
395 config SYS_CCI400_OFFSET
396 hex "Offset for CCI400 base"
397 depends on SYS_FSL_HAS_CCI400
398 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
399 default 0x180000 if FSL_LSCH2
401 Offset for CCI400 base
402 CCI400 base addr = CCSRBAR + CCI400_OFFSET
404 config SYS_FSL_IFC_BANK_COUNT
405 int "Maximum banks of Integrated flash controller"
406 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
407 default 4 if ARCH_LS1043A
408 default 4 if ARCH_LS1046A
409 default 8 if ARCH_LS2080A || ARCH_LS1088A
411 config SYS_FSL_HAS_CCI400
414 config SYS_FSL_HAS_CCN504
417 config SYS_FSL_HAS_CCN508
420 config SYS_FSL_HAS_DP_DDR
423 config SYS_FSL_SRDS_1
426 config SYS_FSL_SRDS_2
429 config SYS_NXP_SRDS_3
432 config SYS_HAS_SERDES
444 config FSL_TZPC_BP147
448 menu "Layerscape clock tree configuration"
449 depends on FSL_LSCH2 || FSL_LSCH3
452 bool "Enable clock tree initialization"
455 config CLUSTER_CLK_FREQ
456 int "Reference clock of core cluster"
457 depends on ARCH_LS1012A
460 This number is the reference clock frequency of core PLL.
461 For most platforms, the core PLL and Platform PLL have the same
462 reference clock, but for some platforms, LS1012A for instance,
463 they are provided sepatately.
465 config SYS_FSL_PCLK_DIV
466 int "Platform clock divider"
467 default 1 if ARCH_LS1028A
468 default 1 if ARCH_LS1043A
469 default 1 if ARCH_LS1046A
470 default 1 if ARCH_LS1088A
473 This is the divider that is used to derive Platform clock from
474 Platform PLL, in another word:
475 Platform_clk = Platform_PLL_freq / this_divider
477 config SYS_FSL_DSPI_CLK_DIV
478 int "DSPI clock divider"
479 default 1 if ARCH_LS1043A
482 This is the divider that is used to derive DSPI clock from Platform
483 clock, in another word DSPI_clk = Platform_clk / this_divider.
485 config SYS_FSL_DUART_CLK_DIV
486 int "DUART clock divider"
487 default 1 if ARCH_LS1043A
488 default 4 if ARCH_LX2160A
491 This is the divider that is used to derive DUART clock from Platform
492 clock, in another word DUART_clk = Platform_clk / this_divider.
494 config SYS_FSL_I2C_CLK_DIV
495 int "I2C clock divider"
496 default 1 if ARCH_LS1043A
497 default 4 if ARCH_LS1012A
498 default 4 if ARCH_LS1028A
499 default 8 if ARCH_LX2160A
500 default 8 if ARCH_LS1088A
503 This is the divider that is used to derive I2C clock from Platform
504 clock, in another word I2C_clk = Platform_clk / this_divider.
506 config SYS_FSL_IFC_CLK_DIV
507 int "IFC clock divider"
508 default 1 if ARCH_LS1043A
509 default 4 if ARCH_LS1012A
510 default 4 if ARCH_LS1028A
511 default 8 if ARCH_LX2160A
512 default 8 if ARCH_LS1088A
515 This is the divider that is used to derive IFC clock from Platform
516 clock, in another word IFC_clk = Platform_clk / this_divider.
518 config SYS_FSL_LPUART_CLK_DIV
519 int "LPUART clock divider"
520 default 1 if ARCH_LS1043A
523 This is the divider that is used to derive LPUART clock from Platform
524 clock, in another word LPUART_clk = Platform_clk / this_divider.
526 config SYS_FSL_SDHC_CLK_DIV
527 int "SDHC clock divider"
528 default 1 if ARCH_LS1043A
529 default 1 if ARCH_LS1012A
532 This is the divider that is used to derive SDHC clock from Platform
533 clock, in another word SDHC_clk = Platform_clk / this_divider.
535 config SYS_FSL_QMAN_CLK_DIV
536 int "QMAN clock divider"
537 default 1 if ARCH_LS1043A
540 This is the divider that is used to derive QMAN clock from Platform
541 clock, in another word QMAN_clk = Platform_clk / this_divider.
547 Reserve memory from the top, tracked by gd->arch.resv_ram. This
548 reserved RAM can be used by special driver that resides in memory
549 after U-Boot exits. It's up to implementation to allocate and allow
550 access to this reserved memory. For example, the reserved RAM can
551 be at the high end of physical memory. The reserve RAM may be
552 excluded from memory bank(s) passed to OS, or marked as reserved.
557 Ethernet controller 1, this is connected to
558 MAC17 for LX2160A or to MAC3 for other SoCs
559 Provides DPAA2 capabilities
564 Ethernet controller 2, this is connected to
565 MAC18 for LX2160A or to MAC4 for other SoCs
566 Provides DPAA2 capabilities
568 config SYS_FSL_ERRATUM_A008336
571 config SYS_FSL_ERRATUM_A008514
574 config SYS_FSL_ERRATUM_A008585
577 config SYS_FSL_ERRATUM_A008850
580 config SYS_FSL_ERRATUM_A009203
583 config SYS_FSL_ERRATUM_A009635
586 config SYS_FSL_ERRATUM_A009660
589 config SYS_FSL_ERRATUM_A009929
592 config SYS_FSL_ERRATUM_A050382
595 config SYS_FSL_HAS_RGMII
597 depends on SYS_FSL_EC1 || SYS_FSL_EC2
600 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
602 config HAS_FSL_XHCI_USB
604 default y if ARCH_LS1043A || ARCH_LS1046A
606 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
607 pins, select it when the pins are assigned to USB.