7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F
32 select ARMV8_SET_SMPEN
36 select SYS_FSL_DDR_VER_50
37 select SYS_FSL_ERRATUM_A008336
38 select SYS_FSL_ERRATUM_A008511
39 select SYS_FSL_ERRATUM_A009801
40 select SYS_FSL_ERRATUM_A009803
41 select SYS_FSL_ERRATUM_A009942
42 select SYS_FSL_ERRATUM_A010165
43 select SYS_FSL_ERRATUM_A010539
44 select SYS_FSL_HAS_DDR4
46 select ARCH_EARLY_INIT_R
47 select BOARD_EARLY_INIT_F
51 select ARMV8_SET_SMPEN
52 select ARM_ERRATA_826974
53 select ARM_ERRATA_828024
54 select ARM_ERRATA_829520
55 select ARM_ERRATA_833471
59 select SYS_FSL_DDR_VER_50
60 select SYS_FSL_HAS_DP_DDR
61 select SYS_FSL_HAS_SEC
62 select SYS_FSL_HAS_DDR4
63 select SYS_FSL_SEC_COMPAT_5
66 select SYS_FSL_ERRATUM_A008336
67 select SYS_FSL_ERRATUM_A008511
68 select SYS_FSL_ERRATUM_A008514
69 select SYS_FSL_ERRATUM_A008585
70 select SYS_FSL_ERRATUM_A009635
71 select SYS_FSL_ERRATUM_A009663
72 select SYS_FSL_ERRATUM_A009801
73 select SYS_FSL_ERRATUM_A009803
74 select SYS_FSL_ERRATUM_A009942
75 select SYS_FSL_ERRATUM_A010165
76 select SYS_FSL_ERRATUM_A009203
77 select ARCH_EARLY_INIT_R
78 select BOARD_EARLY_INIT_F
82 select SYS_FSL_HAS_SEC
83 select SYS_FSL_SEC_COMPAT_5
94 bool "Management Complex network"
95 depends on ARCH_LS2080A
99 Enable Management Complex (MC) network
101 menu "Layerscape architecture"
102 depends on FSL_LSCH2 || FSL_LSCH3
104 config FSL_PCIE_COMPAT
105 string "PCIe compatible of Kernel DT"
106 depends on PCIE_LAYERSCAPE
107 default "fsl,ls1012a-pcie" if ARCH_LS1012A
108 default "fsl,ls1043a-pcie" if ARCH_LS1043A
109 default "fsl,ls1046a-pcie" if ARCH_LS1046A
110 default "fsl,ls2080a-pcie" if ARCH_LS2080A
112 This compatible is used to find pci controller node in Kernel DT
115 config HAS_FEATURE_GIC64K_ALIGN
117 default y if ARCH_LS1043A
119 config HAS_FEATURE_ENHANCED_MSI
121 default y if ARCH_LS1043A
123 menu "Layerscape PPA"
125 bool "FSL Layerscape PPA firmware support"
126 depends on !ARMV8_PSCI
127 select ARMV8_SEC_FIRMWARE_SUPPORT
128 select SEC_FIRMWARE_ARMV8_PSCI
129 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
131 The FSL Primary Protected Application (PPA) is a software component
132 which is loaded during boot stage, and then remains resident in RAM
133 and runs in the TrustZone after boot.
136 prompt "FSL Layerscape PPA firmware loading-media select"
137 depends on FSL_LS_PPA
138 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
139 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
140 default SYS_LS_PPA_FW_IN_XIP
142 config SYS_LS_PPA_FW_IN_XIP
145 Say Y here if the PPA firmware locate at XIP flash, such
146 as NOR or QSPI flash.
148 config SYS_LS_PPA_FW_IN_MMC
149 bool "eMMC or SD Card"
151 Say Y here if the PPA firmware locate at eMMC/SD card.
153 config SYS_LS_PPA_FW_IN_NAND
156 Say Y here if the PPA firmware locate at NAND flash.
160 config SYS_LS_PPA_FW_ADDR
161 hex "Address of PPA firmware loading from"
162 depends on FSL_LS_PPA
163 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
164 default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
165 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
166 default 0x500000 if SYS_LS_PPA_FW_IN_MMC
167 default 0x500000 if SYS_LS_PPA_FW_IN_NAND
170 If the PPA firmware locate at XIP flash, such as NOR or
171 QSPI flash, this address is a directly memory-mapped.
172 If it is in a serial accessed flash, such as NAND and SD
173 card, it is a byte offset.
176 config SYS_FSL_ERRATUM_A010315
177 bool "Workaround for PCIe erratum A010315"
179 config SYS_FSL_ERRATUM_A010539
180 bool "Workaround for PIN MUX erratum A010539"
183 int "Maximum number of CPUs permitted for Layerscape"
184 default 4 if ARCH_LS1043A
185 default 4 if ARCH_LS1046A
186 default 16 if ARCH_LS2080A
189 Set this number to the maximum number of possible CPUs in the SoC.
190 SoCs may have multiple clusters with each cluster may have multiple
191 ports. If some ports are reserved but higher ports are used for
192 cores, count the reserved ports. This will allocate enough memory
193 in spin table to properly handle all cores.
198 Enable Freescale Secure Boot feature
201 bool "Init the QSPI AHB bus"
203 The default setting for QSPI AHB bus just support 3bytes addressing.
204 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
205 bus for those flashes to support the full QSPI flash size.
207 config SYS_FSL_IFC_BANK_COUNT
208 int "Maximum banks of Integrated flash controller"
209 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
210 default 4 if ARCH_LS1043A
211 default 4 if ARCH_LS1046A
212 default 8 if ARCH_LS2080A
214 config SYS_FSL_HAS_DP_DDR
217 config SYS_FSL_SRDS_1
220 config SYS_FSL_SRDS_2
223 config SYS_HAS_SERDES
228 menu "Layerscape clock tree configuration"
229 depends on FSL_LSCH2 || FSL_LSCH3
232 bool "Enable clock tree initialization"
235 config CLUSTER_CLK_FREQ
236 int "Reference clock of core cluster"
237 depends on ARCH_LS1012A
240 This number is the reference clock frequency of core PLL.
241 For most platforms, the core PLL and Platform PLL have the same
242 reference clock, but for some platforms, LS1012A for instance,
243 they are provided sepatately.
245 config SYS_FSL_PCLK_DIV
246 int "Platform clock divider"
247 default 1 if ARCH_LS1043A
248 default 1 if ARCH_LS1046A
251 This is the divider that is used to derive Platform clock from
252 Platform PLL, in another word:
253 Platform_clk = Platform_PLL_freq / this_divider
255 config SYS_FSL_DSPI_CLK_DIV
256 int "DSPI clock divider"
257 default 1 if ARCH_LS1043A
260 This is the divider that is used to derive DSPI clock from Platform
261 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
263 config SYS_FSL_DUART_CLK_DIV
264 int "DUART clock divider"
265 default 1 if ARCH_LS1043A
268 This is the divider that is used to derive DUART clock from Platform
269 clock, in another word DUART_clk = Platform_clk / this_divider.
271 config SYS_FSL_I2C_CLK_DIV
272 int "I2C clock divider"
273 default 1 if ARCH_LS1043A
276 This is the divider that is used to derive I2C clock from Platform
277 clock, in another word I2C_clk = Platform_clk / this_divider.
279 config SYS_FSL_IFC_CLK_DIV
280 int "IFC clock divider"
281 default 1 if ARCH_LS1043A
284 This is the divider that is used to derive IFC clock from Platform
285 clock, in another word IFC_clk = Platform_clk / this_divider.
287 config SYS_FSL_LPUART_CLK_DIV
288 int "LPUART clock divider"
289 default 1 if ARCH_LS1043A
292 This is the divider that is used to derive LPUART clock from Platform
293 clock, in another word LPUART_clk = Platform_clk / this_divider.
295 config SYS_FSL_SDHC_CLK_DIV
296 int "SDHC clock divider"
297 default 1 if ARCH_LS1043A
298 default 1 if ARCH_LS1012A
301 This is the divider that is used to derive SDHC clock from Platform
302 clock, in another word SDHC_clk = Platform_clk / this_divider.
308 Reserve memory from the top, tracked by gd->arch.resv_ram. This
309 reserved RAM can be used by special driver that resides in memory
310 after U-Boot exits. It's up to implementation to allocate and allow
311 access to this reserved memory. For example, the reserved RAM can
312 be at the high end of physical memory. The reserve RAM may be
313 excluded from memory bank(s) passed to OS, or marked as reserved.
315 config SYS_FSL_ERRATUM_A008336
318 config SYS_FSL_ERRATUM_A008514
321 config SYS_FSL_ERRATUM_A008585
324 config SYS_FSL_ERRATUM_A008850
327 config SYS_FSL_ERRATUM_A009203
330 config SYS_FSL_ERRATUM_A009635
333 config SYS_FSL_ERRATUM_A009660
336 config SYS_FSL_ERRATUM_A009929
339 config SYS_MC_RSV_MEM_ALIGN
340 hex "Management Complex reserved memory alignment"
344 Reserved memory needs to be aligned for MC to use. Default value