4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1 if !DM_I2C
20 select SYS_I2C_MXC_I2C2 if !DM_I2C
25 select ARMV8_SET_SMPEN
29 select SYS_FSL_HAS_CCI400
34 select SYS_FSL_DDR_VER_50
35 select SYS_FSL_HAS_DDR3
36 select SYS_FSL_HAS_DDR4
37 select SYS_FSL_HAS_SEC
38 select SYS_FSL_SEC_COMPAT_5
41 select ARCH_EARLY_INIT_R
42 select BOARD_EARLY_INIT_F
44 select SYS_FSL_ERRATUM_A008997
45 select SYS_FSL_ERRATUM_A009007
46 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
48 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
49 select SYS_FSL_ERRATUM_A050382
50 select RESV_RAM if GIC_V3_ITS
55 select ARMV8_SET_SMPEN
56 select ARM_ERRATA_855873 if !TFABOOT
63 select SYS_FSL_DDR_VER_50
64 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
65 select SYS_FSL_ERRATUM_A008997
66 select SYS_FSL_ERRATUM_A009007
67 select SYS_FSL_ERRATUM_A009008
68 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
69 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
70 select SYS_FSL_ERRATUM_A009798
71 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
72 select SYS_FSL_ERRATUM_A010315
73 select SYS_FSL_ERRATUM_A010539
74 select SYS_FSL_HAS_DDR3
75 select SYS_FSL_HAS_DDR4
76 select ARCH_EARLY_INIT_R
77 select BOARD_EARLY_INIT_F
79 select SYS_I2C_MXC_I2C1 if !DM_I2C
80 select SYS_I2C_MXC_I2C2 if !DM_I2C
81 select SYS_I2C_MXC_I2C3 if !DM_I2C
82 select SYS_I2C_MXC_I2C4 if !DM_I2C
87 select ARMV8_SET_SMPEN
94 select SYS_FSL_DDR_VER_50
95 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
96 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
97 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
98 select SYS_FSL_ERRATUM_A008997
99 select SYS_FSL_ERRATUM_A009007
100 select SYS_FSL_ERRATUM_A009008
101 select SYS_FSL_ERRATUM_A009798
102 select SYS_FSL_ERRATUM_A009801
103 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
104 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
105 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
106 select SYS_FSL_ERRATUM_A010539
107 select SYS_FSL_HAS_DDR4
108 select SYS_FSL_SRDS_2
109 select ARCH_EARLY_INIT_R
110 select BOARD_EARLY_INIT_F
112 select SYS_I2C_MXC_I2C1 if !DM_I2C
113 select SYS_I2C_MXC_I2C2 if !DM_I2C
114 select SYS_I2C_MXC_I2C3 if !DM_I2C
115 select SYS_I2C_MXC_I2C4 if !DM_I2C
121 select ARMV8_SET_SMPEN
122 select ARM_ERRATA_855873 if !TFABOOT
123 select FSL_LAYERSCAPE
125 select SYS_FSL_SRDS_1
126 select SYS_HAS_SERDES
128 select SYS_FSL_DDR_LE
129 select SYS_FSL_DDR_VER_50
132 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
133 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
134 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
135 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
136 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
137 select SYS_FSL_ERRATUM_A009007
138 select SYS_FSL_HAS_CCI400
139 select SYS_FSL_HAS_DDR4
140 select SYS_FSL_HAS_RGMII
141 select SYS_FSL_HAS_SEC
142 select SYS_FSL_SEC_COMPAT_5
143 select SYS_FSL_SEC_LE
144 select SYS_FSL_SRDS_1
145 select SYS_FSL_SRDS_2
148 select FSL_TZPC_BP147
149 select ARCH_EARLY_INIT_R
150 select BOARD_EARLY_INIT_F
152 select SYS_I2C_MXC_I2C1 if !TFABOOT
153 select SYS_I2C_MXC_I2C2 if !TFABOOT
154 select SYS_I2C_MXC_I2C3 if !TFABOOT
155 select SYS_I2C_MXC_I2C4 if !TFABOOT
156 select RESV_RAM if GIC_V3_ITS
162 select ARMV8_SET_SMPEN
163 select ARM_ERRATA_826974
164 select ARM_ERRATA_828024
165 select ARM_ERRATA_829520
166 select ARM_ERRATA_833471
167 select FSL_LAYERSCAPE
169 select SYS_FSL_SRDS_1
170 select SYS_HAS_SERDES
172 select SYS_FSL_DDR_LE
173 select SYS_FSL_DDR_VER_50
174 select SYS_FSL_HAS_CCN504
175 select SYS_FSL_HAS_DP_DDR
176 select SYS_FSL_HAS_SEC
177 select SYS_FSL_HAS_DDR4
178 select SYS_FSL_SEC_COMPAT_5
179 select SYS_FSL_SEC_LE
180 select SYS_FSL_SRDS_2
184 select FSL_TZPC_BP147
185 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
186 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
187 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
188 select SYS_FSL_ERRATUM_A008585
189 select SYS_FSL_ERRATUM_A008997
190 select SYS_FSL_ERRATUM_A009007
191 select SYS_FSL_ERRATUM_A009008
192 select SYS_FSL_ERRATUM_A009635
193 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
194 select SYS_FSL_ERRATUM_A009798
195 select SYS_FSL_ERRATUM_A009801
196 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
197 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
198 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
199 select SYS_FSL_ERRATUM_A009203
200 select ARCH_EARLY_INIT_R
201 select BOARD_EARLY_INIT_F
203 select SYS_I2C_MXC_I2C1 if !TFABOOT
204 select SYS_I2C_MXC_I2C2 if !TFABOOT
205 select SYS_I2C_MXC_I2C3 if !TFABOOT
206 select SYS_I2C_MXC_I2C4 if !TFABOOT
207 select RESV_RAM if GIC_V3_ITS
208 imply DISTRO_DEFAULTS
213 select ARMV8_SET_SMPEN
216 select SYS_HAS_SERDES
217 select SYS_FSL_SRDS_1
218 select SYS_FSL_SRDS_2
219 select SYS_NXP_SRDS_3
221 select SYS_FSL_DDR_LE
222 select SYS_FSL_DDR_VER_50
225 select SYS_FSL_ERRATUM_A050106
226 select SYS_FSL_HAS_RGMII
227 select SYS_FSL_HAS_SEC
228 select SYS_FSL_HAS_CCN508
229 select SYS_FSL_HAS_DDR4
230 select SYS_FSL_SEC_COMPAT_5
231 select SYS_FSL_SEC_LE
232 select ARCH_EARLY_INIT_R
233 select BOARD_EARLY_INIT_F
235 select RESV_RAM if GIC_V3_ITS
236 imply DISTRO_DEFAULTS
243 select SYS_FSL_HAS_CCI400
244 select SYS_FSL_HAS_SEC
245 select SYS_FSL_SEC_COMPAT_5
246 select SYS_FSL_SEC_BE
249 select ARCH_MISC_INIT
255 menu "Layerscape architecture"
256 depends on FSL_LSCH2 || FSL_LSCH3
258 config FSL_LAYERSCAPE
261 config HAS_FEATURE_GIC64K_ALIGN
263 default y if ARCH_LS1043A
265 config HAS_FEATURE_ENHANCED_MSI
267 default y if ARCH_LS1043A
269 menu "Layerscape PPA"
271 bool "FSL Layerscape PPA firmware support"
272 depends on !ARMV8_PSCI
273 select ARMV8_SEC_FIRMWARE_SUPPORT
274 select SEC_FIRMWARE_ARMV8_PSCI
275 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
277 The FSL Primary Protected Application (PPA) is a software component
278 which is loaded during boot stage, and then remains resident in RAM
279 and runs in the TrustZone after boot.
282 config SPL_FSL_LS_PPA
283 bool "FSL Layerscape PPA firmware support for SPL build"
284 depends on !ARMV8_PSCI
285 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
286 select SEC_FIRMWARE_ARMV8_PSCI
287 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
289 The FSL Primary Protected Application (PPA) is a software component
290 which is loaded during boot stage, and then remains resident in RAM
291 and runs in the TrustZone after boot. This is to load PPA during SPL
292 stage instead of the RAM version of U-Boot. Once PPA is initialized,
293 the rest of U-Boot (including RAM version) runs at EL2.
295 prompt "FSL Layerscape PPA firmware loading-media select"
296 depends on FSL_LS_PPA
297 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
298 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
299 default SYS_LS_PPA_FW_IN_XIP
301 config SYS_LS_PPA_FW_IN_XIP
304 Say Y here if the PPA firmware locate at XIP flash, such
305 as NOR or QSPI flash.
307 config SYS_LS_PPA_FW_IN_MMC
308 bool "eMMC or SD Card"
310 Say Y here if the PPA firmware locate at eMMC/SD card.
312 config SYS_LS_PPA_FW_IN_NAND
315 Say Y here if the PPA firmware locate at NAND flash.
319 config LS_PPA_ESBC_HDR_SIZE
320 hex "Length of PPA ESBC header"
321 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
324 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
325 NAND to memory to validate PPA image.
329 config SYS_FSL_ERRATUM_A008997
330 bool "Workaround for USB PHY erratum A008997"
332 config SYS_FSL_ERRATUM_A009007
335 Workaround for USB PHY erratum A009007
337 config SYS_FSL_ERRATUM_A009008
338 bool "Workaround for USB PHY erratum A009008"
340 config SYS_FSL_ERRATUM_A009798
341 bool "Workaround for USB PHY erratum A009798"
343 config SYS_FSL_ERRATUM_A050106
344 bool "Workaround for USB PHY erratum A050106"
346 USB3.0 Receiver needs to enable fixed equalization
347 for each of PHY instances in an SOC. This is similar
348 to erratum A-009007, but this one is for LX2160A,
349 and the register value is different.
351 config SYS_FSL_ERRATUM_A010315
352 bool "Workaround for PCIe erratum A010315"
354 config SYS_FSL_ERRATUM_A010539
355 bool "Workaround for PIN MUX erratum A010539"
358 int "Maximum number of CPUs permitted for Layerscape"
359 default 2 if ARCH_LS1028A
360 default 4 if ARCH_LS1043A
361 default 4 if ARCH_LS1046A
362 default 16 if ARCH_LS2080A
363 default 8 if ARCH_LS1088A
364 default 16 if ARCH_LX2160A
367 Set this number to the maximum number of possible CPUs in the SoC.
368 SoCs may have multiple clusters with each cluster may have multiple
369 ports. If some ports are reserved but higher ports are used for
370 cores, count the reserved ports. This will allocate enough memory
371 in spin table to properly handle all cores.
374 bool "Fan controller"
376 Enable the EMC2305 fan controller for configuration of fan
382 Enable Freescale Secure Boot feature
385 bool "Init the QSPI AHB bus"
387 The default setting for QSPI AHB bus just support 3bytes addressing.
388 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
389 bus for those flashes to support the full QSPI flash size.
391 config FSPI_AHB_EN_4BYTE
392 bool "Enable 4-byte Fast Read command for AHB mode"
395 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
396 But some FlexSPI flash sizes are up to 64MBytes.
397 This flag enables fast read command for AHB mode and modifies required
398 LUT to support full FlexSPI flash.
400 config SYS_CCI400_OFFSET
401 hex "Offset for CCI400 base"
402 depends on SYS_FSL_HAS_CCI400
403 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
404 default 0x180000 if FSL_LSCH2
406 Offset for CCI400 base
407 CCI400 base addr = CCSRBAR + CCI400_OFFSET
409 config SYS_FSL_IFC_BANK_COUNT
410 int "Maximum banks of Integrated flash controller"
411 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
412 default 4 if ARCH_LS1043A
413 default 4 if ARCH_LS1046A
414 default 8 if ARCH_LS2080A || ARCH_LS1088A
416 config SYS_FSL_HAS_CCI400
419 config SYS_FSL_HAS_CCN504
422 config SYS_FSL_HAS_CCN508
425 config SYS_FSL_HAS_DP_DDR
428 config SYS_FSL_SRDS_1
431 config SYS_FSL_SRDS_2
434 config SYS_NXP_SRDS_3
437 config SYS_HAS_SERDES
449 config FSL_TZPC_BP147
453 menu "Layerscape clock tree configuration"
454 depends on FSL_LSCH2 || FSL_LSCH3
457 bool "Enable clock tree initialization"
460 config CLUSTER_CLK_FREQ
461 int "Reference clock of core cluster"
462 depends on ARCH_LS1012A
465 This number is the reference clock frequency of core PLL.
466 For most platforms, the core PLL and Platform PLL have the same
467 reference clock, but for some platforms, LS1012A for instance,
468 they are provided sepatately.
470 config SYS_FSL_PCLK_DIV
471 int "Platform clock divider"
472 default 1 if ARCH_LS1028A
473 default 1 if ARCH_LS1043A
474 default 1 if ARCH_LS1046A
475 default 1 if ARCH_LS1088A
478 This is the divider that is used to derive Platform clock from
479 Platform PLL, in another word:
480 Platform_clk = Platform_PLL_freq / this_divider
482 config SYS_FSL_DSPI_CLK_DIV
483 int "DSPI clock divider"
484 default 1 if ARCH_LS1043A
487 This is the divider that is used to derive DSPI clock from Platform
488 clock, in another word DSPI_clk = Platform_clk / this_divider.
490 config SYS_FSL_DUART_CLK_DIV
491 int "DUART clock divider"
492 default 1 if ARCH_LS1043A
493 default 4 if ARCH_LX2160A
496 This is the divider that is used to derive DUART clock from Platform
497 clock, in another word DUART_clk = Platform_clk / this_divider.
499 config SYS_FSL_I2C_CLK_DIV
500 int "I2C clock divider"
501 default 1 if ARCH_LS1043A
502 default 4 if ARCH_LS1012A
503 default 4 if ARCH_LS1028A
504 default 8 if ARCH_LX2160A
505 default 8 if ARCH_LS1088A
508 This is the divider that is used to derive I2C clock from Platform
509 clock, in another word I2C_clk = Platform_clk / this_divider.
511 config SYS_FSL_IFC_CLK_DIV
512 int "IFC clock divider"
513 default 1 if ARCH_LS1043A
514 default 4 if ARCH_LS1012A
515 default 4 if ARCH_LS1028A
516 default 8 if ARCH_LX2160A
517 default 8 if ARCH_LS1088A
520 This is the divider that is used to derive IFC clock from Platform
521 clock, in another word IFC_clk = Platform_clk / this_divider.
523 config SYS_FSL_LPUART_CLK_DIV
524 int "LPUART clock divider"
525 default 1 if ARCH_LS1043A
528 This is the divider that is used to derive LPUART clock from Platform
529 clock, in another word LPUART_clk = Platform_clk / this_divider.
531 config SYS_FSL_SDHC_CLK_DIV
532 int "SDHC clock divider"
533 default 1 if ARCH_LS1043A
534 default 1 if ARCH_LS1012A
537 This is the divider that is used to derive SDHC clock from Platform
538 clock, in another word SDHC_clk = Platform_clk / this_divider.
540 config SYS_FSL_QMAN_CLK_DIV
541 int "QMAN clock divider"
542 default 1 if ARCH_LS1043A
545 This is the divider that is used to derive QMAN clock from Platform
546 clock, in another word QMAN_clk = Platform_clk / this_divider.
552 Reserve memory from the top, tracked by gd->arch.resv_ram. This
553 reserved RAM can be used by special driver that resides in memory
554 after U-Boot exits. It's up to implementation to allocate and allow
555 access to this reserved memory. For example, the reserved RAM can
556 be at the high end of physical memory. The reserve RAM may be
557 excluded from memory bank(s) passed to OS, or marked as reserved.
562 Ethernet controller 1, this is connected to
563 MAC17 for LX2160A or to MAC3 for other SoCs
564 Provides DPAA2 capabilities
569 Ethernet controller 2, this is connected to
570 MAC18 for LX2160A or to MAC4 for other SoCs
571 Provides DPAA2 capabilities
573 config SYS_FSL_ERRATUM_A008336
576 config SYS_FSL_ERRATUM_A008514
579 config SYS_FSL_ERRATUM_A008585
582 config SYS_FSL_ERRATUM_A008850
585 config SYS_FSL_ERRATUM_A009203
588 config SYS_FSL_ERRATUM_A009635
591 config SYS_FSL_ERRATUM_A009660
594 config SYS_FSL_ERRATUM_A050382
597 config SYS_FSL_HAS_RGMII
599 depends on SYS_FSL_EC1 || SYS_FSL_EC2
602 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
604 config HAS_FSL_XHCI_USB
606 default y if ARCH_LS1043A || ARCH_LS1046A
608 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
609 pins, select it when the pins are assigned to USB.