4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1
20 select SYS_I2C_MXC_I2C2
25 select ARMV8_SET_SMPEN
26 select ARM_ERRATA_855873 if !TFABOOT
33 select SYS_FSL_DDR_VER_50
34 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
35 select SYS_FSL_ERRATUM_A008997
36 select SYS_FSL_ERRATUM_A009007
37 select SYS_FSL_ERRATUM_A009008
38 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
39 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
40 select SYS_FSL_ERRATUM_A009798
41 select SYS_FSL_ERRATUM_A009929
42 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
43 select SYS_FSL_ERRATUM_A010315
44 select SYS_FSL_ERRATUM_A010539
45 select SYS_FSL_HAS_DDR3
46 select SYS_FSL_HAS_DDR4
47 select ARCH_EARLY_INIT_R
48 select BOARD_EARLY_INIT_F
50 select SYS_I2C_MXC_I2C1
51 select SYS_I2C_MXC_I2C2
52 select SYS_I2C_MXC_I2C3
53 select SYS_I2C_MXC_I2C4
60 select ARMV8_SET_SMPEN
67 select SYS_FSL_DDR_VER_50
68 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
69 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
70 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
71 select SYS_FSL_ERRATUM_A008997
72 select SYS_FSL_ERRATUM_A009007
73 select SYS_FSL_ERRATUM_A009008
74 select SYS_FSL_ERRATUM_A009798
75 select SYS_FSL_ERRATUM_A009801
76 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
77 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
78 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
79 select SYS_FSL_ERRATUM_A010539
80 select SYS_FSL_HAS_DDR4
82 select ARCH_EARLY_INIT_R
83 select BOARD_EARLY_INIT_F
85 select SYS_I2C_MXC_I2C1
86 select SYS_I2C_MXC_I2C2
87 select SYS_I2C_MXC_I2C3
88 select SYS_I2C_MXC_I2C4
94 select ARMV8_SET_SMPEN
95 select ARM_ERRATA_855873 if !TFABOOT
101 select SYS_FSL_DDR_LE
102 select SYS_FSL_DDR_VER_50
105 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
106 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
107 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
108 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
109 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
110 select SYS_FSL_ERRATUM_A009007
111 select SYS_FSL_HAS_CCI400
112 select SYS_FSL_HAS_DDR4
113 select SYS_FSL_HAS_RGMII
114 select SYS_FSL_HAS_SEC
115 select SYS_FSL_SEC_COMPAT_5
116 select SYS_FSL_SEC_LE
117 select SYS_FSL_SRDS_1
118 select SYS_FSL_SRDS_2
121 select FSL_TZPC_BP147
122 select ARCH_EARLY_INIT_R
123 select BOARD_EARLY_INIT_F
125 select SYS_I2C_MXC_I2C1
126 select SYS_I2C_MXC_I2C2
127 select SYS_I2C_MXC_I2C3
128 select SYS_I2C_MXC_I2C4
134 select ARMV8_SET_SMPEN
135 select ARM_ERRATA_826974
136 select ARM_ERRATA_828024
137 select ARM_ERRATA_829520
138 select ARM_ERRATA_833471
139 select FSL_LAYERSCAPE
141 select SYS_FSL_SRDS_1
142 select SYS_HAS_SERDES
144 select SYS_FSL_DDR_LE
145 select SYS_FSL_DDR_VER_50
146 select SYS_FSL_HAS_CCN504
147 select SYS_FSL_HAS_DP_DDR
148 select SYS_FSL_HAS_SEC
149 select SYS_FSL_HAS_DDR4
150 select SYS_FSL_SEC_COMPAT_5
151 select SYS_FSL_SEC_LE
152 select SYS_FSL_SRDS_2
156 select FSL_TZPC_BP147
157 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
158 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
159 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
160 select SYS_FSL_ERRATUM_A008585
161 select SYS_FSL_ERRATUM_A008997
162 select SYS_FSL_ERRATUM_A009007
163 select SYS_FSL_ERRATUM_A009008
164 select SYS_FSL_ERRATUM_A009635
165 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
166 select SYS_FSL_ERRATUM_A009798
167 select SYS_FSL_ERRATUM_A009801
168 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
169 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
170 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
171 select SYS_FSL_ERRATUM_A009203
172 select ARCH_EARLY_INIT_R
173 select BOARD_EARLY_INIT_F
175 select SYS_I2C_MXC_I2C1
176 select SYS_I2C_MXC_I2C2
177 select SYS_I2C_MXC_I2C3
178 select SYS_I2C_MXC_I2C4
179 imply DISTRO_DEFAULTS
184 select ARMV8_SET_SMPEN
187 select SYS_HAS_SERDES
188 select SYS_FSL_SRDS_1
189 select SYS_FSL_SRDS_2
190 select SYS_NXP_SRDS_3
192 select SYS_FSL_DDR_LE
193 select SYS_FSL_DDR_VER_50
196 select SYS_FSL_HAS_RGMII
197 select SYS_FSL_HAS_SEC
198 select SYS_FSL_HAS_CCN508
199 select SYS_FSL_HAS_DDR4
200 select SYS_FSL_SEC_COMPAT_5
201 select SYS_FSL_SEC_LE
202 select ARCH_EARLY_INIT_R
203 select BOARD_EARLY_INIT_F
205 select SYS_I2C_MXC_I2C1
206 select SYS_I2C_MXC_I2C2
207 select SYS_I2C_MXC_I2C3
208 select SYS_I2C_MXC_I2C4
209 select SYS_I2C_MXC_I2C5
210 select SYS_I2C_MXC_I2C6
211 select SYS_I2C_MXC_I2C7
212 select SYS_I2C_MXC_I2C8
213 imply DISTRO_DEFAULTS
220 select SYS_FSL_HAS_CCI400
221 select SYS_FSL_HAS_SEC
222 select SYS_FSL_SEC_COMPAT_5
223 select SYS_FSL_SEC_BE
232 bool "Management Complex network"
233 depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
237 Enable Management Complex (MC) network
239 menu "Layerscape architecture"
240 depends on FSL_LSCH2 || FSL_LSCH3
242 config FSL_LAYERSCAPE
245 config FSL_PCIE_COMPAT
246 string "PCIe compatible of Kernel DT"
247 depends on PCIE_LAYERSCAPE
248 default "fsl,ls1012a-pcie" if ARCH_LS1012A
249 default "fsl,ls1043a-pcie" if ARCH_LS1043A
250 default "fsl,ls1046a-pcie" if ARCH_LS1046A
251 default "fsl,ls2080a-pcie" if ARCH_LS2080A
252 default "fsl,ls1088a-pcie" if ARCH_LS1088A
253 default "fsl,lx2160a-pcie" if ARCH_LX2160A
255 This compatible is used to find pci controller node in Kernel DT
258 config HAS_FEATURE_GIC64K_ALIGN
260 default y if ARCH_LS1043A
262 config HAS_FEATURE_ENHANCED_MSI
264 default y if ARCH_LS1043A
266 menu "Layerscape PPA"
268 bool "FSL Layerscape PPA firmware support"
269 depends on !ARMV8_PSCI
270 select ARMV8_SEC_FIRMWARE_SUPPORT
271 select SEC_FIRMWARE_ARMV8_PSCI
272 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
274 The FSL Primary Protected Application (PPA) is a software component
275 which is loaded during boot stage, and then remains resident in RAM
276 and runs in the TrustZone after boot.
279 config SPL_FSL_LS_PPA
280 bool "FSL Layerscape PPA firmware support for SPL build"
281 depends on !ARMV8_PSCI
282 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
283 select SEC_FIRMWARE_ARMV8_PSCI
284 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
286 The FSL Primary Protected Application (PPA) is a software component
287 which is loaded during boot stage, and then remains resident in RAM
288 and runs in the TrustZone after boot. This is to load PPA during SPL
289 stage instead of the RAM version of U-Boot. Once PPA is initialized,
290 the rest of U-Boot (including RAM version) runs at EL2.
292 prompt "FSL Layerscape PPA firmware loading-media select"
293 depends on FSL_LS_PPA
294 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
295 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
296 default SYS_LS_PPA_FW_IN_XIP
298 config SYS_LS_PPA_FW_IN_XIP
301 Say Y here if the PPA firmware locate at XIP flash, such
302 as NOR or QSPI flash.
304 config SYS_LS_PPA_FW_IN_MMC
305 bool "eMMC or SD Card"
307 Say Y here if the PPA firmware locate at eMMC/SD card.
309 config SYS_LS_PPA_FW_IN_NAND
312 Say Y here if the PPA firmware locate at NAND flash.
316 config LS_PPA_ESBC_HDR_SIZE
317 hex "Length of PPA ESBC header"
318 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
321 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
322 NAND to memory to validate PPA image.
326 config SYS_FSL_ERRATUM_A008997
327 bool "Workaround for USB PHY erratum A008997"
329 config SYS_FSL_ERRATUM_A009007
332 Workaround for USB PHY erratum A009007
334 config SYS_FSL_ERRATUM_A009008
335 bool "Workaround for USB PHY erratum A009008"
337 config SYS_FSL_ERRATUM_A009798
338 bool "Workaround for USB PHY erratum A009798"
340 config SYS_FSL_ERRATUM_A010315
341 bool "Workaround for PCIe erratum A010315"
343 config SYS_FSL_ERRATUM_A010539
344 bool "Workaround for PIN MUX erratum A010539"
347 int "Maximum number of CPUs permitted for Layerscape"
348 default 4 if ARCH_LS1043A
349 default 4 if ARCH_LS1046A
350 default 16 if ARCH_LS2080A
351 default 8 if ARCH_LS1088A
352 default 16 if ARCH_LX2160A
355 Set this number to the maximum number of possible CPUs in the SoC.
356 SoCs may have multiple clusters with each cluster may have multiple
357 ports. If some ports are reserved but higher ports are used for
358 cores, count the reserved ports. This will allocate enough memory
359 in spin table to properly handle all cores.
362 bool "Fan controller"
364 Enable the EMC2305 fan controller for configuration of fan
370 Enable Freescale Secure Boot feature
373 bool "Init the QSPI AHB bus"
375 The default setting for QSPI AHB bus just support 3bytes addressing.
376 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
377 bus for those flashes to support the full QSPI flash size.
379 config SYS_CCI400_OFFSET
380 hex "Offset for CCI400 base"
381 depends on SYS_FSL_HAS_CCI400
382 default 0x3090000 if ARCH_LS1088A
383 default 0x180000 if FSL_LSCH2
385 Offset for CCI400 base
386 CCI400 base addr = CCSRBAR + CCI400_OFFSET
388 config SYS_FSL_IFC_BANK_COUNT
389 int "Maximum banks of Integrated flash controller"
390 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
391 default 4 if ARCH_LS1043A
392 default 4 if ARCH_LS1046A
393 default 8 if ARCH_LS2080A || ARCH_LS1088A
395 config SYS_FSL_HAS_CCI400
398 config SYS_FSL_HAS_CCN504
401 config SYS_FSL_HAS_CCN508
404 config SYS_FSL_HAS_DP_DDR
407 config SYS_FSL_SRDS_1
410 config SYS_FSL_SRDS_2
413 config SYS_NXP_SRDS_3
416 config SYS_HAS_SERDES
428 config FSL_TZPC_BP147
432 menu "Layerscape clock tree configuration"
433 depends on FSL_LSCH2 || FSL_LSCH3
436 bool "Enable clock tree initialization"
439 config CLUSTER_CLK_FREQ
440 int "Reference clock of core cluster"
441 depends on ARCH_LS1012A
444 This number is the reference clock frequency of core PLL.
445 For most platforms, the core PLL and Platform PLL have the same
446 reference clock, but for some platforms, LS1012A for instance,
447 they are provided sepatately.
449 config SYS_FSL_PCLK_DIV
450 int "Platform clock divider"
451 default 1 if ARCH_LS1043A
452 default 1 if ARCH_LS1046A
453 default 1 if ARCH_LS1088A
456 This is the divider that is used to derive Platform clock from
457 Platform PLL, in another word:
458 Platform_clk = Platform_PLL_freq / this_divider
460 config SYS_FSL_DSPI_CLK_DIV
461 int "DSPI clock divider"
462 default 1 if ARCH_LS1043A
465 This is the divider that is used to derive DSPI clock from Platform
466 clock, in another word DSPI_clk = Platform_clk / this_divider.
468 config SYS_FSL_DUART_CLK_DIV
469 int "DUART clock divider"
470 default 1 if ARCH_LS1043A
471 default 4 if ARCH_LX2160A
474 This is the divider that is used to derive DUART clock from Platform
475 clock, in another word DUART_clk = Platform_clk / this_divider.
477 config SYS_FSL_I2C_CLK_DIV
478 int "I2C clock divider"
479 default 1 if ARCH_LS1043A
482 This is the divider that is used to derive I2C clock from Platform
483 clock, in another word I2C_clk = Platform_clk / this_divider.
485 config SYS_FSL_IFC_CLK_DIV
486 int "IFC clock divider"
487 default 1 if ARCH_LS1043A
490 This is the divider that is used to derive IFC clock from Platform
491 clock, in another word IFC_clk = Platform_clk / this_divider.
493 config SYS_FSL_LPUART_CLK_DIV
494 int "LPUART clock divider"
495 default 1 if ARCH_LS1043A
498 This is the divider that is used to derive LPUART clock from Platform
499 clock, in another word LPUART_clk = Platform_clk / this_divider.
501 config SYS_FSL_SDHC_CLK_DIV
502 int "SDHC clock divider"
503 default 1 if ARCH_LS1043A
504 default 1 if ARCH_LS1012A
507 This is the divider that is used to derive SDHC clock from Platform
508 clock, in another word SDHC_clk = Platform_clk / this_divider.
510 config SYS_FSL_QMAN_CLK_DIV
511 int "QMAN clock divider"
512 default 1 if ARCH_LS1043A
515 This is the divider that is used to derive QMAN clock from Platform
516 clock, in another word QMAN_clk = Platform_clk / this_divider.
522 Reserve memory from the top, tracked by gd->arch.resv_ram. This
523 reserved RAM can be used by special driver that resides in memory
524 after U-Boot exits. It's up to implementation to allocate and allow
525 access to this reserved memory. For example, the reserved RAM can
526 be at the high end of physical memory. The reserve RAM may be
527 excluded from memory bank(s) passed to OS, or marked as reserved.
532 Ethernet controller 1, this is connected to
533 MAC17 for LX2160A or to MAC3 for other SoCs
534 Provides DPAA2 capabilities
539 Ethernet controller 2, this is connected to
540 MAC18 for LX2160A or to MAC4 for other SoCs
541 Provides DPAA2 capabilities
543 config SYS_FSL_ERRATUM_A008336
546 config SYS_FSL_ERRATUM_A008514
549 config SYS_FSL_ERRATUM_A008585
552 config SYS_FSL_ERRATUM_A008850
555 config SYS_FSL_ERRATUM_A009203
558 config SYS_FSL_ERRATUM_A009635
561 config SYS_FSL_ERRATUM_A009660
564 config SYS_FSL_ERRATUM_A009929
568 config SYS_FSL_HAS_RGMII
570 depends on SYS_FSL_EC1 || SYS_FSL_EC2
573 config SYS_MC_RSV_MEM_ALIGN
574 hex "Management Complex reserved memory alignment"
576 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
578 Reserved memory needs to be aligned for MC to use. Default value
582 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
584 config HAS_FSL_XHCI_USB
586 default y if ARCH_LS1043A || ARCH_LS1046A
588 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
589 pins, select it when the pins are assigned to USB.
592 bool "Support for booting from TFA"
595 Enabling this will make a U-Boot binary that is capable of being