4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1
20 select SYS_I2C_MXC_I2C2
25 select ARMV8_SET_SMPEN
28 select SYS_FSL_HAS_CCI400
33 select SYS_FSL_DDR_VER_50
34 select SYS_FSL_HAS_DDR3
35 select SYS_FSL_HAS_DDR4
36 select SYS_FSL_HAS_SEC
37 select SYS_FSL_SEC_COMPAT_5
40 select ARCH_EARLY_INIT_R
41 select BOARD_EARLY_INIT_F
43 select SYS_FSL_ERRATUM_A008997
44 select SYS_FSL_ERRATUM_A009007
45 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
46 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
48 select SYS_FSL_ERRATUM_A050382
53 select ARMV8_SET_SMPEN
54 select ARM_ERRATA_855873 if !TFABOOT
61 select SYS_FSL_DDR_VER_50
62 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
63 select SYS_FSL_ERRATUM_A008997
64 select SYS_FSL_ERRATUM_A009007
65 select SYS_FSL_ERRATUM_A009008
66 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
67 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
68 select SYS_FSL_ERRATUM_A009798
69 select SYS_FSL_ERRATUM_A009929
70 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
71 select SYS_FSL_ERRATUM_A010315
72 select SYS_FSL_ERRATUM_A010539
73 select SYS_FSL_HAS_DDR3
74 select SYS_FSL_HAS_DDR4
75 select ARCH_EARLY_INIT_R
76 select BOARD_EARLY_INIT_F
78 select SYS_I2C_MXC_I2C1
79 select SYS_I2C_MXC_I2C2
80 select SYS_I2C_MXC_I2C3
81 select SYS_I2C_MXC_I2C4
86 select ARMV8_SET_SMPEN
93 select SYS_FSL_DDR_VER_50
94 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
95 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
96 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
97 select SYS_FSL_ERRATUM_A008997
98 select SYS_FSL_ERRATUM_A009007
99 select SYS_FSL_ERRATUM_A009008
100 select SYS_FSL_ERRATUM_A009798
101 select SYS_FSL_ERRATUM_A009801
102 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
103 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
104 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
105 select SYS_FSL_ERRATUM_A010539
106 select SYS_FSL_HAS_DDR4
107 select SYS_FSL_SRDS_2
108 select ARCH_EARLY_INIT_R
109 select BOARD_EARLY_INIT_F
111 select SYS_I2C_MXC_I2C1
112 select SYS_I2C_MXC_I2C2
113 select SYS_I2C_MXC_I2C3
114 select SYS_I2C_MXC_I2C4
120 select ARMV8_SET_SMPEN
121 select ARM_ERRATA_855873 if !TFABOOT
122 select FSL_LAYERSCAPE
124 select SYS_FSL_SRDS_1
125 select SYS_HAS_SERDES
127 select SYS_FSL_DDR_LE
128 select SYS_FSL_DDR_VER_50
131 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
132 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
133 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
134 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
135 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
136 select SYS_FSL_ERRATUM_A009007
137 select SYS_FSL_HAS_CCI400
138 select SYS_FSL_HAS_DDR4
139 select SYS_FSL_HAS_RGMII
140 select SYS_FSL_HAS_SEC
141 select SYS_FSL_SEC_COMPAT_5
142 select SYS_FSL_SEC_LE
143 select SYS_FSL_SRDS_1
144 select SYS_FSL_SRDS_2
147 select FSL_TZPC_BP147
148 select ARCH_EARLY_INIT_R
149 select BOARD_EARLY_INIT_F
151 select SYS_I2C_MXC_I2C1 if !TFABOOT
152 select SYS_I2C_MXC_I2C2 if !TFABOOT
153 select SYS_I2C_MXC_I2C3 if !TFABOOT
154 select SYS_I2C_MXC_I2C4 if !TFABOOT
160 select ARMV8_SET_SMPEN
161 select ARM_ERRATA_826974
162 select ARM_ERRATA_828024
163 select ARM_ERRATA_829520
164 select ARM_ERRATA_833471
165 select FSL_LAYERSCAPE
167 select SYS_FSL_SRDS_1
168 select SYS_HAS_SERDES
170 select SYS_FSL_DDR_LE
171 select SYS_FSL_DDR_VER_50
172 select SYS_FSL_HAS_CCN504
173 select SYS_FSL_HAS_DP_DDR
174 select SYS_FSL_HAS_SEC
175 select SYS_FSL_HAS_DDR4
176 select SYS_FSL_SEC_COMPAT_5
177 select SYS_FSL_SEC_LE
178 select SYS_FSL_SRDS_2
182 select FSL_TZPC_BP147
183 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
184 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
185 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
186 select SYS_FSL_ERRATUM_A008585
187 select SYS_FSL_ERRATUM_A008997
188 select SYS_FSL_ERRATUM_A009007
189 select SYS_FSL_ERRATUM_A009008
190 select SYS_FSL_ERRATUM_A009635
191 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
192 select SYS_FSL_ERRATUM_A009798
193 select SYS_FSL_ERRATUM_A009801
194 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
195 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
196 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
197 select SYS_FSL_ERRATUM_A009203
198 select ARCH_EARLY_INIT_R
199 select BOARD_EARLY_INIT_F
201 select SYS_I2C_MXC_I2C1 if !TFABOOT
202 select SYS_I2C_MXC_I2C2 if !TFABOOT
203 select SYS_I2C_MXC_I2C3 if !TFABOOT
204 select SYS_I2C_MXC_I2C4 if !TFABOOT
205 imply DISTRO_DEFAULTS
210 select ARMV8_SET_SMPEN
213 select SYS_HAS_SERDES
214 select SYS_FSL_SRDS_1
215 select SYS_FSL_SRDS_2
216 select SYS_NXP_SRDS_3
218 select SYS_FSL_DDR_LE
219 select SYS_FSL_DDR_VER_50
222 select SYS_FSL_ERRATUM_A050106
223 select SYS_FSL_HAS_RGMII
224 select SYS_FSL_HAS_SEC
225 select SYS_FSL_HAS_CCN508
226 select SYS_FSL_HAS_DDR4
227 select SYS_FSL_SEC_COMPAT_5
228 select SYS_FSL_SEC_LE
229 select ARCH_EARLY_INIT_R
230 select BOARD_EARLY_INIT_F
232 imply DISTRO_DEFAULTS
239 select SYS_FSL_HAS_CCI400
240 select SYS_FSL_HAS_SEC
241 select SYS_FSL_SEC_COMPAT_5
242 select SYS_FSL_SEC_BE
250 menu "Layerscape architecture"
251 depends on FSL_LSCH2 || FSL_LSCH3
253 config FSL_LAYERSCAPE
256 config FSL_PCIE_COMPAT
257 string "PCIe compatible of Kernel DT"
258 depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
259 default "fsl,ls1012a-pcie" if ARCH_LS1012A
260 default "fsl,ls1028a-pcie" if ARCH_LS1028A
261 default "fsl,ls1043a-pcie" if ARCH_LS1043A
262 default "fsl,ls1046a-pcie" if ARCH_LS1046A
263 default "fsl,ls2080a-pcie" if ARCH_LS2080A
264 default "fsl,ls1088a-pcie" if ARCH_LS1088A
265 default "fsl,lx2160a-pcie" if ARCH_LX2160A
267 This compatible is used to find pci controller node in Kernel DT
270 config HAS_FEATURE_GIC64K_ALIGN
272 default y if ARCH_LS1043A
274 config HAS_FEATURE_ENHANCED_MSI
276 default y if ARCH_LS1043A
278 menu "Layerscape PPA"
280 bool "FSL Layerscape PPA firmware support"
281 depends on !ARMV8_PSCI
282 select ARMV8_SEC_FIRMWARE_SUPPORT
283 select SEC_FIRMWARE_ARMV8_PSCI
284 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
286 The FSL Primary Protected Application (PPA) is a software component
287 which is loaded during boot stage, and then remains resident in RAM
288 and runs in the TrustZone after boot.
291 config SPL_FSL_LS_PPA
292 bool "FSL Layerscape PPA firmware support for SPL build"
293 depends on !ARMV8_PSCI
294 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
295 select SEC_FIRMWARE_ARMV8_PSCI
296 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
298 The FSL Primary Protected Application (PPA) is a software component
299 which is loaded during boot stage, and then remains resident in RAM
300 and runs in the TrustZone after boot. This is to load PPA during SPL
301 stage instead of the RAM version of U-Boot. Once PPA is initialized,
302 the rest of U-Boot (including RAM version) runs at EL2.
304 prompt "FSL Layerscape PPA firmware loading-media select"
305 depends on FSL_LS_PPA
306 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
307 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
308 default SYS_LS_PPA_FW_IN_XIP
310 config SYS_LS_PPA_FW_IN_XIP
313 Say Y here if the PPA firmware locate at XIP flash, such
314 as NOR or QSPI flash.
316 config SYS_LS_PPA_FW_IN_MMC
317 bool "eMMC or SD Card"
319 Say Y here if the PPA firmware locate at eMMC/SD card.
321 config SYS_LS_PPA_FW_IN_NAND
324 Say Y here if the PPA firmware locate at NAND flash.
328 config LS_PPA_ESBC_HDR_SIZE
329 hex "Length of PPA ESBC header"
330 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
333 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
334 NAND to memory to validate PPA image.
338 config SYS_FSL_ERRATUM_A008997
339 bool "Workaround for USB PHY erratum A008997"
341 config SYS_FSL_ERRATUM_A009007
344 Workaround for USB PHY erratum A009007
346 config SYS_FSL_ERRATUM_A009008
347 bool "Workaround for USB PHY erratum A009008"
349 config SYS_FSL_ERRATUM_A009798
350 bool "Workaround for USB PHY erratum A009798"
352 config SYS_FSL_ERRATUM_A050106
353 bool "Workaround for USB PHY erratum A050106"
355 USB3.0 Receiver needs to enable fixed equalization
356 for each of PHY instances in an SOC. This is similar
357 to erratum A-009007, but this one is for LX2160A,
358 and the register value is different.
360 config SYS_FSL_ERRATUM_A010315
361 bool "Workaround for PCIe erratum A010315"
363 config SYS_FSL_ERRATUM_A010539
364 bool "Workaround for PIN MUX erratum A010539"
367 int "Maximum number of CPUs permitted for Layerscape"
368 default 2 if ARCH_LS1028A
369 default 4 if ARCH_LS1043A
370 default 4 if ARCH_LS1046A
371 default 16 if ARCH_LS2080A
372 default 8 if ARCH_LS1088A
373 default 16 if ARCH_LX2160A
376 Set this number to the maximum number of possible CPUs in the SoC.
377 SoCs may have multiple clusters with each cluster may have multiple
378 ports. If some ports are reserved but higher ports are used for
379 cores, count the reserved ports. This will allocate enough memory
380 in spin table to properly handle all cores.
383 bool "Fan controller"
385 Enable the EMC2305 fan controller for configuration of fan
391 Enable Freescale Secure Boot feature
394 bool "Init the QSPI AHB bus"
396 The default setting for QSPI AHB bus just support 3bytes addressing.
397 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
398 bus for those flashes to support the full QSPI flash size.
400 config SYS_CCI400_OFFSET
401 hex "Offset for CCI400 base"
402 depends on SYS_FSL_HAS_CCI400
403 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
404 default 0x180000 if FSL_LSCH2
406 Offset for CCI400 base
407 CCI400 base addr = CCSRBAR + CCI400_OFFSET
409 config SYS_FSL_IFC_BANK_COUNT
410 int "Maximum banks of Integrated flash controller"
411 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
412 default 4 if ARCH_LS1043A
413 default 4 if ARCH_LS1046A
414 default 8 if ARCH_LS2080A || ARCH_LS1088A
416 config SYS_FSL_HAS_CCI400
419 config SYS_FSL_HAS_CCN504
422 config SYS_FSL_HAS_CCN508
425 config SYS_FSL_HAS_DP_DDR
428 config SYS_FSL_SRDS_1
431 config SYS_FSL_SRDS_2
434 config SYS_NXP_SRDS_3
437 config SYS_HAS_SERDES
449 config FSL_TZPC_BP147
453 menu "Layerscape clock tree configuration"
454 depends on FSL_LSCH2 || FSL_LSCH3
457 bool "Enable clock tree initialization"
460 config CLUSTER_CLK_FREQ
461 int "Reference clock of core cluster"
462 depends on ARCH_LS1012A
465 This number is the reference clock frequency of core PLL.
466 For most platforms, the core PLL and Platform PLL have the same
467 reference clock, but for some platforms, LS1012A for instance,
468 they are provided sepatately.
470 config SYS_FSL_PCLK_DIV
471 int "Platform clock divider"
472 default 1 if ARCH_LS1028A
473 default 1 if ARCH_LS1043A
474 default 1 if ARCH_LS1046A
475 default 1 if ARCH_LS1088A
478 This is the divider that is used to derive Platform clock from
479 Platform PLL, in another word:
480 Platform_clk = Platform_PLL_freq / this_divider
482 config SYS_FSL_DSPI_CLK_DIV
483 int "DSPI clock divider"
484 default 1 if ARCH_LS1043A
487 This is the divider that is used to derive DSPI clock from Platform
488 clock, in another word DSPI_clk = Platform_clk / this_divider.
490 config SYS_FSL_DUART_CLK_DIV
491 int "DUART clock divider"
492 default 1 if ARCH_LS1043A
493 default 4 if ARCH_LX2160A
496 This is the divider that is used to derive DUART clock from Platform
497 clock, in another word DUART_clk = Platform_clk / this_divider.
499 config SYS_FSL_I2C_CLK_DIV
500 int "I2C clock divider"
501 default 1 if ARCH_LS1043A
502 default 4 if ARCH_LS1012A
503 default 4 if ARCH_LS1028A
504 default 8 if ARCH_LX2160A
505 default 8 if ARCH_LS1088A
508 This is the divider that is used to derive I2C clock from Platform
509 clock, in another word I2C_clk = Platform_clk / this_divider.
511 config SYS_FSL_IFC_CLK_DIV
512 int "IFC clock divider"
513 default 1 if ARCH_LS1043A
514 default 4 if ARCH_LS1012A
515 default 4 if ARCH_LS1028A
516 default 8 if ARCH_LX2160A
517 default 8 if ARCH_LS1088A
520 This is the divider that is used to derive IFC clock from Platform
521 clock, in another word IFC_clk = Platform_clk / this_divider.
523 config SYS_FSL_LPUART_CLK_DIV
524 int "LPUART clock divider"
525 default 1 if ARCH_LS1043A
528 This is the divider that is used to derive LPUART clock from Platform
529 clock, in another word LPUART_clk = Platform_clk / this_divider.
531 config SYS_FSL_SDHC_CLK_DIV
532 int "SDHC clock divider"
533 default 1 if ARCH_LS1043A
534 default 1 if ARCH_LS1012A
537 This is the divider that is used to derive SDHC clock from Platform
538 clock, in another word SDHC_clk = Platform_clk / this_divider.
540 config SYS_FSL_QMAN_CLK_DIV
541 int "QMAN clock divider"
542 default 1 if ARCH_LS1043A
545 This is the divider that is used to derive QMAN clock from Platform
546 clock, in another word QMAN_clk = Platform_clk / this_divider.
552 Reserve memory from the top, tracked by gd->arch.resv_ram. This
553 reserved RAM can be used by special driver that resides in memory
554 after U-Boot exits. It's up to implementation to allocate and allow
555 access to this reserved memory. For example, the reserved RAM can
556 be at the high end of physical memory. The reserve RAM may be
557 excluded from memory bank(s) passed to OS, or marked as reserved.
562 Ethernet controller 1, this is connected to
563 MAC17 for LX2160A or to MAC3 for other SoCs
564 Provides DPAA2 capabilities
569 Ethernet controller 2, this is connected to
570 MAC18 for LX2160A or to MAC4 for other SoCs
571 Provides DPAA2 capabilities
573 config SYS_FSL_ERRATUM_A008336
576 config SYS_FSL_ERRATUM_A008514
579 config SYS_FSL_ERRATUM_A008585
582 config SYS_FSL_ERRATUM_A008850
585 config SYS_FSL_ERRATUM_A009203
588 config SYS_FSL_ERRATUM_A009635
591 config SYS_FSL_ERRATUM_A009660
594 config SYS_FSL_ERRATUM_A009929
597 config SYS_FSL_ERRATUM_A050382
600 config SYS_FSL_HAS_RGMII
602 depends on SYS_FSL_EC1 || SYS_FSL_EC2
605 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
607 config HAS_FSL_XHCI_USB
609 default y if ARCH_LS1043A || ARCH_LS1046A
611 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
612 pins, select it when the pins are assigned to USB.