7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F
32 select ARMV8_SET_SMPEN
36 select SYS_FSL_DDR_VER_50
37 select SYS_FSL_ERRATUM_A008336
38 select SYS_FSL_ERRATUM_A008511
39 select SYS_FSL_ERRATUM_A009801
40 select SYS_FSL_ERRATUM_A009803
41 select SYS_FSL_ERRATUM_A009942
42 select SYS_FSL_ERRATUM_A010165
43 select SYS_FSL_ERRATUM_A010539
44 select SYS_FSL_HAS_DDR4
46 select ARCH_EARLY_INIT_R
47 select BOARD_EARLY_INIT_F
51 select ARMV8_SET_SMPEN
55 select SYS_FSL_DDR_VER_50
56 select SYS_FSL_HAS_DP_DDR
57 select SYS_FSL_HAS_SEC
58 select SYS_FSL_HAS_DDR4
59 select SYS_FSL_SEC_COMPAT_5
62 select SYS_FSL_ERRATUM_A008336
63 select SYS_FSL_ERRATUM_A008511
64 select SYS_FSL_ERRATUM_A008514
65 select SYS_FSL_ERRATUM_A008585
66 select SYS_FSL_ERRATUM_A009635
67 select SYS_FSL_ERRATUM_A009663
68 select SYS_FSL_ERRATUM_A009801
69 select SYS_FSL_ERRATUM_A009803
70 select SYS_FSL_ERRATUM_A009942
71 select SYS_FSL_ERRATUM_A010165
72 select ARCH_EARLY_INIT_R
73 select BOARD_EARLY_INIT_F
77 select SYS_FSL_HAS_SEC
78 select SYS_FSL_SEC_COMPAT_5
88 menu "Layerscape architecture"
89 depends on FSL_LSCH2 || FSL_LSCH3
91 config FSL_PCIE_COMPAT
92 string "PCIe compatible of Kernel DT"
93 depends on PCIE_LAYERSCAPE
94 default "fsl,ls1012a-pcie" if ARCH_LS1012A
95 default "fsl,ls1043a-pcie" if ARCH_LS1043A
96 default "fsl,ls1046a-pcie" if ARCH_LS1046A
97 default "fsl,ls2080a-pcie" if ARCH_LS2080A
99 This compatible is used to find pci controller node in Kernel DT
102 config HAS_FEATURE_GIC64K_ALIGN
104 default y if ARCH_LS1043A
106 config HAS_FEATURE_ENHANCED_MSI
108 default y if ARCH_LS1043A
110 menu "Layerscape PPA"
112 bool "FSL Layerscape PPA firmware support"
113 depends on !ARMV8_PSCI
114 select ARMV8_SEC_FIRMWARE_SUPPORT
115 select SEC_FIRMWARE_ARMV8_PSCI
116 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
118 The FSL Primary Protected Application (PPA) is a software component
119 which is loaded during boot stage, and then remains resident in RAM
120 and runs in the TrustZone after boot.
123 prompt "FSL Layerscape PPA firmware loading-media select"
124 depends on FSL_LS_PPA
125 default SYS_LS_PPA_FW_IN_XIP
127 config SYS_LS_PPA_FW_IN_XIP
130 Say Y here if the PPA firmware locate at XIP flash, such
131 as NOR or QSPI flash.
135 config SYS_LS_PPA_FW_ADDR
136 hex "Address of PPA firmware loading from"
137 depends on FSL_LS_PPA
138 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
139 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
141 If the PPA firmware locate at XIP flash, such as NOR or
142 QSPI flash, this address is a directly memory-mapped.
143 If it is in a serial accessed flash, such as NAND and SD
144 card, it is a byte offset.
147 config SYS_FSL_ERRATUM_A010315
148 bool "Workaround for PCIe erratum A010315"
150 config SYS_FSL_ERRATUM_A010539
151 bool "Workaround for PIN MUX erratum A010539"
154 int "Maximum number of CPUs permitted for Layerscape"
155 default 4 if ARCH_LS1043A
156 default 4 if ARCH_LS1046A
157 default 16 if ARCH_LS2080A
160 Set this number to the maximum number of possible CPUs in the SoC.
161 SoCs may have multiple clusters with each cluster may have multiple
162 ports. If some ports are reserved but higher ports are used for
163 cores, count the reserved ports. This will allocate enough memory
164 in spin table to properly handle all cores.
169 Enable Freescale Secure Boot feature
172 bool "Init the QSPI AHB bus"
174 The default setting for QSPI AHB bus just support 3bytes addressing.
175 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
176 bus for those flashes to support the full QSPI flash size.
178 config SYS_FSL_IFC_BANK_COUNT
179 int "Maximum banks of Integrated flash controller"
180 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
181 default 4 if ARCH_LS1043A
182 default 4 if ARCH_LS1046A
183 default 8 if ARCH_LS2080A
185 config SYS_FSL_HAS_DP_DDR
188 config SYS_FSL_SRDS_1
191 config SYS_FSL_SRDS_2
194 config SYS_HAS_SERDES
199 menu "Layerscape clock tree configuration"
200 depends on FSL_LSCH2 || FSL_LSCH3
203 bool "Enable clock tree initialization"
206 config CLUSTER_CLK_FREQ
207 int "Reference clock of core cluster"
208 depends on ARCH_LS1012A
211 This number is the reference clock frequency of core PLL.
212 For most platforms, the core PLL and Platform PLL have the same
213 reference clock, but for some platforms, LS1012A for instance,
214 they are provided sepatately.
216 config SYS_FSL_PCLK_DIV
217 int "Platform clock divider"
218 default 1 if ARCH_LS1043A
219 default 1 if ARCH_LS1046A
222 This is the divider that is used to derive Platform clock from
223 Platform PLL, in another word:
224 Platform_clk = Platform_PLL_freq / this_divider
226 config SYS_FSL_DSPI_CLK_DIV
227 int "DSPI clock divider"
228 default 1 if ARCH_LS1043A
231 This is the divider that is used to derive DSPI clock from Platform
232 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
234 config SYS_FSL_DUART_CLK_DIV
235 int "DUART clock divider"
236 default 1 if ARCH_LS1043A
239 This is the divider that is used to derive DUART clock from Platform
240 clock, in another word DUART_clk = Platform_clk / this_divider.
242 config SYS_FSL_I2C_CLK_DIV
243 int "I2C clock divider"
244 default 1 if ARCH_LS1043A
247 This is the divider that is used to derive I2C clock from Platform
248 clock, in another word I2C_clk = Platform_clk / this_divider.
250 config SYS_FSL_IFC_CLK_DIV
251 int "IFC clock divider"
252 default 1 if ARCH_LS1043A
255 This is the divider that is used to derive IFC clock from Platform
256 clock, in another word IFC_clk = Platform_clk / this_divider.
258 config SYS_FSL_LPUART_CLK_DIV
259 int "LPUART clock divider"
260 default 1 if ARCH_LS1043A
263 This is the divider that is used to derive LPUART clock from Platform
264 clock, in another word LPUART_clk = Platform_clk / this_divider.
266 config SYS_FSL_SDHC_CLK_DIV
267 int "SDHC clock divider"
268 default 1 if ARCH_LS1043A
269 default 1 if ARCH_LS1012A
272 This is the divider that is used to derive SDHC clock from Platform
273 clock, in another word SDHC_clk = Platform_clk / this_divider.
276 config SYS_FSL_ERRATUM_A008336
279 config SYS_FSL_ERRATUM_A008514
282 config SYS_FSL_ERRATUM_A008585
285 config SYS_FSL_ERRATUM_A008850
288 config SYS_FSL_ERRATUM_A009635
291 config SYS_FSL_ERRATUM_A009660
294 config SYS_FSL_ERRATUM_A009929