4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1 if !DM_I2C
20 select SYS_I2C_MXC_I2C2 if !DM_I2C
25 select ARMV8_SET_SMPEN
29 select SYS_FSL_HAS_CCI400
34 select SYS_FSL_DDR_VER_50
35 select SYS_FSL_HAS_DDR3
36 select SYS_FSL_HAS_DDR4
37 select SYS_FSL_HAS_SEC
38 select SYS_FSL_SEC_COMPAT_5
41 select ARCH_EARLY_INIT_R
42 select BOARD_EARLY_INIT_F
44 select SYS_FSL_ERRATUM_A008997
45 select SYS_FSL_ERRATUM_A009007
46 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
48 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
49 select SYS_FSL_ERRATUM_A050382
50 select SYS_FSL_ERRATUM_A011334
51 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
52 select RESV_RAM if GIC_V3_ITS
57 select ARMV8_SET_SMPEN
58 select ARM_ERRATA_855873 if !TFABOOT
65 select SYS_FSL_DDR_VER_50
66 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
67 select SYS_FSL_ERRATUM_A008997
68 select SYS_FSL_ERRATUM_A009007
69 select SYS_FSL_ERRATUM_A009008
70 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
71 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
72 select SYS_FSL_ERRATUM_A009798
73 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
74 select SYS_FSL_ERRATUM_A010315
75 select SYS_FSL_ERRATUM_A010539
76 select SYS_FSL_HAS_DDR3
77 select SYS_FSL_HAS_DDR4
78 select ARCH_EARLY_INIT_R
79 select BOARD_EARLY_INIT_F
81 select SYS_I2C_MXC_I2C1 if !DM_I2C
82 select SYS_I2C_MXC_I2C2 if !DM_I2C
83 select SYS_I2C_MXC_I2C3 if !DM_I2C
84 select SYS_I2C_MXC_I2C4 if !DM_I2C
89 select ARMV8_SET_SMPEN
96 select SYS_FSL_DDR_VER_50
97 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
98 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
99 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
100 select SYS_FSL_ERRATUM_A008997
101 select SYS_FSL_ERRATUM_A009007
102 select SYS_FSL_ERRATUM_A009008
103 select SYS_FSL_ERRATUM_A009798
104 select SYS_FSL_ERRATUM_A009801
105 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
106 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
107 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
108 select SYS_FSL_ERRATUM_A010539
109 select SYS_FSL_HAS_DDR4
110 select SYS_FSL_SRDS_2
111 select ARCH_EARLY_INIT_R
112 select BOARD_EARLY_INIT_F
114 select SYS_I2C_MXC_I2C1 if !DM_I2C
115 select SYS_I2C_MXC_I2C2 if !DM_I2C
116 select SYS_I2C_MXC_I2C3 if !DM_I2C
117 select SYS_I2C_MXC_I2C4 if !DM_I2C
123 select ARMV8_SET_SMPEN
124 select ARM_ERRATA_855873 if !TFABOOT
125 select FSL_LAYERSCAPE
127 select SYS_FSL_SRDS_1
128 select SYS_HAS_SERDES
130 select SYS_FSL_DDR_LE
131 select SYS_FSL_DDR_VER_50
134 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
135 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
136 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
137 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
138 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
139 select SYS_FSL_ERRATUM_A009007
140 select SYS_FSL_HAS_CCI400
141 select SYS_FSL_HAS_DDR4
142 select SYS_FSL_HAS_RGMII
143 select SYS_FSL_HAS_SEC
144 select SYS_FSL_SEC_COMPAT_5
145 select SYS_FSL_SEC_LE
146 select SYS_FSL_SRDS_1
147 select SYS_FSL_SRDS_2
150 select FSL_TZPC_BP147
151 select ARCH_EARLY_INIT_R
152 select BOARD_EARLY_INIT_F
154 select SYS_I2C_MXC_I2C1 if !TFABOOT
155 select SYS_I2C_MXC_I2C2 if !TFABOOT
156 select SYS_I2C_MXC_I2C3 if !TFABOOT
157 select SYS_I2C_MXC_I2C4 if !TFABOOT
158 select RESV_RAM if GIC_V3_ITS
164 select ARMV8_SET_SMPEN
165 select ARM_ERRATA_826974
166 select ARM_ERRATA_828024
167 select ARM_ERRATA_829520
168 select ARM_ERRATA_833471
169 select FSL_LAYERSCAPE
171 select SYS_FSL_SRDS_1
172 select SYS_HAS_SERDES
174 select SYS_FSL_DDR_LE
175 select SYS_FSL_DDR_VER_50
176 select SYS_FSL_HAS_CCN504
177 select SYS_FSL_HAS_DP_DDR
178 select SYS_FSL_HAS_SEC
179 select SYS_FSL_HAS_DDR4
180 select SYS_FSL_SEC_COMPAT_5
181 select SYS_FSL_SEC_LE
182 select SYS_FSL_SRDS_2
186 select FSL_TZPC_BP147
187 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
188 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
189 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
190 select SYS_FSL_ERRATUM_A008585
191 select SYS_FSL_ERRATUM_A008997
192 select SYS_FSL_ERRATUM_A009007
193 select SYS_FSL_ERRATUM_A009008
194 select SYS_FSL_ERRATUM_A009635
195 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
196 select SYS_FSL_ERRATUM_A009798
197 select SYS_FSL_ERRATUM_A009801
198 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
199 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
200 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
201 select SYS_FSL_ERRATUM_A009203
202 select ARCH_EARLY_INIT_R
203 select BOARD_EARLY_INIT_F
205 select SYS_I2C_MXC_I2C1 if !TFABOOT
206 select SYS_I2C_MXC_I2C2 if !TFABOOT
207 select SYS_I2C_MXC_I2C3 if !TFABOOT
208 select SYS_I2C_MXC_I2C4 if !TFABOOT
209 select RESV_RAM if GIC_V3_ITS
210 imply DISTRO_DEFAULTS
215 select ARMV8_SET_SMPEN
218 select SYS_HAS_SERDES
219 select SYS_FSL_SRDS_1
220 select SYS_FSL_SRDS_2
222 select SYS_FSL_DDR_LE
223 select SYS_FSL_DDR_VER_50
226 select SYS_FSL_ERRATUM_A050106
227 select SYS_FSL_HAS_RGMII
228 select SYS_FSL_HAS_SEC
229 select SYS_FSL_HAS_CCN508
230 select SYS_FSL_HAS_DDR4
231 select SYS_FSL_SEC_COMPAT_5
232 select SYS_FSL_SEC_LE
233 select ARCH_EARLY_INIT_R
234 select BOARD_EARLY_INIT_F
236 select RESV_RAM if GIC_V3_ITS
237 imply DISTRO_DEFAULTS
244 select ARMV8_SET_SMPEN
247 select SYS_HAS_SERDES
248 select SYS_FSL_SRDS_1
249 select SYS_FSL_SRDS_2
250 select SYS_NXP_SRDS_3
252 select SYS_FSL_DDR_LE
253 select SYS_FSL_DDR_VER_50
256 select SYS_FSL_ERRATUM_A050106
257 select SYS_FSL_HAS_RGMII
258 select SYS_FSL_HAS_SEC
259 select SYS_FSL_HAS_CCN508
260 select SYS_FSL_HAS_DDR4
261 select SYS_FSL_SEC_COMPAT_5
262 select SYS_FSL_SEC_LE
263 select ARCH_EARLY_INIT_R
264 select BOARD_EARLY_INIT_F
266 select RESV_RAM if GIC_V3_ITS
267 imply DISTRO_DEFAULTS
274 select SYS_FSL_HAS_CCI400
275 select SYS_FSL_HAS_SEC
276 select SYS_FSL_SEC_COMPAT_5
277 select SYS_FSL_SEC_BE
280 select ARCH_MISC_INIT
286 menu "Layerscape architecture"
287 depends on FSL_LSCH2 || FSL_LSCH3
289 config FSL_LAYERSCAPE
292 config HAS_FEATURE_GIC64K_ALIGN
294 default y if ARCH_LS1043A
296 config HAS_FEATURE_ENHANCED_MSI
298 default y if ARCH_LS1043A
300 menu "Layerscape PPA"
302 bool "FSL Layerscape PPA firmware support"
303 depends on !ARMV8_PSCI
304 select ARMV8_SEC_FIRMWARE_SUPPORT
305 select SEC_FIRMWARE_ARMV8_PSCI
306 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
308 The FSL Primary Protected Application (PPA) is a software component
309 which is loaded during boot stage, and then remains resident in RAM
310 and runs in the TrustZone after boot.
313 config SPL_FSL_LS_PPA
314 bool "FSL Layerscape PPA firmware support for SPL build"
315 depends on !ARMV8_PSCI
316 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
317 select SEC_FIRMWARE_ARMV8_PSCI
318 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
320 The FSL Primary Protected Application (PPA) is a software component
321 which is loaded during boot stage, and then remains resident in RAM
322 and runs in the TrustZone after boot. This is to load PPA during SPL
323 stage instead of the RAM version of U-Boot. Once PPA is initialized,
324 the rest of U-Boot (including RAM version) runs at EL2.
326 prompt "FSL Layerscape PPA firmware loading-media select"
327 depends on FSL_LS_PPA
328 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
329 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
330 default SYS_LS_PPA_FW_IN_XIP
332 config SYS_LS_PPA_FW_IN_XIP
335 Say Y here if the PPA firmware locate at XIP flash, such
336 as NOR or QSPI flash.
338 config SYS_LS_PPA_FW_IN_MMC
339 bool "eMMC or SD Card"
341 Say Y here if the PPA firmware locate at eMMC/SD card.
343 config SYS_LS_PPA_FW_IN_NAND
346 Say Y here if the PPA firmware locate at NAND flash.
350 config LS_PPA_ESBC_HDR_SIZE
351 hex "Length of PPA ESBC header"
352 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
355 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
356 NAND to memory to validate PPA image.
360 config SYS_FSL_ERRATUM_A008997
361 bool "Workaround for USB PHY erratum A008997"
363 config SYS_FSL_ERRATUM_A009007
366 Workaround for USB PHY erratum A009007
368 config SYS_FSL_ERRATUM_A009008
369 bool "Workaround for USB PHY erratum A009008"
371 config SYS_FSL_ERRATUM_A009798
372 bool "Workaround for USB PHY erratum A009798"
374 config SYS_FSL_ERRATUM_A050106
375 bool "Workaround for USB PHY erratum A050106"
377 USB3.0 Receiver needs to enable fixed equalization
378 for each of PHY instances in an SOC. This is similar
379 to erratum A-009007, but this one is for LX2160A and LX2162A,
380 and the register value is different.
382 config SYS_FSL_ERRATUM_A010315
383 bool "Workaround for PCIe erratum A010315"
385 config SYS_FSL_ERRATUM_A010539
386 bool "Workaround for PIN MUX erratum A010539"
389 int "Maximum number of CPUs permitted for Layerscape"
390 default 2 if ARCH_LS1028A
391 default 4 if ARCH_LS1043A
392 default 4 if ARCH_LS1046A
393 default 16 if ARCH_LS2080A
394 default 8 if ARCH_LS1088A
395 default 16 if ARCH_LX2160A
396 default 16 if ARCH_LX2162A
399 Set this number to the maximum number of possible CPUs in the SoC.
400 SoCs may have multiple clusters with each cluster may have multiple
401 ports. If some ports are reserved but higher ports are used for
402 cores, count the reserved ports. This will allocate enough memory
403 in spin table to properly handle all cores.
406 bool "Fan controller"
408 Enable the EMC2305 fan controller for configuration of fan
414 Enable Freescale Secure Boot feature
417 bool "Init the QSPI AHB bus"
419 The default setting for QSPI AHB bus just support 3bytes addressing.
420 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
421 bus for those flashes to support the full QSPI flash size.
423 config FSPI_AHB_EN_4BYTE
424 bool "Enable 4-byte Fast Read command for AHB mode"
427 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
428 But some FlexSPI flash sizes are up to 64MBytes.
429 This flag enables fast read command for AHB mode and modifies required
430 LUT to support full FlexSPI flash.
432 config SYS_CCI400_OFFSET
433 hex "Offset for CCI400 base"
434 depends on SYS_FSL_HAS_CCI400
435 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
436 default 0x180000 if FSL_LSCH2
438 Offset for CCI400 base
439 CCI400 base addr = CCSRBAR + CCI400_OFFSET
441 config SYS_FSL_IFC_BANK_COUNT
442 int "Maximum banks of Integrated flash controller"
443 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
444 default 4 if ARCH_LS1043A
445 default 4 if ARCH_LS1046A
446 default 8 if ARCH_LS2080A || ARCH_LS1088A
448 config SYS_FSL_HAS_CCI400
451 config SYS_FSL_HAS_CCN504
454 config SYS_FSL_HAS_CCN508
457 config SYS_FSL_HAS_DP_DDR
460 config SYS_FSL_SRDS_1
463 config SYS_FSL_SRDS_2
466 config SYS_NXP_SRDS_3
469 config SYS_HAS_SERDES
481 config FSL_TZPC_BP147
485 menu "Layerscape clock tree configuration"
486 depends on FSL_LSCH2 || FSL_LSCH3
489 bool "Enable clock tree initialization"
492 config CLUSTER_CLK_FREQ
493 int "Reference clock of core cluster"
494 depends on ARCH_LS1012A
497 This number is the reference clock frequency of core PLL.
498 For most platforms, the core PLL and Platform PLL have the same
499 reference clock, but for some platforms, LS1012A for instance,
500 they are provided sepatately.
502 config SYS_FSL_PCLK_DIV
503 int "Platform clock divider"
504 default 1 if ARCH_LS1028A
505 default 1 if ARCH_LS1043A
506 default 1 if ARCH_LS1046A
507 default 1 if ARCH_LS1088A
510 This is the divider that is used to derive Platform clock from
511 Platform PLL, in another word:
512 Platform_clk = Platform_PLL_freq / this_divider
514 config SYS_FSL_DSPI_CLK_DIV
515 int "DSPI clock divider"
516 default 1 if ARCH_LS1043A
519 This is the divider that is used to derive DSPI clock from Platform
520 clock, in another word DSPI_clk = Platform_clk / this_divider.
522 config SYS_FSL_DUART_CLK_DIV
523 int "DUART clock divider"
524 default 1 if ARCH_LS1043A
525 default 4 if ARCH_LX2160A
526 default 4 if ARCH_LX2162A
529 This is the divider that is used to derive DUART clock from Platform
530 clock, in another word DUART_clk = Platform_clk / this_divider.
532 config SYS_FSL_I2C_CLK_DIV
533 int "I2C clock divider"
534 default 1 if ARCH_LS1043A
535 default 4 if ARCH_LS1012A
536 default 4 if ARCH_LS1028A
537 default 8 if ARCH_LX2160A
538 default 8 if ARCH_LX2162A
539 default 8 if ARCH_LS1088A
542 This is the divider that is used to derive I2C clock from Platform
543 clock, in another word I2C_clk = Platform_clk / this_divider.
545 config SYS_FSL_IFC_CLK_DIV
546 int "IFC clock divider"
547 default 1 if ARCH_LS1043A
548 default 4 if ARCH_LS1012A
549 default 4 if ARCH_LS1028A
550 default 8 if ARCH_LX2160A
551 default 8 if ARCH_LX2162A
552 default 8 if ARCH_LS1088A
555 This is the divider that is used to derive IFC clock from Platform
556 clock, in another word IFC_clk = Platform_clk / this_divider.
558 config SYS_FSL_LPUART_CLK_DIV
559 int "LPUART clock divider"
560 default 1 if ARCH_LS1043A
563 This is the divider that is used to derive LPUART clock from Platform
564 clock, in another word LPUART_clk = Platform_clk / this_divider.
566 config SYS_FSL_SDHC_CLK_DIV
567 int "SDHC clock divider"
568 default 1 if ARCH_LS1043A
569 default 1 if ARCH_LS1012A
572 This is the divider that is used to derive SDHC clock from Platform
573 clock, in another word SDHC_clk = Platform_clk / this_divider.
575 config SYS_FSL_QMAN_CLK_DIV
576 int "QMAN clock divider"
577 default 1 if ARCH_LS1043A
580 This is the divider that is used to derive QMAN clock from Platform
581 clock, in another word QMAN_clk = Platform_clk / this_divider.
587 Reserve memory from the top, tracked by gd->arch.resv_ram. This
588 reserved RAM can be used by special driver that resides in memory
589 after U-Boot exits. It's up to implementation to allocate and allow
590 access to this reserved memory. For example, the reserved RAM can
591 be at the high end of physical memory. The reserve RAM may be
592 excluded from memory bank(s) passed to OS, or marked as reserved.
597 Ethernet controller 1, this is connected to
598 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
599 Provides DPAA2 capabilities
604 Ethernet controller 2, this is connected to
605 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
606 Provides DPAA2 capabilities
608 config SYS_FSL_ERRATUM_A008336
611 config SYS_FSL_ERRATUM_A008514
614 config SYS_FSL_ERRATUM_A008585
617 config SYS_FSL_ERRATUM_A008850
620 config SYS_FSL_ERRATUM_A009203
623 config SYS_FSL_ERRATUM_A009635
626 config SYS_FSL_ERRATUM_A009660
629 config SYS_FSL_ERRATUM_A050382
632 config SYS_FSL_HAS_RGMII
634 depends on SYS_FSL_EC1 || SYS_FSL_EC2
637 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
639 config HAS_FSL_XHCI_USB
641 default y if ARCH_LS1043A || ARCH_LS1046A
643 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
644 pins, select it when the pins are assigned to USB.
646 config SYS_FSL_BOOTROM_BASE
651 config SYS_FSL_BOOTROM_SIZE