7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F
34 select ARMV8_SET_SMPEN
38 select SYS_FSL_DDR_VER_50
39 select SYS_FSL_ERRATUM_A008336
40 select SYS_FSL_ERRATUM_A008511
41 select SYS_FSL_ERRATUM_A008850
42 select SYS_FSL_ERRATUM_A009801
43 select SYS_FSL_ERRATUM_A009803
44 select SYS_FSL_ERRATUM_A009942
45 select SYS_FSL_ERRATUM_A010165
46 select SYS_FSL_ERRATUM_A010539
47 select SYS_FSL_HAS_DDR4
49 select ARCH_EARLY_INIT_R
50 select BOARD_EARLY_INIT_F
55 select ARMV8_SET_SMPEN
56 select ARM_ERRATA_826974
57 select ARM_ERRATA_828024
58 select ARM_ERRATA_829520
59 select ARM_ERRATA_833471
63 select SYS_FSL_DDR_VER_50
64 select SYS_FSL_HAS_CCN504
65 select SYS_FSL_HAS_DP_DDR
66 select SYS_FSL_HAS_SEC
67 select SYS_FSL_HAS_DDR4
68 select SYS_FSL_SEC_COMPAT_5
73 select SYS_FSL_ERRATUM_A008336
74 select SYS_FSL_ERRATUM_A008511
75 select SYS_FSL_ERRATUM_A008514
76 select SYS_FSL_ERRATUM_A008585
77 select SYS_FSL_ERRATUM_A009635
78 select SYS_FSL_ERRATUM_A009663
79 select SYS_FSL_ERRATUM_A009801
80 select SYS_FSL_ERRATUM_A009803
81 select SYS_FSL_ERRATUM_A009942
82 select SYS_FSL_ERRATUM_A010165
83 select SYS_FSL_ERRATUM_A009203
84 select ARCH_EARLY_INIT_R
85 select BOARD_EARLY_INIT_F
89 select SYS_FSL_HAS_CCI400
90 select SYS_FSL_HAS_SEC
91 select SYS_FSL_SEC_COMPAT_5
102 bool "Management Complex network"
103 depends on ARCH_LS2080A
107 Enable Management Complex (MC) network
109 menu "Layerscape architecture"
110 depends on FSL_LSCH2 || FSL_LSCH3
112 config FSL_PCIE_COMPAT
113 string "PCIe compatible of Kernel DT"
114 depends on PCIE_LAYERSCAPE
115 default "fsl,ls1012a-pcie" if ARCH_LS1012A
116 default "fsl,ls1043a-pcie" if ARCH_LS1043A
117 default "fsl,ls1046a-pcie" if ARCH_LS1046A
118 default "fsl,ls2080a-pcie" if ARCH_LS2080A
120 This compatible is used to find pci controller node in Kernel DT
123 config HAS_FEATURE_GIC64K_ALIGN
125 default y if ARCH_LS1043A
127 config HAS_FEATURE_ENHANCED_MSI
129 default y if ARCH_LS1043A
131 menu "Layerscape PPA"
133 bool "FSL Layerscape PPA firmware support"
134 depends on !ARMV8_PSCI
135 select ARMV8_SEC_FIRMWARE_SUPPORT
136 select SEC_FIRMWARE_ARMV8_PSCI
137 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
139 The FSL Primary Protected Application (PPA) is a software component
140 which is loaded during boot stage, and then remains resident in RAM
141 and runs in the TrustZone after boot.
144 config SPL_FSL_LS_PPA
145 bool "FSL Layerscape PPA firmware support for SPL build"
146 depends on !ARMV8_PSCI
147 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
148 select SEC_FIRMWARE_ARMV8_PSCI
149 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
151 The FSL Primary Protected Application (PPA) is a software component
152 which is loaded during boot stage, and then remains resident in RAM
153 and runs in the TrustZone after boot. This is to load PPA during SPL
154 stage instead of the RAM version of U-Boot. Once PPA is initialized,
155 the rest of U-Boot (including RAM version) runs at EL2.
157 prompt "FSL Layerscape PPA firmware loading-media select"
158 depends on FSL_LS_PPA
159 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
160 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
161 default SYS_LS_PPA_FW_IN_XIP
163 config SYS_LS_PPA_FW_IN_XIP
166 Say Y here if the PPA firmware locate at XIP flash, such
167 as NOR or QSPI flash.
169 config SYS_LS_PPA_FW_IN_MMC
170 bool "eMMC or SD Card"
172 Say Y here if the PPA firmware locate at eMMC/SD card.
174 config SYS_LS_PPA_FW_IN_NAND
177 Say Y here if the PPA firmware locate at NAND flash.
181 config SYS_LS_PPA_FW_ADDR
182 hex "Address of PPA firmware loading from"
183 depends on FSL_LS_PPA
184 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
185 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
186 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
187 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
188 default 0x400000 if SYS_LS_PPA_FW_IN_MMC
189 default 0x400000 if SYS_LS_PPA_FW_IN_NAND
192 If the PPA firmware locate at XIP flash, such as NOR or
193 QSPI flash, this address is a directly memory-mapped.
194 If it is in a serial accessed flash, such as NAND and SD
195 card, it is a byte offset.
197 config SYS_LS_PPA_ESBC_ADDR
198 hex "hdr address of PPA firmware loading from"
199 depends on FSL_LS_PPA && CHAIN_OF_TRUST
200 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
201 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
202 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
203 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
204 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
205 default 0x680000 if SYS_LS_PPA_FW_IN_MMC
206 default 0x680000 if SYS_LS_PPA_FW_IN_NAND
208 If the PPA header firmware locate at XIP flash, such as NOR or
209 QSPI flash, this address is a directly memory-mapped.
210 If it is in a serial accessed flash, such as NAND and SD
211 card, it is a byte offset.
213 config LS_PPA_ESBC_HDR_SIZE
214 hex "Length of PPA ESBC header"
215 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
218 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
219 NAND to memory to validate PPA image.
223 config SYS_FSL_ERRATUM_A010315
224 bool "Workaround for PCIe erratum A010315"
226 config SYS_FSL_ERRATUM_A010539
227 bool "Workaround for PIN MUX erratum A010539"
230 int "Maximum number of CPUs permitted for Layerscape"
231 default 4 if ARCH_LS1043A
232 default 4 if ARCH_LS1046A
233 default 16 if ARCH_LS2080A
236 Set this number to the maximum number of possible CPUs in the SoC.
237 SoCs may have multiple clusters with each cluster may have multiple
238 ports. If some ports are reserved but higher ports are used for
239 cores, count the reserved ports. This will allocate enough memory
240 in spin table to properly handle all cores.
245 Enable Freescale Secure Boot feature
248 bool "Init the QSPI AHB bus"
250 The default setting for QSPI AHB bus just support 3bytes addressing.
251 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
252 bus for those flashes to support the full QSPI flash size.
254 config SYS_CCI400_OFFSET
255 hex "Offset for CCI400 base"
256 depends on SYS_FSL_HAS_CCI400
257 default 0x3090000 if ARCH_LS1088A
258 default 0x180000 if FSL_LSCH2
260 Offset for CCI400 base
261 CCI400 base addr = CCSRBAR + CCI400_OFFSET
263 config SYS_FSL_IFC_BANK_COUNT
264 int "Maximum banks of Integrated flash controller"
265 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
266 default 4 if ARCH_LS1043A
267 default 4 if ARCH_LS1046A
268 default 8 if ARCH_LS2080A
270 config SYS_FSL_HAS_CCI400
273 config SYS_FSL_HAS_CCN504
276 config SYS_FSL_HAS_DP_DDR
279 config SYS_FSL_SRDS_1
282 config SYS_FSL_SRDS_2
285 config SYS_HAS_SERDES
296 menu "Layerscape clock tree configuration"
297 depends on FSL_LSCH2 || FSL_LSCH3
300 bool "Enable clock tree initialization"
303 config CLUSTER_CLK_FREQ
304 int "Reference clock of core cluster"
305 depends on ARCH_LS1012A
308 This number is the reference clock frequency of core PLL.
309 For most platforms, the core PLL and Platform PLL have the same
310 reference clock, but for some platforms, LS1012A for instance,
311 they are provided sepatately.
313 config SYS_FSL_PCLK_DIV
314 int "Platform clock divider"
315 default 1 if ARCH_LS1043A
316 default 1 if ARCH_LS1046A
319 This is the divider that is used to derive Platform clock from
320 Platform PLL, in another word:
321 Platform_clk = Platform_PLL_freq / this_divider
323 config SYS_FSL_DSPI_CLK_DIV
324 int "DSPI clock divider"
325 default 1 if ARCH_LS1043A
328 This is the divider that is used to derive DSPI clock from Platform
329 clock, in another word DSPI_clk = Platform_clk / this_divider.
331 config SYS_FSL_DUART_CLK_DIV
332 int "DUART clock divider"
333 default 1 if ARCH_LS1043A
336 This is the divider that is used to derive DUART clock from Platform
337 clock, in another word DUART_clk = Platform_clk / this_divider.
339 config SYS_FSL_I2C_CLK_DIV
340 int "I2C clock divider"
341 default 1 if ARCH_LS1043A
344 This is the divider that is used to derive I2C clock from Platform
345 clock, in another word I2C_clk = Platform_clk / this_divider.
347 config SYS_FSL_IFC_CLK_DIV
348 int "IFC clock divider"
349 default 1 if ARCH_LS1043A
352 This is the divider that is used to derive IFC clock from Platform
353 clock, in another word IFC_clk = Platform_clk / this_divider.
355 config SYS_FSL_LPUART_CLK_DIV
356 int "LPUART clock divider"
357 default 1 if ARCH_LS1043A
360 This is the divider that is used to derive LPUART clock from Platform
361 clock, in another word LPUART_clk = Platform_clk / this_divider.
363 config SYS_FSL_SDHC_CLK_DIV
364 int "SDHC clock divider"
365 default 1 if ARCH_LS1043A
366 default 1 if ARCH_LS1012A
369 This is the divider that is used to derive SDHC clock from Platform
370 clock, in another word SDHC_clk = Platform_clk / this_divider.
376 Reserve memory from the top, tracked by gd->arch.resv_ram. This
377 reserved RAM can be used by special driver that resides in memory
378 after U-Boot exits. It's up to implementation to allocate and allow
379 access to this reserved memory. For example, the reserved RAM can
380 be at the high end of physical memory. The reserve RAM may be
381 excluded from memory bank(s) passed to OS, or marked as reserved.
383 config SYS_FSL_ERRATUM_A008336
386 config SYS_FSL_ERRATUM_A008514
389 config SYS_FSL_ERRATUM_A008585
392 config SYS_FSL_ERRATUM_A008850
395 config SYS_FSL_ERRATUM_A009203
398 config SYS_FSL_ERRATUM_A009635
401 config SYS_FSL_ERRATUM_A009660
404 config SYS_FSL_ERRATUM_A009929
407 config SYS_MC_RSV_MEM_ALIGN
408 hex "Management Complex reserved memory alignment"
412 Reserved memory needs to be aligned for MC to use. Default value
416 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A