6 select SYS_FSL_ERRATUM_A010315
13 select SYS_FSL_DDR_VER_50
14 select SYS_FSL_ERRATUM_A010315
15 select SYS_FSL_ERRATUM_A010539
16 select SYS_FSL_HAS_DDR3
17 select SYS_FSL_HAS_DDR4
24 select SYS_FSL_DDR_VER_50
25 select SYS_FSL_ERRATUM_A010539
26 select SYS_FSL_HAS_DDR4
34 select SYS_FSL_DDR_VER_50
35 select SYS_FSL_HAS_DP_DDR
36 select SYS_FSL_HAS_SEC
37 select SYS_FSL_HAS_DDR4
38 select SYS_FSL_SEC_COMPAT_5
44 select SYS_FSL_HAS_SEC
45 select SYS_FSL_SEC_COMPAT_5
55 menu "Layerscape architecture"
56 depends on FSL_LSCH2 || FSL_LSCH3
60 bool "FSL Layerscape PPA firmware support"
61 depends on !ARMV8_PSCI
62 depends on ARCH_LS1043A || ARCH_LS1046A
63 select FSL_PPA_ARMV8_PSCI
65 The FSL Primary Protected Application (PPA) is a software component
66 which is loaded during boot stage, and then remains resident in RAM
67 and runs in the TrustZone after boot.
70 config FSL_PPA_ARMV8_PSCI
71 bool "PSCI implementation in PPA firmware"
74 This config enables the ARMv8 PSCI implementation in PPA firmware.
75 This is a private PSCI implementation and different from those
76 implemented under the common ARMv8 PSCI framework.
79 config SYS_FSL_ERRATUM_A010315
80 bool "Workaround for PCIe erratum A010315"
82 config SYS_FSL_ERRATUM_A010539
83 bool "Workaround for PIN MUX erratum A010539"
86 int "Maximum number of CPUs permitted for Layerscape"
87 default 4 if ARCH_LS1043A
88 default 4 if ARCH_LS1046A
89 default 16 if ARCH_LS2080A
92 Set this number to the maximum number of possible CPUs in the SoC.
93 SoCs may have multiple clusters with each cluster may have multiple
94 ports. If some ports are reserved but higher ports are used for
95 cores, count the reserved ports. This will allocate enough memory
96 in spin table to properly handle all cores.
98 config NUM_DDR_CONTROLLERS
99 int "Maximum DDR controllers"
100 default 3 if ARCH_LS2080A
106 Enable Freescale Secure Boot feature
109 bool "Init the QSPI AHB bus"
111 The default setting for QSPI AHB bus just support 3bytes addressing.
112 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
113 bus for those flashes to support the full QSPI flash size.
115 config SYS_FSL_IFC_BANK_COUNT
116 int "Maximum banks of Integrated flash controller"
117 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
118 default 4 if ARCH_LS1043A
119 default 4 if ARCH_LS1046A
120 default 8 if ARCH_LS2080A
122 config SYS_FSL_HAS_DP_DDR
125 config SYS_FSL_SRDS_1
128 config SYS_FSL_SRDS_2
131 config SYS_HAS_SERDES