4 select ARM_ERRATA_855873 if !TFABOOT
8 select SKIP_LOWLEVEL_INIT
13 select SYS_FSL_ERRATUM_A010315
14 select SYS_FSL_ERRATUM_A009798
15 select SYS_FSL_ERRATUM_A008997
16 select SYS_FSL_ERRATUM_A009007
17 select SYS_FSL_ERRATUM_A009008
18 select ARCH_EARLY_INIT_R
19 select BOARD_EARLY_INIT_F
21 select SYS_I2C_MXC_I2C1 if !DM_I2C
22 select SYS_I2C_MXC_I2C2 if !DM_I2C
27 select ARMV8_SET_SMPEN
32 select SYS_FSL_HAS_CCI400
37 select SYS_FSL_DDR_VER_50
38 select SYS_FSL_HAS_DDR3
39 select SYS_FSL_HAS_DDR4
40 select SYS_FSL_HAS_SEC
41 select SYS_FSL_SEC_COMPAT_5
44 select ARCH_EARLY_INIT_R
45 select BOARD_EARLY_INIT_F
47 select SYS_FSL_ERRATUM_A008997
48 select SYS_FSL_ERRATUM_A009007
49 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
50 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
51 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
52 select SYS_FSL_ERRATUM_A050382
53 select SYS_FSL_ERRATUM_A011334
54 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
55 select RESV_RAM if GIC_V3_ITS
60 select ARMV8_SET_SMPEN
61 select ARM_ERRATA_855873 if !TFABOOT
65 select HAS_FSL_XHCI_USB if USB_HOST
66 select SKIP_LOWLEVEL_INIT
71 select SYS_FSL_DDR_VER_50
72 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
73 select SYS_FSL_ERRATUM_A008997
74 select SYS_FSL_ERRATUM_A009007
75 select SYS_FSL_ERRATUM_A009008
76 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
77 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
78 select SYS_FSL_ERRATUM_A009798
79 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
80 select SYS_FSL_ERRATUM_A010315
81 select SYS_FSL_ERRATUM_A010539
82 select SYS_FSL_HAS_DDR3
83 select SYS_FSL_HAS_DDR4
84 select ARCH_EARLY_INIT_R
85 select BOARD_EARLY_INIT_F
87 select SYS_I2C_MXC_I2C1 if !DM_I2C
88 select SYS_I2C_MXC_I2C2 if !DM_I2C
89 select SYS_I2C_MXC_I2C3 if !DM_I2C
90 select SYS_I2C_MXC_I2C4 if !DM_I2C
96 select ARMV8_SET_SMPEN
100 select HAS_FSL_XHCI_USB if USB_HOST
101 select SKIP_LOWLEVEL_INIT
102 select SYS_FSL_SRDS_1
103 select SYS_HAS_SERDES
105 select SYS_FSL_DDR_BE
106 select SYS_FSL_DDR_VER_50
107 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
108 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
109 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
110 select SYS_FSL_ERRATUM_A008997
111 select SYS_FSL_ERRATUM_A009007
112 select SYS_FSL_ERRATUM_A009008
113 select SYS_FSL_ERRATUM_A009798
114 select SYS_FSL_ERRATUM_A009801
115 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
116 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
117 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
118 select SYS_FSL_ERRATUM_A010539
119 select SYS_FSL_HAS_DDR4
120 select SYS_FSL_SRDS_2
121 select ARCH_EARLY_INIT_R
122 select BOARD_EARLY_INIT_F
124 select SYS_I2C_MXC_I2C1 if !DM_I2C
125 select SYS_I2C_MXC_I2C2 if !DM_I2C
126 select SYS_I2C_MXC_I2C3 if !DM_I2C
127 select SYS_I2C_MXC_I2C4 if !DM_I2C
131 imply SPL_SYS_I2C_LEGACY
135 select ARMV8_SET_SMPEN
136 select ARM_ERRATA_855873 if !TFABOOT
137 select FSL_LAYERSCAPE
140 select SKIP_LOWLEVEL_INIT
141 select SYS_FSL_SRDS_1
142 select SYS_HAS_SERDES
144 select SYS_FSL_DDR_LE
145 select SYS_FSL_DDR_VER_50
148 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
149 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
150 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
151 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
152 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
153 select SYS_FSL_ERRATUM_A009007
154 select SYS_FSL_HAS_CCI400
155 select SYS_FSL_HAS_DDR4
156 select SYS_FSL_HAS_RGMII
157 select SYS_FSL_HAS_SEC
158 select SYS_FSL_SEC_COMPAT_5
159 select SYS_FSL_SEC_LE
160 select SYS_FSL_SRDS_1
161 select SYS_FSL_SRDS_2
164 select FSL_TZPC_BP147
165 select ARCH_EARLY_INIT_R
166 select BOARD_EARLY_INIT_F
168 select SYS_I2C_MXC_I2C1 if !TFABOOT
169 select SYS_I2C_MXC_I2C2 if !TFABOOT
170 select SYS_I2C_MXC_I2C3 if !TFABOOT
171 select SYS_I2C_MXC_I2C4 if !TFABOOT
172 select RESV_RAM if GIC_V3_ITS
175 imply SPL_SYS_I2C_LEGACY
180 select ARMV8_SET_SMPEN
181 select ARM_ERRATA_826974
182 select ARM_ERRATA_828024
183 select ARM_ERRATA_829520
184 select ARM_ERRATA_833471
185 select FSL_LAYERSCAPE
188 select SKIP_LOWLEVEL_INIT
189 select SYS_FSL_SRDS_1
190 select SYS_HAS_SERDES
192 select SYS_FSL_DDR_LE
193 select SYS_FSL_DDR_VER_50
194 select SYS_FSL_HAS_CCN504
195 select SYS_FSL_HAS_DP_DDR
196 select SYS_FSL_HAS_SEC
197 select SYS_FSL_HAS_DDR4
198 select SYS_FSL_SEC_COMPAT_5
199 select SYS_FSL_SEC_LE
200 select SYS_FSL_SRDS_2
204 select FSL_TZPC_BP147
205 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
206 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
207 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
208 select SYS_FSL_ERRATUM_A008585
209 select SYS_FSL_ERRATUM_A008997
210 select SYS_FSL_ERRATUM_A009007
211 select SYS_FSL_ERRATUM_A009008
212 select SYS_FSL_ERRATUM_A009635
213 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
214 select SYS_FSL_ERRATUM_A009798
215 select SYS_FSL_ERRATUM_A009801
216 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
217 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
218 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
219 select SYS_FSL_ERRATUM_A009203
220 select ARCH_EARLY_INIT_R
221 select BOARD_EARLY_INIT_F
223 select SYS_I2C_MXC_I2C1 if !TFABOOT
224 select SYS_I2C_MXC_I2C2 if !TFABOOT
225 select SYS_I2C_MXC_I2C3 if !TFABOOT
226 select SYS_I2C_MXC_I2C4 if !TFABOOT
227 select RESV_RAM if GIC_V3_ITS
228 imply DISTRO_DEFAULTS
231 imply SPL_SYS_I2C_LEGACY
235 select ARMV8_SET_SMPEN
239 select SYS_HAS_SERDES
240 select SYS_FSL_SRDS_1
241 select SYS_FSL_SRDS_2
243 select SYS_FSL_DDR_LE
244 select SYS_FSL_DDR_VER_50
247 select SYS_FSL_ERRATUM_A050204
248 select SYS_FSL_ERRATUM_A011334
249 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
250 select SYS_FSL_HAS_RGMII
251 select SYS_FSL_HAS_SEC
252 select SYS_FSL_HAS_CCN508
253 select SYS_FSL_HAS_DDR4
254 select SYS_FSL_SEC_COMPAT_5
255 select SYS_FSL_SEC_LE
256 select ARCH_EARLY_INIT_R
257 select BOARD_EARLY_INIT_F
259 select RESV_RAM if GIC_V3_ITS
260 imply DISTRO_DEFAULTS
264 imply SPL_SYS_I2C_LEGACY
268 select ARMV8_SET_SMPEN
271 select HAS_FSL_XHCI_USB if USB_HOST
273 select SYS_HAS_SERDES
274 select SYS_FSL_SRDS_1
275 select SYS_FSL_SRDS_2
276 select SYS_NXP_SRDS_3
278 select SYS_FSL_DDR_LE
279 select SYS_FSL_DDR_VER_50
282 select SYS_FSL_ERRATUM_A050204
283 select SYS_FSL_ERRATUM_A011334
284 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
285 select SYS_FSL_HAS_RGMII
286 select SYS_FSL_HAS_SEC
287 select SYS_FSL_HAS_CCN508
288 select SYS_FSL_HAS_DDR4
289 select SYS_FSL_SEC_COMPAT_5
290 select SYS_FSL_SEC_LE
291 select ARCH_EARLY_INIT_R
292 select BOARD_EARLY_INIT_F
294 select RESV_RAM if GIC_V3_ITS
295 imply DISTRO_DEFAULTS
300 imply SPL_SYS_I2C_LEGACY
304 select SKIP_LOWLEVEL_INIT
305 select SYS_FSL_HAS_CCI400
306 select SYS_FSL_HAS_SEC
307 select SYS_FSL_SEC_COMPAT_5
308 select SYS_FSL_SEC_BE
311 select ARCH_MISC_INIT
317 menu "Layerscape architecture"
318 depends on FSL_LSCH2 || FSL_LSCH3
320 config FSL_LAYERSCAPE
323 config HAS_FEATURE_GIC64K_ALIGN
325 default y if ARCH_LS1043A
327 config HAS_FEATURE_ENHANCED_MSI
329 default y if ARCH_LS1043A
331 menu "Layerscape PPA"
333 bool "FSL Layerscape PPA firmware support"
334 depends on !ARMV8_PSCI
335 select ARMV8_SEC_FIRMWARE_SUPPORT
336 select SEC_FIRMWARE_ARMV8_PSCI
337 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
339 The FSL Primary Protected Application (PPA) is a software component
340 which is loaded during boot stage, and then remains resident in RAM
341 and runs in the TrustZone after boot.
344 config SPL_FSL_LS_PPA
345 bool "FSL Layerscape PPA firmware support for SPL build"
346 depends on !ARMV8_PSCI
347 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
348 select SEC_FIRMWARE_ARMV8_PSCI
349 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
351 The FSL Primary Protected Application (PPA) is a software component
352 which is loaded during boot stage, and then remains resident in RAM
353 and runs in the TrustZone after boot. This is to load PPA during SPL
354 stage instead of the RAM version of U-Boot. Once PPA is initialized,
355 the rest of U-Boot (including RAM version) runs at EL2.
357 prompt "FSL Layerscape PPA firmware loading-media select"
358 depends on FSL_LS_PPA
359 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
360 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
361 default SYS_LS_PPA_FW_IN_XIP
363 config SYS_LS_PPA_FW_IN_XIP
366 Say Y here if the PPA firmware locate at XIP flash, such
367 as NOR or QSPI flash.
369 config SYS_LS_PPA_FW_IN_MMC
370 bool "eMMC or SD Card"
372 Say Y here if the PPA firmware locate at eMMC/SD card.
374 config SYS_LS_PPA_FW_IN_NAND
377 Say Y here if the PPA firmware locate at NAND flash.
381 config LS_PPA_ESBC_HDR_SIZE
382 hex "Length of PPA ESBC header"
383 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
386 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
387 NAND to memory to validate PPA image.
391 config SYS_FSL_ERRATUM_A008997
392 bool "Workaround for USB PHY erratum A008997"
394 config SYS_FSL_ERRATUM_A009007
397 Workaround for USB PHY erratum A009007
399 config SYS_FSL_ERRATUM_A009008
400 bool "Workaround for USB PHY erratum A009008"
402 config SYS_FSL_ERRATUM_A009798
403 bool "Workaround for USB PHY erratum A009798"
405 config SYS_FSL_ERRATUM_A050204
406 bool "Workaround for USB PHY erratum A050204"
408 USB3.0 Receiver needs to enable fixed equalization
409 for each of PHY instances in an SOC. This is similar
410 to erratum A-009007, but this one is for LX2160A and LX2162A,
411 and the register value is different.
413 config SYS_FSL_ERRATUM_A010315
414 bool "Workaround for PCIe erratum A010315"
416 config SYS_FSL_ERRATUM_A010539
417 bool "Workaround for PIN MUX erratum A010539"
420 int "Maximum number of CPUs permitted for Layerscape"
421 default 2 if ARCH_LS1028A
422 default 4 if ARCH_LS1043A
423 default 4 if ARCH_LS1046A
424 default 16 if ARCH_LS2080A
425 default 8 if ARCH_LS1088A
426 default 16 if ARCH_LX2160A
427 default 16 if ARCH_LX2162A
430 Set this number to the maximum number of possible CPUs in the SoC.
431 SoCs may have multiple clusters with each cluster may have multiple
432 ports. If some ports are reserved but higher ports are used for
433 cores, count the reserved ports. This will allocate enough memory
434 in spin table to properly handle all cores.
437 bool "Fan controller"
439 Enable the EMC2305 fan controller for configuration of fan
445 Enable Freescale Secure Boot feature
448 bool "Init the QSPI AHB bus"
450 The default setting for QSPI AHB bus just support 3bytes addressing.
451 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
452 bus for those flashes to support the full QSPI flash size.
454 config FSPI_AHB_EN_4BYTE
455 bool "Enable 4-byte Fast Read command for AHB mode"
458 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
459 But some FlexSPI flash sizes are up to 64MBytes.
460 This flag enables fast read command for AHB mode and modifies required
461 LUT to support full FlexSPI flash.
463 config SYS_CCI400_OFFSET
464 hex "Offset for CCI400 base"
465 depends on SYS_FSL_HAS_CCI400
466 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
467 default 0x180000 if FSL_LSCH2
469 Offset for CCI400 base
470 CCI400 base addr = CCSRBAR + CCI400_OFFSET
472 config SYS_FSL_IFC_BANK_COUNT
473 int "Maximum banks of Integrated flash controller"
474 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
475 default 4 if ARCH_LS1043A
476 default 4 if ARCH_LS1046A
477 default 8 if ARCH_LS2080A || ARCH_LS1088A
479 config SYS_FSL_HAS_CCI400
482 config SYS_FSL_HAS_CCN504
485 config SYS_FSL_HAS_CCN508
488 config SYS_FSL_HAS_DP_DDR
491 config SYS_FSL_SRDS_1
494 config SYS_FSL_SRDS_2
497 config SYS_NXP_SRDS_3
500 config SYS_HAS_SERDES
512 config FSL_TZPC_BP147
516 menu "Layerscape clock tree configuration"
517 depends on FSL_LSCH2 || FSL_LSCH3
520 bool "Enable clock tree initialization"
523 config CLUSTER_CLK_FREQ
524 int "Reference clock of core cluster"
525 depends on ARCH_LS1012A
528 This number is the reference clock frequency of core PLL.
529 For most platforms, the core PLL and Platform PLL have the same
530 reference clock, but for some platforms, LS1012A for instance,
531 they are provided sepatately.
533 config SYS_FSL_PCLK_DIV
534 int "Platform clock divider"
535 default 1 if ARCH_LS1028A
536 default 1 if ARCH_LS1043A
537 default 1 if ARCH_LS1046A
538 default 1 if ARCH_LS1088A
541 This is the divider that is used to derive Platform clock from
542 Platform PLL, in another word:
543 Platform_clk = Platform_PLL_freq / this_divider
545 config SYS_FSL_DSPI_CLK_DIV
546 int "DSPI clock divider"
547 default 1 if ARCH_LS1043A
550 This is the divider that is used to derive DSPI clock from Platform
551 clock, in another word DSPI_clk = Platform_clk / this_divider.
553 config SYS_FSL_DUART_CLK_DIV
554 int "DUART clock divider"
555 default 1 if ARCH_LS1043A
556 default 4 if ARCH_LX2160A
557 default 4 if ARCH_LX2162A
560 This is the divider that is used to derive DUART clock from Platform
561 clock, in another word DUART_clk = Platform_clk / this_divider.
563 config SYS_FSL_I2C_CLK_DIV
564 int "I2C clock divider"
565 default 1 if ARCH_LS1043A
566 default 4 if ARCH_LS1012A
567 default 4 if ARCH_LS1028A
568 default 8 if ARCH_LX2160A
569 default 8 if ARCH_LX2162A
570 default 8 if ARCH_LS1088A
573 This is the divider that is used to derive I2C clock from Platform
574 clock, in another word I2C_clk = Platform_clk / this_divider.
576 config SYS_FSL_IFC_CLK_DIV
577 int "IFC clock divider"
578 default 1 if ARCH_LS1043A
579 default 4 if ARCH_LS1012A
580 default 4 if ARCH_LS1028A
581 default 8 if ARCH_LX2160A
582 default 8 if ARCH_LX2162A
583 default 8 if ARCH_LS1088A
586 This is the divider that is used to derive IFC clock from Platform
587 clock, in another word IFC_clk = Platform_clk / this_divider.
589 config SYS_FSL_LPUART_CLK_DIV
590 int "LPUART clock divider"
591 default 1 if ARCH_LS1043A
594 This is the divider that is used to derive LPUART clock from Platform
595 clock, in another word LPUART_clk = Platform_clk / this_divider.
597 config SYS_FSL_SDHC_CLK_DIV
598 int "SDHC clock divider"
599 default 1 if ARCH_LS1043A
600 default 1 if ARCH_LS1012A
603 This is the divider that is used to derive SDHC clock from Platform
604 clock, in another word SDHC_clk = Platform_clk / this_divider.
606 config SYS_FSL_QMAN_CLK_DIV
607 int "QMAN clock divider"
608 default 1 if ARCH_LS1043A
611 This is the divider that is used to derive QMAN clock from Platform
612 clock, in another word QMAN_clk = Platform_clk / this_divider.
618 Reserve memory from the top, tracked by gd->arch.resv_ram. This
619 reserved RAM can be used by special driver that resides in memory
620 after U-Boot exits. It's up to implementation to allocate and allow
621 access to this reserved memory. For example, the reserved RAM can
622 be at the high end of physical memory. The reserve RAM may be
623 excluded from memory bank(s) passed to OS, or marked as reserved.
628 Ethernet controller 1, this is connected to
629 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
630 Provides DPAA2 capabilities
635 Ethernet controller 2, this is connected to
636 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
637 Provides DPAA2 capabilities
639 config SYS_FSL_ERRATUM_A008336
642 config SYS_FSL_ERRATUM_A008514
645 config SYS_FSL_ERRATUM_A008585
648 config SYS_FSL_ERRATUM_A008850
651 config SYS_FSL_ERRATUM_A009203
654 config SYS_FSL_ERRATUM_A009635
657 config SYS_FSL_ERRATUM_A009660
660 config SYS_FSL_ERRATUM_A050382
663 config SYS_FSL_HAS_RGMII
665 depends on SYS_FSL_EC1 || SYS_FSL_EC2
668 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
670 config HAS_FSL_XHCI_USB
673 For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
674 pins, select it when the pins are assigned to USB.
676 config SYS_FSL_BOOTROM_BASE
681 config SYS_FSL_BOOTROM_SIZE