4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1
20 select SYS_I2C_MXC_I2C2
25 select ARMV8_SET_SMPEN
28 select SYS_FSL_HAS_CCI400
33 select SYS_FSL_DDR_VER_50
34 select SYS_FSL_HAS_DDR3
35 select SYS_FSL_HAS_DDR4
36 select SYS_FSL_HAS_SEC
37 select SYS_FSL_SEC_COMPAT_5
40 select ARCH_EARLY_INIT_R
41 select BOARD_EARLY_INIT_F
43 select SYS_FSL_ERRATUM_A008997
44 select SYS_FSL_ERRATUM_A009007
45 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
46 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
52 select ARMV8_SET_SMPEN
53 select ARM_ERRATA_855873 if !TFABOOT
60 select SYS_FSL_DDR_VER_50
61 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
62 select SYS_FSL_ERRATUM_A008997
63 select SYS_FSL_ERRATUM_A009007
64 select SYS_FSL_ERRATUM_A009008
65 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
66 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
67 select SYS_FSL_ERRATUM_A009798
68 select SYS_FSL_ERRATUM_A009929
69 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
70 select SYS_FSL_ERRATUM_A010315
71 select SYS_FSL_ERRATUM_A010539
72 select SYS_FSL_HAS_DDR3
73 select SYS_FSL_HAS_DDR4
74 select ARCH_EARLY_INIT_R
75 select BOARD_EARLY_INIT_F
77 select SYS_I2C_MXC_I2C1
78 select SYS_I2C_MXC_I2C2
79 select SYS_I2C_MXC_I2C3
80 select SYS_I2C_MXC_I2C4
85 select ARMV8_SET_SMPEN
92 select SYS_FSL_DDR_VER_50
93 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
94 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
95 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
96 select SYS_FSL_ERRATUM_A008997
97 select SYS_FSL_ERRATUM_A009007
98 select SYS_FSL_ERRATUM_A009008
99 select SYS_FSL_ERRATUM_A009798
100 select SYS_FSL_ERRATUM_A009801
101 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
102 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
103 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
104 select SYS_FSL_ERRATUM_A010539
105 select SYS_FSL_HAS_DDR4
106 select SYS_FSL_SRDS_2
107 select ARCH_EARLY_INIT_R
108 select BOARD_EARLY_INIT_F
110 select SYS_I2C_MXC_I2C1
111 select SYS_I2C_MXC_I2C2
112 select SYS_I2C_MXC_I2C3
113 select SYS_I2C_MXC_I2C4
119 select ARMV8_SET_SMPEN
120 select ARM_ERRATA_855873 if !TFABOOT
121 select FSL_LAYERSCAPE
123 select SYS_FSL_SRDS_1
124 select SYS_HAS_SERDES
126 select SYS_FSL_DDR_LE
127 select SYS_FSL_DDR_VER_50
130 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
131 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
132 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
133 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
134 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
135 select SYS_FSL_ERRATUM_A009007
136 select SYS_FSL_HAS_CCI400
137 select SYS_FSL_HAS_DDR4
138 select SYS_FSL_HAS_RGMII
139 select SYS_FSL_HAS_SEC
140 select SYS_FSL_SEC_COMPAT_5
141 select SYS_FSL_SEC_LE
142 select SYS_FSL_SRDS_1
143 select SYS_FSL_SRDS_2
146 select FSL_TZPC_BP147
147 select ARCH_EARLY_INIT_R
148 select BOARD_EARLY_INIT_F
150 select SYS_I2C_MXC_I2C1
151 select SYS_I2C_MXC_I2C2
152 select SYS_I2C_MXC_I2C3
153 select SYS_I2C_MXC_I2C4
159 select ARMV8_SET_SMPEN
160 select ARM_ERRATA_826974
161 select ARM_ERRATA_828024
162 select ARM_ERRATA_829520
163 select ARM_ERRATA_833471
164 select FSL_LAYERSCAPE
166 select SYS_FSL_SRDS_1
167 select SYS_HAS_SERDES
169 select SYS_FSL_DDR_LE
170 select SYS_FSL_DDR_VER_50
171 select SYS_FSL_HAS_CCN504
172 select SYS_FSL_HAS_DP_DDR
173 select SYS_FSL_HAS_SEC
174 select SYS_FSL_HAS_DDR4
175 select SYS_FSL_SEC_COMPAT_5
176 select SYS_FSL_SEC_LE
177 select SYS_FSL_SRDS_2
181 select FSL_TZPC_BP147
182 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
183 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
184 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
185 select SYS_FSL_ERRATUM_A008585
186 select SYS_FSL_ERRATUM_A008997
187 select SYS_FSL_ERRATUM_A009007
188 select SYS_FSL_ERRATUM_A009008
189 select SYS_FSL_ERRATUM_A009635
190 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
191 select SYS_FSL_ERRATUM_A009798
192 select SYS_FSL_ERRATUM_A009801
193 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
194 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
195 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
196 select SYS_FSL_ERRATUM_A009203
197 select ARCH_EARLY_INIT_R
198 select BOARD_EARLY_INIT_F
200 select SYS_I2C_MXC_I2C1 if !TFABOOT
201 select SYS_I2C_MXC_I2C2 if !TFABOOT
202 select SYS_I2C_MXC_I2C3 if !TFABOOT
203 select SYS_I2C_MXC_I2C4 if !TFABOOT
204 imply DISTRO_DEFAULTS
209 select ARMV8_SET_SMPEN
212 select SYS_HAS_SERDES
213 select SYS_FSL_SRDS_1
214 select SYS_FSL_SRDS_2
215 select SYS_NXP_SRDS_3
217 select SYS_FSL_DDR_LE
218 select SYS_FSL_DDR_VER_50
221 select SYS_FSL_HAS_RGMII
222 select SYS_FSL_HAS_SEC
223 select SYS_FSL_HAS_CCN508
224 select SYS_FSL_HAS_DDR4
225 select SYS_FSL_SEC_COMPAT_5
226 select SYS_FSL_SEC_LE
227 select ARCH_EARLY_INIT_R
228 select BOARD_EARLY_INIT_F
230 imply DISTRO_DEFAULTS
237 select SYS_FSL_HAS_CCI400
238 select SYS_FSL_HAS_SEC
239 select SYS_FSL_SEC_COMPAT_5
240 select SYS_FSL_SEC_BE
249 bool "Management Complex network"
250 depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
254 Enable Management Complex (MC) network
256 menu "Layerscape architecture"
257 depends on FSL_LSCH2 || FSL_LSCH3
259 config FSL_LAYERSCAPE
262 config FSL_PCIE_COMPAT
263 string "PCIe compatible of Kernel DT"
264 depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
265 default "fsl,ls1012a-pcie" if ARCH_LS1012A
266 default "fsl,ls1028a-pcie" if ARCH_LS1028A
267 default "fsl,ls1043a-pcie" if ARCH_LS1043A
268 default "fsl,ls1046a-pcie" if ARCH_LS1046A
269 default "fsl,ls2080a-pcie" if ARCH_LS2080A
270 default "fsl,ls1088a-pcie" if ARCH_LS1088A
271 default "fsl,lx2160a-pcie" if ARCH_LX2160A
273 This compatible is used to find pci controller node in Kernel DT
276 config HAS_FEATURE_GIC64K_ALIGN
278 default y if ARCH_LS1043A
280 config HAS_FEATURE_ENHANCED_MSI
282 default y if ARCH_LS1043A
284 menu "Layerscape PPA"
286 bool "FSL Layerscape PPA firmware support"
287 depends on !ARMV8_PSCI
288 select ARMV8_SEC_FIRMWARE_SUPPORT
289 select SEC_FIRMWARE_ARMV8_PSCI
290 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
292 The FSL Primary Protected Application (PPA) is a software component
293 which is loaded during boot stage, and then remains resident in RAM
294 and runs in the TrustZone after boot.
297 config SPL_FSL_LS_PPA
298 bool "FSL Layerscape PPA firmware support for SPL build"
299 depends on !ARMV8_PSCI
300 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
301 select SEC_FIRMWARE_ARMV8_PSCI
302 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
304 The FSL Primary Protected Application (PPA) is a software component
305 which is loaded during boot stage, and then remains resident in RAM
306 and runs in the TrustZone after boot. This is to load PPA during SPL
307 stage instead of the RAM version of U-Boot. Once PPA is initialized,
308 the rest of U-Boot (including RAM version) runs at EL2.
310 prompt "FSL Layerscape PPA firmware loading-media select"
311 depends on FSL_LS_PPA
312 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
313 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
314 default SYS_LS_PPA_FW_IN_XIP
316 config SYS_LS_PPA_FW_IN_XIP
319 Say Y here if the PPA firmware locate at XIP flash, such
320 as NOR or QSPI flash.
322 config SYS_LS_PPA_FW_IN_MMC
323 bool "eMMC or SD Card"
325 Say Y here if the PPA firmware locate at eMMC/SD card.
327 config SYS_LS_PPA_FW_IN_NAND
330 Say Y here if the PPA firmware locate at NAND flash.
334 config LS_PPA_ESBC_HDR_SIZE
335 hex "Length of PPA ESBC header"
336 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
339 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
340 NAND to memory to validate PPA image.
344 config SYS_FSL_ERRATUM_A008997
345 bool "Workaround for USB PHY erratum A008997"
347 config SYS_FSL_ERRATUM_A009007
350 Workaround for USB PHY erratum A009007
352 config SYS_FSL_ERRATUM_A009008
353 bool "Workaround for USB PHY erratum A009008"
355 config SYS_FSL_ERRATUM_A009798
356 bool "Workaround for USB PHY erratum A009798"
358 config SYS_FSL_ERRATUM_A010315
359 bool "Workaround for PCIe erratum A010315"
361 config SYS_FSL_ERRATUM_A010539
362 bool "Workaround for PIN MUX erratum A010539"
365 int "Maximum number of CPUs permitted for Layerscape"
366 default 2 if ARCH_LS1028A
367 default 4 if ARCH_LS1043A
368 default 4 if ARCH_LS1046A
369 default 16 if ARCH_LS2080A
370 default 8 if ARCH_LS1088A
371 default 16 if ARCH_LX2160A
374 Set this number to the maximum number of possible CPUs in the SoC.
375 SoCs may have multiple clusters with each cluster may have multiple
376 ports. If some ports are reserved but higher ports are used for
377 cores, count the reserved ports. This will allocate enough memory
378 in spin table to properly handle all cores.
381 bool "Fan controller"
383 Enable the EMC2305 fan controller for configuration of fan
389 Enable Freescale Secure Boot feature
392 bool "Init the QSPI AHB bus"
394 The default setting for QSPI AHB bus just support 3bytes addressing.
395 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
396 bus for those flashes to support the full QSPI flash size.
398 config SYS_CCI400_OFFSET
399 hex "Offset for CCI400 base"
400 depends on SYS_FSL_HAS_CCI400
401 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
402 default 0x180000 if FSL_LSCH2
404 Offset for CCI400 base
405 CCI400 base addr = CCSRBAR + CCI400_OFFSET
407 config SYS_FSL_IFC_BANK_COUNT
408 int "Maximum banks of Integrated flash controller"
409 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
410 default 4 if ARCH_LS1043A
411 default 4 if ARCH_LS1046A
412 default 8 if ARCH_LS2080A || ARCH_LS1088A
414 config SYS_FSL_HAS_CCI400
417 config SYS_FSL_HAS_CCN504
420 config SYS_FSL_HAS_CCN508
423 config SYS_FSL_HAS_DP_DDR
426 config SYS_FSL_SRDS_1
429 config SYS_FSL_SRDS_2
432 config SYS_NXP_SRDS_3
435 config SYS_HAS_SERDES
447 config FSL_TZPC_BP147
451 menu "Layerscape clock tree configuration"
452 depends on FSL_LSCH2 || FSL_LSCH3
455 bool "Enable clock tree initialization"
458 config CLUSTER_CLK_FREQ
459 int "Reference clock of core cluster"
460 depends on ARCH_LS1012A
463 This number is the reference clock frequency of core PLL.
464 For most platforms, the core PLL and Platform PLL have the same
465 reference clock, but for some platforms, LS1012A for instance,
466 they are provided sepatately.
468 config SYS_FSL_PCLK_DIV
469 int "Platform clock divider"
470 default 1 if ARCH_LS1028A
471 default 1 if ARCH_LS1043A
472 default 1 if ARCH_LS1046A
473 default 1 if ARCH_LS1088A
476 This is the divider that is used to derive Platform clock from
477 Platform PLL, in another word:
478 Platform_clk = Platform_PLL_freq / this_divider
480 config SYS_FSL_DSPI_CLK_DIV
481 int "DSPI clock divider"
482 default 1 if ARCH_LS1043A
485 This is the divider that is used to derive DSPI clock from Platform
486 clock, in another word DSPI_clk = Platform_clk / this_divider.
488 config SYS_FSL_DUART_CLK_DIV
489 int "DUART clock divider"
490 default 1 if ARCH_LS1043A
491 default 4 if ARCH_LX2160A
494 This is the divider that is used to derive DUART clock from Platform
495 clock, in another word DUART_clk = Platform_clk / this_divider.
497 config SYS_FSL_I2C_CLK_DIV
498 int "I2C clock divider"
499 default 1 if ARCH_LS1043A
502 This is the divider that is used to derive I2C clock from Platform
503 clock, in another word I2C_clk = Platform_clk / this_divider.
505 config SYS_FSL_IFC_CLK_DIV
506 int "IFC clock divider"
507 default 1 if ARCH_LS1043A
510 This is the divider that is used to derive IFC clock from Platform
511 clock, in another word IFC_clk = Platform_clk / this_divider.
513 config SYS_FSL_LPUART_CLK_DIV
514 int "LPUART clock divider"
515 default 1 if ARCH_LS1043A
518 This is the divider that is used to derive LPUART clock from Platform
519 clock, in another word LPUART_clk = Platform_clk / this_divider.
521 config SYS_FSL_SDHC_CLK_DIV
522 int "SDHC clock divider"
523 default 1 if ARCH_LS1043A
524 default 1 if ARCH_LS1012A
527 This is the divider that is used to derive SDHC clock from Platform
528 clock, in another word SDHC_clk = Platform_clk / this_divider.
530 config SYS_FSL_QMAN_CLK_DIV
531 int "QMAN clock divider"
532 default 1 if ARCH_LS1043A
535 This is the divider that is used to derive QMAN clock from Platform
536 clock, in another word QMAN_clk = Platform_clk / this_divider.
542 Reserve memory from the top, tracked by gd->arch.resv_ram. This
543 reserved RAM can be used by special driver that resides in memory
544 after U-Boot exits. It's up to implementation to allocate and allow
545 access to this reserved memory. For example, the reserved RAM can
546 be at the high end of physical memory. The reserve RAM may be
547 excluded from memory bank(s) passed to OS, or marked as reserved.
552 Ethernet controller 1, this is connected to
553 MAC17 for LX2160A or to MAC3 for other SoCs
554 Provides DPAA2 capabilities
559 Ethernet controller 2, this is connected to
560 MAC18 for LX2160A or to MAC4 for other SoCs
561 Provides DPAA2 capabilities
563 config SYS_FSL_ERRATUM_A008336
566 config SYS_FSL_ERRATUM_A008514
569 config SYS_FSL_ERRATUM_A008585
572 config SYS_FSL_ERRATUM_A008850
575 config SYS_FSL_ERRATUM_A009203
578 config SYS_FSL_ERRATUM_A009635
581 config SYS_FSL_ERRATUM_A009660
584 config SYS_FSL_ERRATUM_A009929
588 config SYS_FSL_HAS_RGMII
590 depends on SYS_FSL_EC1 || SYS_FSL_EC2
593 config SYS_MC_RSV_MEM_ALIGN
594 hex "Management Complex reserved memory alignment"
596 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
598 Reserved memory needs to be aligned for MC to use. Default value
602 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
604 config HAS_FSL_XHCI_USB
606 default y if ARCH_LS1043A || ARCH_LS1046A
608 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
609 pins, select it when the pins are assigned to USB.