4 select ARM_ERRATA_855873 if !TFABOOT
8 select SKIP_LOWLEVEL_INIT
13 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
14 select SYS_FSL_ERRATUM_A009798
15 select SYS_FSL_ERRATUM_A008997
16 select SYS_FSL_ERRATUM_A009007
17 select SYS_FSL_ERRATUM_A009008
18 select ARCH_EARLY_INIT_R
19 select BOARD_EARLY_INIT_F
21 select SYS_I2C_MXC_I2C1 if !DM_I2C
22 select SYS_I2C_MXC_I2C2 if !DM_I2C
28 select ARMV8_SET_SMPEN
33 select SYS_FSL_HAS_CCI400
38 select SYS_FSL_DDR_VER_50
39 select SYS_FSL_HAS_DDR3
40 select SYS_FSL_HAS_DDR4
41 select SYS_FSL_HAS_SEC
42 select SYS_FSL_SEC_COMPAT_5
46 select ARCH_EARLY_INIT_R
47 select BOARD_EARLY_INIT_F
49 select SYS_FSL_ERRATUM_A008997
50 select SYS_FSL_ERRATUM_A009007
51 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
52 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
53 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
54 select SYS_FSL_ERRATUM_A050382
55 select SYS_FSL_ERRATUM_A011334
56 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
57 select RESV_RAM if GIC_V3_ITS
62 select ARMV8_SET_SMPEN
63 select ARM_ERRATA_855873 if !TFABOOT
64 select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
68 select HAS_FSL_XHCI_USB if USB_HOST
69 select SKIP_LOWLEVEL_INIT
74 select SYS_FSL_DDR_VER_50
75 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
76 select SYS_FSL_ERRATUM_A008997
77 select SYS_FSL_ERRATUM_A009007
78 select SYS_FSL_ERRATUM_A009008
79 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
80 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
81 select SYS_FSL_ERRATUM_A009798
82 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
83 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
84 select SYS_FSL_ERRATUM_A010539
85 select SYS_FSL_HAS_DDR3
86 select SYS_FSL_HAS_DDR4
87 select ARCH_EARLY_INIT_R
88 select BOARD_EARLY_INIT_F
90 select SYS_I2C_MXC_I2C1 if !DM_I2C
91 select SYS_I2C_MXC_I2C2 if !DM_I2C
92 select SYS_I2C_MXC_I2C3 if !DM_I2C
93 select SYS_I2C_MXC_I2C4 if !DM_I2C
99 select ARMV8_SET_SMPEN
100 select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
101 select FSL_LAYERSCAPE
104 select HAS_FSL_XHCI_USB if USB_HOST
105 select SKIP_LOWLEVEL_INIT
106 select SYS_FSL_SRDS_1
107 select SYS_HAS_SERDES
109 select SYS_FSL_DDR_BE
110 select SYS_FSL_DDR_VER_50
111 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
112 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
113 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
114 select SYS_FSL_ERRATUM_A008997
115 select SYS_FSL_ERRATUM_A009007
116 select SYS_FSL_ERRATUM_A009008
117 select SYS_FSL_ERRATUM_A009798
118 select SYS_FSL_ERRATUM_A009801
119 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
120 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
121 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
122 select SYS_FSL_ERRATUM_A010539
123 select SYS_FSL_HAS_DDR4
124 select SYS_FSL_SRDS_2
125 select ARCH_EARLY_INIT_R
126 select BOARD_EARLY_INIT_F
128 select SYS_I2C_MXC_I2C1 if !DM_I2C
129 select SYS_I2C_MXC_I2C2 if !DM_I2C
130 select SYS_I2C_MXC_I2C3 if !DM_I2C
131 select SYS_I2C_MXC_I2C4 if !DM_I2C
135 imply SPL_SYS_I2C_LEGACY
139 select ARMV8_SET_SMPEN
140 select ARM_ERRATA_855873 if !TFABOOT
142 select FSL_LAYERSCAPE
145 select SKIP_LOWLEVEL_INIT
146 select SYS_FSL_SRDS_1
147 select SYS_HAS_SERDES
149 select SYS_FSL_DDR_LE
150 select SYS_FSL_DDR_VER_50
153 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
154 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
155 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
156 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
157 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
158 select SYS_FSL_ERRATUM_A009007
159 select SYS_FSL_HAS_CCI400
160 select SYS_FSL_HAS_DDR4
161 select SYS_FSL_HAS_RGMII
162 select SYS_FSL_HAS_SEC
163 select SYS_FSL_SEC_COMPAT_5
164 select SYS_FSL_SEC_LE
165 select SYS_FSL_SRDS_1
166 select SYS_FSL_SRDS_2
169 select FSL_TZPC_BP147
170 select ARCH_EARLY_INIT_R
171 select BOARD_EARLY_INIT_F
173 select SYS_I2C_MXC_I2C1 if !TFABOOT
174 select SYS_I2C_MXC_I2C2 if !TFABOOT
175 select SYS_I2C_MXC_I2C3 if !TFABOOT
176 select SYS_I2C_MXC_I2C4 if !TFABOOT
177 select RESV_RAM if GIC_V3_ITS
180 imply SPL_SYS_I2C_LEGACY
185 select ARMV8_SET_SMPEN
186 select ARM_ERRATA_826974
187 select ARM_ERRATA_828024
188 select ARM_ERRATA_829520
189 select ARM_ERRATA_833471
191 select FSL_LAYERSCAPE
194 select SKIP_LOWLEVEL_INIT
195 select SYS_FSL_SRDS_1
196 select SYS_HAS_SERDES
198 select SYS_FSL_DDR_LE
199 select SYS_FSL_DDR_VER_50
200 select SYS_FSL_HAS_CCN504
201 select SYS_FSL_HAS_DP_DDR
202 select SYS_FSL_HAS_SEC
203 select SYS_FSL_HAS_DDR4
204 select SYS_FSL_SEC_COMPAT_5
205 select SYS_FSL_SEC_LE
206 select SYS_FSL_SRDS_2
210 select FSL_TZPC_BP147
211 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
212 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
213 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
214 select SYS_FSL_ERRATUM_A008585
215 select SYS_FSL_ERRATUM_A008997
216 select SYS_FSL_ERRATUM_A009007
217 select SYS_FSL_ERRATUM_A009008
218 select SYS_FSL_ERRATUM_A009635
219 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
220 select SYS_FSL_ERRATUM_A009798
221 select SYS_FSL_ERRATUM_A009801
222 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
223 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
224 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
225 select SYS_FSL_ERRATUM_A009203
226 select ARCH_EARLY_INIT_R
227 select BOARD_EARLY_INIT_F
229 select SYS_I2C_MXC_I2C1 if !TFABOOT
230 select SYS_I2C_MXC_I2C2 if !TFABOOT
231 select SYS_I2C_MXC_I2C3 if !TFABOOT
232 select SYS_I2C_MXC_I2C4 if !TFABOOT
233 select RESV_RAM if GIC_V3_ITS
234 imply DISTRO_DEFAULTS
237 imply SPL_SYS_I2C_LEGACY
241 select ARMV8_SET_SMPEN
243 select FSL_DDR_INTERACTIVE
244 select FSL_LAYERSCAPE
246 select FSL_TZPC_BP147
249 select SYS_HAS_SERDES
250 select SYS_FSL_SRDS_1
251 select SYS_FSL_SRDS_2
253 select SYS_FSL_DDR_LE
254 select SYS_FSL_DDR_VER_50
257 select SYS_FSL_ERRATUM_A050204
258 select SYS_FSL_ERRATUM_A011334
259 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
260 select SYS_FSL_HAS_RGMII
261 select SYS_FSL_HAS_SEC
262 select SYS_FSL_HAS_CCN508
263 select SYS_FSL_HAS_DDR4
264 select SYS_FSL_SEC_COMPAT_5
265 select SYS_FSL_SEC_LE
266 select SYS_PCI_64BIT if PCI
267 select ARCH_EARLY_INIT_R
268 select BOARD_EARLY_INIT_F
270 select RESV_RAM if GIC_V3_ITS
271 imply DISTRO_DEFAULTS
275 imply SPL_SYS_I2C_LEGACY
279 select ARMV8_SET_SMPEN
281 select FSL_DDR_INTERACTIVE
282 select FSL_LAYERSCAPE
284 select FSL_TZPC_BP147
286 select HAS_FSL_XHCI_USB if USB_HOST
288 select SYS_HAS_SERDES
289 select SYS_FSL_SRDS_1
290 select SYS_FSL_SRDS_2
291 select SYS_NXP_SRDS_3
293 select SYS_FSL_DDR_LE
294 select SYS_FSL_DDR_VER_50
297 select SYS_FSL_ERRATUM_A050204
298 select SYS_FSL_ERRATUM_A011334
299 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
300 select SYS_FSL_HAS_RGMII
301 select SYS_FSL_HAS_SEC
302 select SYS_FSL_HAS_CCN508
303 select SYS_FSL_HAS_DDR4
304 select SYS_FSL_SEC_COMPAT_5
305 select SYS_FSL_SEC_LE
306 select SYS_PCI_64BIT if PCI
307 select ARCH_EARLY_INIT_R
308 select BOARD_EARLY_INIT_F
310 select RESV_RAM if GIC_V3_ITS
311 imply DISTRO_DEFAULTS
316 imply SPL_SYS_I2C_LEGACY
320 select SKIP_LOWLEVEL_INIT
321 select SYS_FSL_HAS_CCI400
322 select SYS_FSL_HAS_SEC
323 select SYS_FSL_SEC_COMPAT_5
324 select SYS_FSL_SEC_BE
327 select ARCH_MISC_INIT
333 menu "Layerscape architecture"
334 depends on FSL_LSCH2 || FSL_LSCH3
336 config FSL_LAYERSCAPE
339 config HAS_FEATURE_GIC64K_ALIGN
341 default y if ARCH_LS1043A
343 config HAS_FEATURE_ENHANCED_MSI
345 default y if ARCH_LS1043A
347 menu "Layerscape PPA"
349 bool "FSL Layerscape PPA firmware support"
350 depends on !ARMV8_PSCI
351 select ARMV8_SEC_FIRMWARE_SUPPORT
352 select SEC_FIRMWARE_ARMV8_PSCI
353 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
355 The FSL Primary Protected Application (PPA) is a software component
356 which is loaded during boot stage, and then remains resident in RAM
357 and runs in the TrustZone after boot.
360 config SPL_FSL_LS_PPA
361 bool "FSL Layerscape PPA firmware support for SPL build"
362 depends on !ARMV8_PSCI
363 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
364 select SEC_FIRMWARE_ARMV8_PSCI
365 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
367 The FSL Primary Protected Application (PPA) is a software component
368 which is loaded during boot stage, and then remains resident in RAM
369 and runs in the TrustZone after boot. This is to load PPA during SPL
370 stage instead of the RAM version of U-Boot. Once PPA is initialized,
371 the rest of U-Boot (including RAM version) runs at EL2.
373 prompt "FSL Layerscape PPA firmware loading-media select"
374 depends on FSL_LS_PPA
375 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
376 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
377 default SYS_LS_PPA_FW_IN_XIP
379 config SYS_LS_PPA_FW_IN_XIP
382 Say Y here if the PPA firmware locate at XIP flash, such
383 as NOR or QSPI flash.
385 config SYS_LS_PPA_FW_IN_MMC
386 bool "eMMC or SD Card"
388 Say Y here if the PPA firmware locate at eMMC/SD card.
390 config SYS_LS_PPA_FW_IN_NAND
393 Say Y here if the PPA firmware locate at NAND flash.
397 config LS_PPA_ESBC_HDR_SIZE
398 hex "Length of PPA ESBC header"
399 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
402 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
403 NAND to memory to validate PPA image.
407 config SYS_FSL_ERRATUM_A008997
408 bool "Workaround for USB PHY erratum A008997"
410 config SYS_FSL_ERRATUM_A009007
413 Workaround for USB PHY erratum A009007
415 config SYS_FSL_ERRATUM_A009008
416 bool "Workaround for USB PHY erratum A009008"
418 config SYS_FSL_ERRATUM_A009798
419 bool "Workaround for USB PHY erratum A009798"
421 config SYS_FSL_ERRATUM_A050204
422 bool "Workaround for USB PHY erratum A050204"
424 USB3.0 Receiver needs to enable fixed equalization
425 for each of PHY instances in an SOC. This is similar
426 to erratum A-009007, but this one is for LX2160A and LX2162A,
427 and the register value is different.
429 config SYS_FSL_ERRATUM_A010315
430 bool "Workaround for PCIe erratum A010315"
432 config SYS_FSL_ERRATUM_A010539
433 bool "Workaround for PIN MUX erratum A010539"
436 int "Maximum number of CPUs permitted for Layerscape"
437 default 2 if ARCH_LS1028A
438 default 4 if ARCH_LS1043A
439 default 4 if ARCH_LS1046A
440 default 16 if ARCH_LS2080A
441 default 8 if ARCH_LS1088A
442 default 16 if ARCH_LX2160A
443 default 16 if ARCH_LX2162A
446 Set this number to the maximum number of possible CPUs in the SoC.
447 SoCs may have multiple clusters with each cluster may have multiple
448 ports. If some ports are reserved but higher ports are used for
449 cores, count the reserved ports. This will allocate enough memory
450 in spin table to properly handle all cores.
453 bool "Fan controller"
455 Enable the EMC2305 fan controller for configuration of fan
461 Enable Freescale Secure Boot feature
464 bool "Init the QSPI AHB bus"
466 The default setting for QSPI AHB bus just support 3bytes addressing.
467 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
468 bus for those flashes to support the full QSPI flash size.
470 config FSPI_AHB_EN_4BYTE
471 bool "Enable 4-byte Fast Read command for AHB mode"
473 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
474 But some FlexSPI flash sizes are up to 64MBytes.
475 This flag enables fast read command for AHB mode and modifies required
476 LUT to support full FlexSPI flash.
478 config SYS_CCI400_OFFSET
479 hex "Offset for CCI400 base"
480 depends on SYS_FSL_HAS_CCI400
481 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
482 default 0x180000 if FSL_LSCH2
484 Offset for CCI400 base
485 CCI400 base addr = CCSRBAR + CCI400_OFFSET
487 config SYS_FSL_IFC_BANK_COUNT
488 int "Maximum banks of Integrated flash controller"
489 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
490 default 4 if ARCH_LS1043A
491 default 4 if ARCH_LS1046A
492 default 8 if ARCH_LS2080A || ARCH_LS1088A
494 config SYS_FSL_HAS_CCI400
497 config SYS_FSL_HAS_CCN504
500 config SYS_FSL_HAS_CCN508
503 config SYS_FSL_HAS_DP_DDR
506 config SYS_FSL_SRDS_1
509 config SYS_FSL_SRDS_2
512 config SYS_NXP_SRDS_3
515 config SYS_HAS_SERDES
527 config FSL_TZPC_BP147
531 menu "Layerscape clock tree configuration"
532 depends on FSL_LSCH2 || FSL_LSCH3
534 config CLUSTER_CLK_FREQ
535 int "Reference clock of core cluster"
536 depends on ARCH_LS1012A
539 This number is the reference clock frequency of core PLL.
540 For most platforms, the core PLL and Platform PLL have the same
541 reference clock, but for some platforms, LS1012A for instance,
542 they are provided sepatately.
544 config SYS_FSL_PCLK_DIV
545 int "Platform clock divider"
546 default 1 if ARCH_LS1028A
547 default 1 if ARCH_LS1043A
548 default 1 if ARCH_LS1046A
549 default 1 if ARCH_LS1088A
552 This is the divider that is used to derive Platform clock from
553 Platform PLL, in another word:
554 Platform_clk = Platform_PLL_freq / this_divider
556 config SYS_FSL_DSPI_CLK_DIV
557 int "DSPI clock divider"
558 default 1 if ARCH_LS1043A
561 This is the divider that is used to derive DSPI clock from Platform
562 clock, in another word DSPI_clk = Platform_clk / this_divider.
564 config SYS_FSL_DUART_CLK_DIV
565 int "DUART clock divider"
566 default 1 if ARCH_LS1043A
567 default 4 if ARCH_LX2160A
568 default 4 if ARCH_LX2162A
571 This is the divider that is used to derive DUART clock from Platform
572 clock, in another word DUART_clk = Platform_clk / this_divider.
574 config SYS_FSL_I2C_CLK_DIV
575 int "I2C clock divider"
576 default 1 if ARCH_LS1043A
577 default 4 if ARCH_LS1012A
578 default 4 if ARCH_LS1028A
579 default 8 if ARCH_LX2160A
580 default 8 if ARCH_LX2162A
581 default 8 if ARCH_LS1088A
584 This is the divider that is used to derive I2C clock from Platform
585 clock, in another word I2C_clk = Platform_clk / this_divider.
587 config SYS_FSL_IFC_CLK_DIV
588 int "IFC clock divider"
589 default 1 if ARCH_LS1043A
590 default 4 if ARCH_LS1012A
591 default 4 if ARCH_LS1028A
592 default 8 if ARCH_LX2160A
593 default 8 if ARCH_LX2162A
594 default 8 if ARCH_LS1088A
597 This is the divider that is used to derive IFC clock from Platform
598 clock, in another word IFC_clk = Platform_clk / this_divider.
600 config SYS_FSL_LPUART_CLK_DIV
601 int "LPUART clock divider"
602 default 1 if ARCH_LS1043A
605 This is the divider that is used to derive LPUART clock from Platform
606 clock, in another word LPUART_clk = Platform_clk / this_divider.
608 config SYS_FSL_SDHC_CLK_DIV
609 int "SDHC clock divider"
610 default 1 if ARCH_LS1043A
611 default 1 if ARCH_LS1012A
614 This is the divider that is used to derive SDHC clock from Platform
615 clock, in another word SDHC_clk = Platform_clk / this_divider.
617 config SYS_FSL_QMAN_CLK_DIV
618 int "QMAN clock divider"
619 default 1 if ARCH_LS1043A
622 This is the divider that is used to derive QMAN clock from Platform
623 clock, in another word QMAN_clk = Platform_clk / this_divider.
629 Reserve memory from the top, tracked by gd->arch.resv_ram. This
630 reserved RAM can be used by special driver that resides in memory
631 after U-Boot exits. It's up to implementation to allocate and allow
632 access to this reserved memory. For example, the reserved RAM can
633 be at the high end of physical memory. The reserve RAM may be
634 excluded from memory bank(s) passed to OS, or marked as reserved.
639 Ethernet controller 1, this is connected to
640 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
641 Provides DPAA2 capabilities
646 Ethernet controller 2, this is connected to
647 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
648 Provides DPAA2 capabilities
650 config SYS_FSL_ERRATUM_A008336
653 config SYS_FSL_ERRATUM_A008514
656 config SYS_FSL_ERRATUM_A008585
659 config SYS_FSL_ERRATUM_A008850
662 config SYS_FSL_ERRATUM_A009203
665 config SYS_FSL_ERRATUM_A009635
668 config SYS_FSL_ERRATUM_A009660
671 config SYS_FSL_ERRATUM_A050382
674 config SYS_FSL_HAS_RGMII
676 depends on SYS_FSL_EC1 || SYS_FSL_EC2
679 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
681 config HAS_FSL_XHCI_USB
684 For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
685 pins, select it when the pins are assigned to USB.
687 config SYS_FSL_BOOTROM_BASE
692 config SYS_FSL_BOOTROM_SIZE