5 select SYS_FSL_ERRATUM_A010315
10 select SYS_FSL_ERRATUM_A010315
11 select SYS_FSL_ERRATUM_A010539
16 select SYS_FSL_ERRATUM_A010539
28 menu "Layerscape architecture"
29 depends on FSL_LSCH2 || FSL_LSCH3
34 config SYS_FSL_ERRATUM_A010315
35 bool "Workaround for PCIe erratum A010315"
37 config SYS_FSL_ERRATUM_A010539
38 bool "Workaround for PIN MUX erratum A010539"
41 int "Maximum number of CPUs permitted for Layerscape"
42 default 4 if ARCH_LS1043A
43 default 4 if ARCH_LS1046A
44 default 16 if ARCH_LS2080A
47 Set this number to the maximum number of possible CPUs in the SoC.
48 SoCs may have multiple clusters with each cluster may have multiple
49 ports. If some ports are reserved but higher ports are used for
50 cores, count the reserved ports. This will allocate enough memory
51 in spin table to properly handle all cores.
53 config NUM_DDR_CONTROLLERS
54 int "Maximum DDR controllers"
55 default 3 if ARCH_LS2080A
58 config SYS_FSL_IFC_BANK_COUNT
59 int "Maximum banks of Integrated flash controller"
60 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
61 default 4 if ARCH_LS1043A
62 default 4 if ARCH_LS1046A
63 default 8 if ARCH_LS2080A
65 config SYS_FSL_HAS_DP_DDR