4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1 if !DM_I2C
20 select SYS_I2C_MXC_I2C2 if !DM_I2C
25 select ARMV8_SET_SMPEN
29 select SYS_FSL_HAS_CCI400
34 select SYS_FSL_DDR_VER_50
35 select SYS_FSL_HAS_DDR3
36 select SYS_FSL_HAS_DDR4
37 select SYS_FSL_HAS_SEC
38 select SYS_FSL_SEC_COMPAT_5
41 select ARCH_EARLY_INIT_R
42 select BOARD_EARLY_INIT_F
44 select SYS_FSL_ERRATUM_A008997
45 select SYS_FSL_ERRATUM_A009007
46 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
48 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
49 select SYS_FSL_ERRATUM_A050382
50 select RESV_RAM if GIC_V3_ITS
55 select ARMV8_SET_SMPEN
56 select ARM_ERRATA_855873 if !TFABOOT
63 select SYS_FSL_DDR_VER_50
64 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
65 select SYS_FSL_ERRATUM_A008997
66 select SYS_FSL_ERRATUM_A009007
67 select SYS_FSL_ERRATUM_A009008
68 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
69 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
70 select SYS_FSL_ERRATUM_A009798
71 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
72 select SYS_FSL_ERRATUM_A010315
73 select SYS_FSL_ERRATUM_A010539
74 select SYS_FSL_HAS_DDR3
75 select SYS_FSL_HAS_DDR4
76 select ARCH_EARLY_INIT_R
77 select BOARD_EARLY_INIT_F
79 select SYS_I2C_MXC_I2C1 if !DM_I2C
80 select SYS_I2C_MXC_I2C2 if !DM_I2C
81 select SYS_I2C_MXC_I2C3 if !DM_I2C
82 select SYS_I2C_MXC_I2C4 if !DM_I2C
87 select ARMV8_SET_SMPEN
94 select SYS_FSL_DDR_VER_50
95 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
96 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
97 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
98 select SYS_FSL_ERRATUM_A008997
99 select SYS_FSL_ERRATUM_A009007
100 select SYS_FSL_ERRATUM_A009008
101 select SYS_FSL_ERRATUM_A009798
102 select SYS_FSL_ERRATUM_A009801
103 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
104 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
105 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
106 select SYS_FSL_ERRATUM_A010539
107 select SYS_FSL_HAS_DDR4
108 select SYS_FSL_SRDS_2
109 select ARCH_EARLY_INIT_R
110 select BOARD_EARLY_INIT_F
112 select SYS_I2C_MXC_I2C1 if !DM_I2C
113 select SYS_I2C_MXC_I2C2 if !DM_I2C
114 select SYS_I2C_MXC_I2C3 if !DM_I2C
115 select SYS_I2C_MXC_I2C4 if !DM_I2C
121 select ARMV8_SET_SMPEN
122 select ARM_ERRATA_855873 if !TFABOOT
123 select FSL_LAYERSCAPE
125 select SYS_FSL_SRDS_1
126 select SYS_HAS_SERDES
128 select SYS_FSL_DDR_LE
129 select SYS_FSL_DDR_VER_50
132 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
133 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
134 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
135 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
136 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
137 select SYS_FSL_ERRATUM_A009007
138 select SYS_FSL_HAS_CCI400
139 select SYS_FSL_HAS_DDR4
140 select SYS_FSL_HAS_RGMII
141 select SYS_FSL_HAS_SEC
142 select SYS_FSL_SEC_COMPAT_5
143 select SYS_FSL_SEC_LE
144 select SYS_FSL_SRDS_1
145 select SYS_FSL_SRDS_2
148 select FSL_TZPC_BP147
149 select ARCH_EARLY_INIT_R
150 select BOARD_EARLY_INIT_F
152 select SYS_I2C_MXC_I2C1 if !TFABOOT
153 select SYS_I2C_MXC_I2C2 if !TFABOOT
154 select SYS_I2C_MXC_I2C3 if !TFABOOT
155 select SYS_I2C_MXC_I2C4 if !TFABOOT
156 select RESV_RAM if GIC_V3_ITS
162 select ARMV8_SET_SMPEN
163 select ARM_ERRATA_826974
164 select ARM_ERRATA_828024
165 select ARM_ERRATA_829520
166 select ARM_ERRATA_833471
167 select FSL_LAYERSCAPE
169 select SYS_FSL_SRDS_1
170 select SYS_HAS_SERDES
172 select SYS_FSL_DDR_LE
173 select SYS_FSL_DDR_VER_50
174 select SYS_FSL_HAS_CCN504
175 select SYS_FSL_HAS_DP_DDR
176 select SYS_FSL_HAS_SEC
177 select SYS_FSL_HAS_DDR4
178 select SYS_FSL_SEC_COMPAT_5
179 select SYS_FSL_SEC_LE
180 select SYS_FSL_SRDS_2
184 select FSL_TZPC_BP147
185 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
186 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
187 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
188 select SYS_FSL_ERRATUM_A008585
189 select SYS_FSL_ERRATUM_A008997
190 select SYS_FSL_ERRATUM_A009007
191 select SYS_FSL_ERRATUM_A009008
192 select SYS_FSL_ERRATUM_A009635
193 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
194 select SYS_FSL_ERRATUM_A009798
195 select SYS_FSL_ERRATUM_A009801
196 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
197 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
198 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
199 select SYS_FSL_ERRATUM_A009203
200 select ARCH_EARLY_INIT_R
201 select BOARD_EARLY_INIT_F
203 select SYS_I2C_MXC_I2C1 if !TFABOOT
204 select SYS_I2C_MXC_I2C2 if !TFABOOT
205 select SYS_I2C_MXC_I2C3 if !TFABOOT
206 select SYS_I2C_MXC_I2C4 if !TFABOOT
207 select RESV_RAM if GIC_V3_ITS
208 imply DISTRO_DEFAULTS
213 select ARMV8_SET_SMPEN
216 select SYS_HAS_SERDES
217 select SYS_FSL_SRDS_1
218 select SYS_FSL_SRDS_2
220 select SYS_FSL_DDR_LE
221 select SYS_FSL_DDR_VER_50
224 select SYS_FSL_ERRATUM_A050106
225 select SYS_FSL_HAS_RGMII
226 select SYS_FSL_HAS_SEC
227 select SYS_FSL_HAS_CCN508
228 select SYS_FSL_HAS_DDR4
229 select SYS_FSL_SEC_COMPAT_5
230 select SYS_FSL_SEC_LE
231 select ARCH_EARLY_INIT_R
232 select BOARD_EARLY_INIT_F
234 select RESV_RAM if GIC_V3_ITS
235 imply DISTRO_DEFAULTS
242 select ARMV8_SET_SMPEN
245 select SYS_HAS_SERDES
246 select SYS_FSL_SRDS_1
247 select SYS_FSL_SRDS_2
248 select SYS_NXP_SRDS_3
250 select SYS_FSL_DDR_LE
251 select SYS_FSL_DDR_VER_50
254 select SYS_FSL_ERRATUM_A050106
255 select SYS_FSL_HAS_RGMII
256 select SYS_FSL_HAS_SEC
257 select SYS_FSL_HAS_CCN508
258 select SYS_FSL_HAS_DDR4
259 select SYS_FSL_SEC_COMPAT_5
260 select SYS_FSL_SEC_LE
261 select ARCH_EARLY_INIT_R
262 select BOARD_EARLY_INIT_F
264 select RESV_RAM if GIC_V3_ITS
265 imply DISTRO_DEFAULTS
272 select SYS_FSL_HAS_CCI400
273 select SYS_FSL_HAS_SEC
274 select SYS_FSL_SEC_COMPAT_5
275 select SYS_FSL_SEC_BE
278 select ARCH_MISC_INIT
284 menu "Layerscape architecture"
285 depends on FSL_LSCH2 || FSL_LSCH3
287 config FSL_LAYERSCAPE
290 config HAS_FEATURE_GIC64K_ALIGN
292 default y if ARCH_LS1043A
294 config HAS_FEATURE_ENHANCED_MSI
296 default y if ARCH_LS1043A
298 menu "Layerscape PPA"
300 bool "FSL Layerscape PPA firmware support"
301 depends on !ARMV8_PSCI
302 select ARMV8_SEC_FIRMWARE_SUPPORT
303 select SEC_FIRMWARE_ARMV8_PSCI
304 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
306 The FSL Primary Protected Application (PPA) is a software component
307 which is loaded during boot stage, and then remains resident in RAM
308 and runs in the TrustZone after boot.
311 config SPL_FSL_LS_PPA
312 bool "FSL Layerscape PPA firmware support for SPL build"
313 depends on !ARMV8_PSCI
314 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
315 select SEC_FIRMWARE_ARMV8_PSCI
316 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
318 The FSL Primary Protected Application (PPA) is a software component
319 which is loaded during boot stage, and then remains resident in RAM
320 and runs in the TrustZone after boot. This is to load PPA during SPL
321 stage instead of the RAM version of U-Boot. Once PPA is initialized,
322 the rest of U-Boot (including RAM version) runs at EL2.
324 prompt "FSL Layerscape PPA firmware loading-media select"
325 depends on FSL_LS_PPA
326 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
327 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
328 default SYS_LS_PPA_FW_IN_XIP
330 config SYS_LS_PPA_FW_IN_XIP
333 Say Y here if the PPA firmware locate at XIP flash, such
334 as NOR or QSPI flash.
336 config SYS_LS_PPA_FW_IN_MMC
337 bool "eMMC or SD Card"
339 Say Y here if the PPA firmware locate at eMMC/SD card.
341 config SYS_LS_PPA_FW_IN_NAND
344 Say Y here if the PPA firmware locate at NAND flash.
348 config LS_PPA_ESBC_HDR_SIZE
349 hex "Length of PPA ESBC header"
350 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
353 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
354 NAND to memory to validate PPA image.
358 config SYS_FSL_ERRATUM_A008997
359 bool "Workaround for USB PHY erratum A008997"
361 config SYS_FSL_ERRATUM_A009007
364 Workaround for USB PHY erratum A009007
366 config SYS_FSL_ERRATUM_A009008
367 bool "Workaround for USB PHY erratum A009008"
369 config SYS_FSL_ERRATUM_A009798
370 bool "Workaround for USB PHY erratum A009798"
372 config SYS_FSL_ERRATUM_A050106
373 bool "Workaround for USB PHY erratum A050106"
375 USB3.0 Receiver needs to enable fixed equalization
376 for each of PHY instances in an SOC. This is similar
377 to erratum A-009007, but this one is for LX2160A and LX2162A,
378 and the register value is different.
380 config SYS_FSL_ERRATUM_A010315
381 bool "Workaround for PCIe erratum A010315"
383 config SYS_FSL_ERRATUM_A010539
384 bool "Workaround for PIN MUX erratum A010539"
387 int "Maximum number of CPUs permitted for Layerscape"
388 default 2 if ARCH_LS1028A
389 default 4 if ARCH_LS1043A
390 default 4 if ARCH_LS1046A
391 default 16 if ARCH_LS2080A
392 default 8 if ARCH_LS1088A
393 default 16 if ARCH_LX2160A
394 default 16 if ARCH_LX2162A
397 Set this number to the maximum number of possible CPUs in the SoC.
398 SoCs may have multiple clusters with each cluster may have multiple
399 ports. If some ports are reserved but higher ports are used for
400 cores, count the reserved ports. This will allocate enough memory
401 in spin table to properly handle all cores.
404 bool "Fan controller"
406 Enable the EMC2305 fan controller for configuration of fan
412 Enable Freescale Secure Boot feature
415 bool "Init the QSPI AHB bus"
417 The default setting for QSPI AHB bus just support 3bytes addressing.
418 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
419 bus for those flashes to support the full QSPI flash size.
421 config FSPI_AHB_EN_4BYTE
422 bool "Enable 4-byte Fast Read command for AHB mode"
425 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
426 But some FlexSPI flash sizes are up to 64MBytes.
427 This flag enables fast read command for AHB mode and modifies required
428 LUT to support full FlexSPI flash.
430 config SYS_CCI400_OFFSET
431 hex "Offset for CCI400 base"
432 depends on SYS_FSL_HAS_CCI400
433 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
434 default 0x180000 if FSL_LSCH2
436 Offset for CCI400 base
437 CCI400 base addr = CCSRBAR + CCI400_OFFSET
439 config SYS_FSL_IFC_BANK_COUNT
440 int "Maximum banks of Integrated flash controller"
441 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
442 default 4 if ARCH_LS1043A
443 default 4 if ARCH_LS1046A
444 default 8 if ARCH_LS2080A || ARCH_LS1088A
446 config SYS_FSL_HAS_CCI400
449 config SYS_FSL_HAS_CCN504
452 config SYS_FSL_HAS_CCN508
455 config SYS_FSL_HAS_DP_DDR
458 config SYS_FSL_SRDS_1
461 config SYS_FSL_SRDS_2
464 config SYS_NXP_SRDS_3
467 config SYS_HAS_SERDES
479 config FSL_TZPC_BP147
483 menu "Layerscape clock tree configuration"
484 depends on FSL_LSCH2 || FSL_LSCH3
487 bool "Enable clock tree initialization"
490 config CLUSTER_CLK_FREQ
491 int "Reference clock of core cluster"
492 depends on ARCH_LS1012A
495 This number is the reference clock frequency of core PLL.
496 For most platforms, the core PLL and Platform PLL have the same
497 reference clock, but for some platforms, LS1012A for instance,
498 they are provided sepatately.
500 config SYS_FSL_PCLK_DIV
501 int "Platform clock divider"
502 default 1 if ARCH_LS1028A
503 default 1 if ARCH_LS1043A
504 default 1 if ARCH_LS1046A
505 default 1 if ARCH_LS1088A
508 This is the divider that is used to derive Platform clock from
509 Platform PLL, in another word:
510 Platform_clk = Platform_PLL_freq / this_divider
512 config SYS_FSL_DSPI_CLK_DIV
513 int "DSPI clock divider"
514 default 1 if ARCH_LS1043A
517 This is the divider that is used to derive DSPI clock from Platform
518 clock, in another word DSPI_clk = Platform_clk / this_divider.
520 config SYS_FSL_DUART_CLK_DIV
521 int "DUART clock divider"
522 default 1 if ARCH_LS1043A
523 default 4 if ARCH_LX2160A
524 default 4 if ARCH_LX2162A
527 This is the divider that is used to derive DUART clock from Platform
528 clock, in another word DUART_clk = Platform_clk / this_divider.
530 config SYS_FSL_I2C_CLK_DIV
531 int "I2C clock divider"
532 default 1 if ARCH_LS1043A
533 default 4 if ARCH_LS1012A
534 default 4 if ARCH_LS1028A
535 default 8 if ARCH_LX2160A
536 default 8 if ARCH_LX2162A
537 default 8 if ARCH_LS1088A
540 This is the divider that is used to derive I2C clock from Platform
541 clock, in another word I2C_clk = Platform_clk / this_divider.
543 config SYS_FSL_IFC_CLK_DIV
544 int "IFC clock divider"
545 default 1 if ARCH_LS1043A
546 default 4 if ARCH_LS1012A
547 default 4 if ARCH_LS1028A
548 default 8 if ARCH_LX2160A
549 default 8 if ARCH_LX2162A
550 default 8 if ARCH_LS1088A
553 This is the divider that is used to derive IFC clock from Platform
554 clock, in another word IFC_clk = Platform_clk / this_divider.
556 config SYS_FSL_LPUART_CLK_DIV
557 int "LPUART clock divider"
558 default 1 if ARCH_LS1043A
561 This is the divider that is used to derive LPUART clock from Platform
562 clock, in another word LPUART_clk = Platform_clk / this_divider.
564 config SYS_FSL_SDHC_CLK_DIV
565 int "SDHC clock divider"
566 default 1 if ARCH_LS1043A
567 default 1 if ARCH_LS1012A
570 This is the divider that is used to derive SDHC clock from Platform
571 clock, in another word SDHC_clk = Platform_clk / this_divider.
573 config SYS_FSL_QMAN_CLK_DIV
574 int "QMAN clock divider"
575 default 1 if ARCH_LS1043A
578 This is the divider that is used to derive QMAN clock from Platform
579 clock, in another word QMAN_clk = Platform_clk / this_divider.
585 Reserve memory from the top, tracked by gd->arch.resv_ram. This
586 reserved RAM can be used by special driver that resides in memory
587 after U-Boot exits. It's up to implementation to allocate and allow
588 access to this reserved memory. For example, the reserved RAM can
589 be at the high end of physical memory. The reserve RAM may be
590 excluded from memory bank(s) passed to OS, or marked as reserved.
595 Ethernet controller 1, this is connected to
596 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
597 Provides DPAA2 capabilities
602 Ethernet controller 2, this is connected to
603 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
604 Provides DPAA2 capabilities
606 config SYS_FSL_ERRATUM_A008336
609 config SYS_FSL_ERRATUM_A008514
612 config SYS_FSL_ERRATUM_A008585
615 config SYS_FSL_ERRATUM_A008850
618 config SYS_FSL_ERRATUM_A009203
621 config SYS_FSL_ERRATUM_A009635
624 config SYS_FSL_ERRATUM_A009660
627 config SYS_FSL_ERRATUM_A050382
630 config SYS_FSL_HAS_RGMII
632 depends on SYS_FSL_EC1 || SYS_FSL_EC2
635 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
637 config HAS_FSL_XHCI_USB
639 default y if ARCH_LS1043A || ARCH_LS1046A
641 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
642 pins, select it when the pins are assigned to USB.