4 select ARM_ERRATA_855873 if !TFABOOT
10 select SYS_FSL_ERRATUM_A010315
11 select SYS_FSL_ERRATUM_A009798
12 select SYS_FSL_ERRATUM_A008997
13 select SYS_FSL_ERRATUM_A009007
14 select SYS_FSL_ERRATUM_A009008
15 select ARCH_EARLY_INIT_R
16 select BOARD_EARLY_INIT_F
18 select SYS_I2C_MXC_I2C1
19 select SYS_I2C_MXC_I2C2
24 select ARMV8_SET_SMPEN
25 select ARM_ERRATA_855873 if !TFABOOT
31 select SYS_FSL_DDR_VER_50
32 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
33 select SYS_FSL_ERRATUM_A008997
34 select SYS_FSL_ERRATUM_A009007
35 select SYS_FSL_ERRATUM_A009008
36 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
37 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
38 select SYS_FSL_ERRATUM_A009798
39 select SYS_FSL_ERRATUM_A009929
40 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
41 select SYS_FSL_ERRATUM_A010315
42 select SYS_FSL_ERRATUM_A010539
43 select SYS_FSL_HAS_DDR3
44 select SYS_FSL_HAS_DDR4
45 select ARCH_EARLY_INIT_R
46 select BOARD_EARLY_INIT_F
48 select SYS_I2C_MXC_I2C1
49 select SYS_I2C_MXC_I2C2
50 select SYS_I2C_MXC_I2C3
51 select SYS_I2C_MXC_I2C4
58 select ARMV8_SET_SMPEN
64 select SYS_FSL_DDR_VER_50
65 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
66 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
67 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
68 select SYS_FSL_ERRATUM_A008997
69 select SYS_FSL_ERRATUM_A009007
70 select SYS_FSL_ERRATUM_A009008
71 select SYS_FSL_ERRATUM_A009798
72 select SYS_FSL_ERRATUM_A009801
73 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
74 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
75 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
76 select SYS_FSL_ERRATUM_A010539
77 select SYS_FSL_HAS_DDR4
79 select ARCH_EARLY_INIT_R
80 select BOARD_EARLY_INIT_F
82 select SYS_I2C_MXC_I2C1
83 select SYS_I2C_MXC_I2C2
84 select SYS_I2C_MXC_I2C3
85 select SYS_I2C_MXC_I2C4
91 select ARMV8_SET_SMPEN
92 select ARM_ERRATA_855873
98 select SYS_FSL_DDR_VER_50
101 select SYS_FSL_ERRATUM_A009803
102 select SYS_FSL_ERRATUM_A009942
103 select SYS_FSL_ERRATUM_A010165
104 select SYS_FSL_ERRATUM_A008511
105 select SYS_FSL_ERRATUM_A008850
106 select SYS_FSL_ERRATUM_A009007
107 select SYS_FSL_HAS_CCI400
108 select SYS_FSL_HAS_DDR4
109 select SYS_FSL_HAS_RGMII
110 select SYS_FSL_HAS_SEC
111 select SYS_FSL_SEC_COMPAT_5
112 select SYS_FSL_SEC_LE
113 select SYS_FSL_SRDS_1
114 select SYS_FSL_SRDS_2
116 select ARCH_EARLY_INIT_R
117 select BOARD_EARLY_INIT_F
119 select SYS_I2C_MXC_I2C1
120 select SYS_I2C_MXC_I2C2
121 select SYS_I2C_MXC_I2C3
122 select SYS_I2C_MXC_I2C4
128 select ARMV8_SET_SMPEN
129 select ARM_ERRATA_826974
130 select ARM_ERRATA_828024
131 select ARM_ERRATA_829520
132 select ARM_ERRATA_833471
134 select SYS_FSL_SRDS_1
135 select SYS_HAS_SERDES
137 select SYS_FSL_DDR_LE
138 select SYS_FSL_DDR_VER_50
139 select SYS_FSL_HAS_CCN504
140 select SYS_FSL_HAS_DP_DDR
141 select SYS_FSL_HAS_SEC
142 select SYS_FSL_HAS_DDR4
143 select SYS_FSL_SEC_COMPAT_5
144 select SYS_FSL_SEC_LE
145 select SYS_FSL_SRDS_2
148 select SYS_FSL_ERRATUM_A008336
149 select SYS_FSL_ERRATUM_A008511
150 select SYS_FSL_ERRATUM_A008514
151 select SYS_FSL_ERRATUM_A008585
152 select SYS_FSL_ERRATUM_A008997
153 select SYS_FSL_ERRATUM_A009007
154 select SYS_FSL_ERRATUM_A009008
155 select SYS_FSL_ERRATUM_A009635
156 select SYS_FSL_ERRATUM_A009663
157 select SYS_FSL_ERRATUM_A009798
158 select SYS_FSL_ERRATUM_A009801
159 select SYS_FSL_ERRATUM_A009803
160 select SYS_FSL_ERRATUM_A009942
161 select SYS_FSL_ERRATUM_A010165
162 select SYS_FSL_ERRATUM_A009203
163 select ARCH_EARLY_INIT_R
164 select BOARD_EARLY_INIT_F
166 select SYS_I2C_MXC_I2C1
167 select SYS_I2C_MXC_I2C2
168 select SYS_I2C_MXC_I2C3
169 select SYS_I2C_MXC_I2C4
170 imply DISTRO_DEFAULTS
175 select ARMV8_SET_SMPEN
178 select SYS_HAS_SERDES
179 select SYS_FSL_SRDS_1
180 select SYS_FSL_SRDS_2
181 select SYS_NXP_SRDS_3
183 select SYS_FSL_DDR_LE
184 select SYS_FSL_DDR_VER_50
187 select SYS_FSL_HAS_RGMII
188 select SYS_FSL_HAS_SEC
189 select SYS_FSL_HAS_CCN508
190 select SYS_FSL_HAS_DDR4
191 select SYS_FSL_SEC_COMPAT_5
192 select SYS_FSL_SEC_LE
193 select ARCH_EARLY_INIT_R
194 select BOARD_EARLY_INIT_F
196 select SYS_I2C_MXC_I2C1
197 select SYS_I2C_MXC_I2C2
198 select SYS_I2C_MXC_I2C3
199 select SYS_I2C_MXC_I2C4
200 select SYS_I2C_MXC_I2C5
201 select SYS_I2C_MXC_I2C6
202 select SYS_I2C_MXC_I2C7
203 select SYS_I2C_MXC_I2C8
204 imply DISTRO_DEFAULTS
211 select SYS_FSL_HAS_CCI400
212 select SYS_FSL_HAS_SEC
213 select SYS_FSL_SEC_COMPAT_5
214 select SYS_FSL_SEC_BE
223 bool "Management Complex network"
224 depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
228 Enable Management Complex (MC) network
230 menu "Layerscape architecture"
231 depends on FSL_LSCH2 || FSL_LSCH3
233 config FSL_PCIE_COMPAT
234 string "PCIe compatible of Kernel DT"
235 depends on PCIE_LAYERSCAPE
236 default "fsl,ls1012a-pcie" if ARCH_LS1012A
237 default "fsl,ls1043a-pcie" if ARCH_LS1043A
238 default "fsl,ls1046a-pcie" if ARCH_LS1046A
239 default "fsl,ls2080a-pcie" if ARCH_LS2080A
240 default "fsl,ls1088a-pcie" if ARCH_LS1088A
241 default "fsl,lx2160a-pcie" if ARCH_LX2160A
243 This compatible is used to find pci controller node in Kernel DT
246 config HAS_FEATURE_GIC64K_ALIGN
248 default y if ARCH_LS1043A
250 config HAS_FEATURE_ENHANCED_MSI
252 default y if ARCH_LS1043A
254 menu "Layerscape PPA"
256 bool "FSL Layerscape PPA firmware support"
257 depends on !ARMV8_PSCI
258 select ARMV8_SEC_FIRMWARE_SUPPORT
259 select SEC_FIRMWARE_ARMV8_PSCI
260 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
262 The FSL Primary Protected Application (PPA) is a software component
263 which is loaded during boot stage, and then remains resident in RAM
264 and runs in the TrustZone after boot.
267 config SPL_FSL_LS_PPA
268 bool "FSL Layerscape PPA firmware support for SPL build"
269 depends on !ARMV8_PSCI
270 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
271 select SEC_FIRMWARE_ARMV8_PSCI
272 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
274 The FSL Primary Protected Application (PPA) is a software component
275 which is loaded during boot stage, and then remains resident in RAM
276 and runs in the TrustZone after boot. This is to load PPA during SPL
277 stage instead of the RAM version of U-Boot. Once PPA is initialized,
278 the rest of U-Boot (including RAM version) runs at EL2.
280 prompt "FSL Layerscape PPA firmware loading-media select"
281 depends on FSL_LS_PPA
282 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
283 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
284 default SYS_LS_PPA_FW_IN_XIP
286 config SYS_LS_PPA_FW_IN_XIP
289 Say Y here if the PPA firmware locate at XIP flash, such
290 as NOR or QSPI flash.
292 config SYS_LS_PPA_FW_IN_MMC
293 bool "eMMC or SD Card"
295 Say Y here if the PPA firmware locate at eMMC/SD card.
297 config SYS_LS_PPA_FW_IN_NAND
300 Say Y here if the PPA firmware locate at NAND flash.
304 config LS_PPA_ESBC_HDR_SIZE
305 hex "Length of PPA ESBC header"
306 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
309 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
310 NAND to memory to validate PPA image.
314 config SYS_FSL_ERRATUM_A008997
315 bool "Workaround for USB PHY erratum A008997"
317 config SYS_FSL_ERRATUM_A009007
320 Workaround for USB PHY erratum A009007
322 config SYS_FSL_ERRATUM_A009008
323 bool "Workaround for USB PHY erratum A009008"
325 config SYS_FSL_ERRATUM_A009798
326 bool "Workaround for USB PHY erratum A009798"
328 config SYS_FSL_ERRATUM_A010315
329 bool "Workaround for PCIe erratum A010315"
331 config SYS_FSL_ERRATUM_A010539
332 bool "Workaround for PIN MUX erratum A010539"
335 int "Maximum number of CPUs permitted for Layerscape"
336 default 4 if ARCH_LS1043A
337 default 4 if ARCH_LS1046A
338 default 16 if ARCH_LS2080A
339 default 8 if ARCH_LS1088A
340 default 16 if ARCH_LX2160A
343 Set this number to the maximum number of possible CPUs in the SoC.
344 SoCs may have multiple clusters with each cluster may have multiple
345 ports. If some ports are reserved but higher ports are used for
346 cores, count the reserved ports. This will allocate enough memory
347 in spin table to properly handle all cores.
352 Enable Freescale Secure Boot feature
355 bool "Init the QSPI AHB bus"
357 The default setting for QSPI AHB bus just support 3bytes addressing.
358 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
359 bus for those flashes to support the full QSPI flash size.
361 config SYS_CCI400_OFFSET
362 hex "Offset for CCI400 base"
363 depends on SYS_FSL_HAS_CCI400
364 default 0x3090000 if ARCH_LS1088A
365 default 0x180000 if FSL_LSCH2
367 Offset for CCI400 base
368 CCI400 base addr = CCSRBAR + CCI400_OFFSET
370 config SYS_FSL_IFC_BANK_COUNT
371 int "Maximum banks of Integrated flash controller"
372 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
373 default 4 if ARCH_LS1043A
374 default 4 if ARCH_LS1046A
375 default 8 if ARCH_LS2080A || ARCH_LS1088A
377 config SYS_FSL_HAS_CCI400
380 config SYS_FSL_HAS_CCN504
383 config SYS_FSL_HAS_CCN508
386 config SYS_FSL_HAS_DP_DDR
389 config SYS_FSL_SRDS_1
392 config SYS_FSL_SRDS_2
395 config SYS_NXP_SRDS_3
398 config SYS_HAS_SERDES
409 menu "Layerscape clock tree configuration"
410 depends on FSL_LSCH2 || FSL_LSCH3
413 bool "Enable clock tree initialization"
416 config CLUSTER_CLK_FREQ
417 int "Reference clock of core cluster"
418 depends on ARCH_LS1012A
421 This number is the reference clock frequency of core PLL.
422 For most platforms, the core PLL and Platform PLL have the same
423 reference clock, but for some platforms, LS1012A for instance,
424 they are provided sepatately.
426 config SYS_FSL_PCLK_DIV
427 int "Platform clock divider"
428 default 1 if ARCH_LS1043A
429 default 1 if ARCH_LS1046A
430 default 1 if ARCH_LS1088A
433 This is the divider that is used to derive Platform clock from
434 Platform PLL, in another word:
435 Platform_clk = Platform_PLL_freq / this_divider
437 config SYS_FSL_DSPI_CLK_DIV
438 int "DSPI clock divider"
439 default 1 if ARCH_LS1043A
442 This is the divider that is used to derive DSPI clock from Platform
443 clock, in another word DSPI_clk = Platform_clk / this_divider.
445 config SYS_FSL_DUART_CLK_DIV
446 int "DUART clock divider"
447 default 1 if ARCH_LS1043A
448 default 4 if ARCH_LX2160A
451 This is the divider that is used to derive DUART clock from Platform
452 clock, in another word DUART_clk = Platform_clk / this_divider.
454 config SYS_FSL_I2C_CLK_DIV
455 int "I2C clock divider"
456 default 1 if ARCH_LS1043A
459 This is the divider that is used to derive I2C clock from Platform
460 clock, in another word I2C_clk = Platform_clk / this_divider.
462 config SYS_FSL_IFC_CLK_DIV
463 int "IFC clock divider"
464 default 1 if ARCH_LS1043A
467 This is the divider that is used to derive IFC clock from Platform
468 clock, in another word IFC_clk = Platform_clk / this_divider.
470 config SYS_FSL_LPUART_CLK_DIV
471 int "LPUART clock divider"
472 default 1 if ARCH_LS1043A
475 This is the divider that is used to derive LPUART clock from Platform
476 clock, in another word LPUART_clk = Platform_clk / this_divider.
478 config SYS_FSL_SDHC_CLK_DIV
479 int "SDHC clock divider"
480 default 1 if ARCH_LS1043A
481 default 1 if ARCH_LS1012A
484 This is the divider that is used to derive SDHC clock from Platform
485 clock, in another word SDHC_clk = Platform_clk / this_divider.
487 config SYS_FSL_QMAN_CLK_DIV
488 int "QMAN clock divider"
489 default 1 if ARCH_LS1043A
492 This is the divider that is used to derive QMAN clock from Platform
493 clock, in another word QMAN_clk = Platform_clk / this_divider.
499 Reserve memory from the top, tracked by gd->arch.resv_ram. This
500 reserved RAM can be used by special driver that resides in memory
501 after U-Boot exits. It's up to implementation to allocate and allow
502 access to this reserved memory. For example, the reserved RAM can
503 be at the high end of physical memory. The reserve RAM may be
504 excluded from memory bank(s) passed to OS, or marked as reserved.
509 Ethernet controller 1, this is connected to
510 MAC17 for LX2160A or to MAC3 for other SoCs
511 Provides DPAA2 capabilities
516 Ethernet controller 2, this is connected to
517 MAC18 for LX2160A or to MAC4 for other SoCs
518 Provides DPAA2 capabilities
520 config SYS_FSL_ERRATUM_A008336
523 config SYS_FSL_ERRATUM_A008514
526 config SYS_FSL_ERRATUM_A008585
529 config SYS_FSL_ERRATUM_A008850
532 config SYS_FSL_ERRATUM_A009203
535 config SYS_FSL_ERRATUM_A009635
538 config SYS_FSL_ERRATUM_A009660
541 config SYS_FSL_ERRATUM_A009929
545 config SYS_FSL_HAS_RGMII
547 depends on SYS_FSL_EC1 || SYS_FSL_EC2
550 config SYS_MC_RSV_MEM_ALIGN
551 hex "Management Complex reserved memory alignment"
553 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
555 Reserved memory needs to be aligned for MC to use. Default value
559 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
561 config HAS_FSL_XHCI_USB
563 default y if ARCH_LS1043A || ARCH_LS1046A
565 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
566 pins, select it when the pins are assigned to USB.
569 bool "Support for booting from TFA"
572 Enabling this will make a U-Boot binary that is capable of being