4 select ARM_ERRATA_855873 if !TFABOOT
8 select SKIP_LOWLEVEL_INIT
13 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
14 select SYS_FSL_ERRATUM_A009798
15 select SYS_FSL_ERRATUM_A008997
16 select SYS_FSL_ERRATUM_A009007
17 select SYS_FSL_ERRATUM_A009008
18 select ARCH_EARLY_INIT_R
19 select BOARD_EARLY_INIT_F
21 select SYS_I2C_MXC_I2C1 if !DM_I2C
22 select SYS_I2C_MXC_I2C2 if !DM_I2C
28 select ARMV8_SET_SMPEN
29 select ESBC_HDR_LS if CHAIN_OF_TRUST
34 select SYS_FSL_HAS_CCI400
39 select SYS_FSL_DDR_VER_50
40 select SYS_FSL_HAS_DDR3
41 select SYS_FSL_HAS_DDR4
42 select SYS_FSL_HAS_SEC
43 select SYS_FSL_SEC_COMPAT_5
47 select ARCH_EARLY_INIT_R
48 select BOARD_EARLY_INIT_F
50 select SYS_FSL_ERRATUM_A008997
51 select SYS_FSL_ERRATUM_A009007
52 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
53 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
54 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
55 select SYS_FSL_ERRATUM_A050382
56 select SYS_FSL_ERRATUM_A011334
57 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
58 select RESV_RAM if GIC_V3_ITS
59 select SYS_HAS_ARMV8_SECURE_BASE
64 select ARMV8_SET_SMPEN
65 select ARM_ERRATA_855873 if !TFABOOT
66 select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
70 select HAS_FSL_XHCI_USB if USB_HOST
71 select SKIP_LOWLEVEL_INIT
76 select SYS_FSL_DDR_VER_50
77 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
78 select SYS_FSL_ERRATUM_A008997
79 select SYS_FSL_ERRATUM_A009008
80 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
81 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
82 select SYS_FSL_ERRATUM_A009798
83 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
84 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
85 select SYS_FSL_ERRATUM_A010539
86 select SYS_FSL_HAS_DDR3
87 select SYS_FSL_HAS_DDR4
88 select ARCH_EARLY_INIT_R
89 select BOARD_EARLY_INIT_F
91 select SYS_I2C_MXC_I2C1 if !DM_I2C
92 select SYS_I2C_MXC_I2C2 if !DM_I2C
93 select SYS_I2C_MXC_I2C3 if !DM_I2C
94 select SYS_I2C_MXC_I2C4 if !DM_I2C
95 select SYS_HAS_ARMV8_SECURE_BASE
101 select ARMV8_SET_SMPEN
102 select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
103 select FSL_LAYERSCAPE
106 select HAS_FSL_XHCI_USB if USB_HOST
107 select SKIP_LOWLEVEL_INIT
108 select SYS_FSL_SRDS_1
109 select SYS_HAS_SERDES
111 select SYS_FSL_DDR_BE
112 select SYS_FSL_DDR_VER_50
113 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
114 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
115 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
116 select SYS_FSL_ERRATUM_A008997
117 select SYS_FSL_ERRATUM_A009008
118 select SYS_FSL_ERRATUM_A009798
119 select SYS_FSL_ERRATUM_A009801
120 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
121 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
122 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
123 select SYS_FSL_ERRATUM_A010539
124 select SYS_FSL_HAS_DDR4
125 select SYS_FSL_SRDS_2
126 select ARCH_EARLY_INIT_R
127 select BOARD_EARLY_INIT_F
129 select SYS_I2C_MXC_I2C1 if !DM_I2C
130 select SYS_I2C_MXC_I2C2 if !DM_I2C
131 select SYS_I2C_MXC_I2C3 if !DM_I2C
132 select SYS_I2C_MXC_I2C4 if !DM_I2C
136 imply SPL_SYS_I2C_LEGACY
140 select ARMV8_SET_SMPEN
141 select ARM_ERRATA_855873 if !TFABOOT
142 select ESBC_HDR_LS if CHAIN_OF_TRUST
144 select FSL_LAYERSCAPE
147 select SKIP_LOWLEVEL_INIT
148 select SYS_FSL_SRDS_1
149 select SYS_HAS_SERDES
151 select SYS_FSL_DDR_LE
152 select SYS_FSL_DDR_VER_50
155 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
156 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
157 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
158 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
159 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
160 select SYS_FSL_ERRATUM_A009007
161 select SYS_FSL_HAS_CCI400
162 select SYS_FSL_HAS_DDR4
163 select SYS_FSL_HAS_RGMII
164 select SYS_FSL_HAS_SEC
165 select SYS_FSL_SEC_COMPAT_5
166 select SYS_FSL_SEC_LE
167 select SYS_FSL_SRDS_1
168 select SYS_FSL_SRDS_2
171 select FSL_TZPC_BP147
172 select ARCH_EARLY_INIT_R
173 select BOARD_EARLY_INIT_F
175 select SYS_I2C_MXC_I2C1 if !TFABOOT
176 select SYS_I2C_MXC_I2C2 if !TFABOOT
177 select SYS_I2C_MXC_I2C3 if !TFABOOT
178 select SYS_I2C_MXC_I2C4 if !TFABOOT
179 select RESV_RAM if GIC_V3_ITS
182 imply SPL_SYS_I2C_LEGACY
187 select ARMV8_SET_SMPEN
188 select ARM_ERRATA_826974
189 select ARM_ERRATA_828024
190 select ARM_ERRATA_829520
191 select ARM_ERRATA_833471
192 select ESBC_HDR_LS if CHAIN_OF_TRUST
194 select FSL_LAYERSCAPE
197 select SKIP_LOWLEVEL_INIT
198 select SYS_FSL_SRDS_1
199 select SYS_HAS_SERDES
201 select SYS_FSL_DDR_LE
202 select SYS_FSL_DDR_VER_50
203 select SYS_FSL_HAS_CCN504
204 select SYS_FSL_HAS_DP_DDR
205 select SYS_FSL_HAS_SEC
206 select SYS_FSL_HAS_DDR4
207 select SYS_FSL_SEC_COMPAT_5
208 select SYS_FSL_SEC_LE
209 select SYS_FSL_SRDS_2
213 select FSL_TZPC_BP147
214 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
215 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
216 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
217 select SYS_FSL_ERRATUM_A008585
218 select SYS_FSL_ERRATUM_A008997
219 select SYS_FSL_ERRATUM_A009007
220 select SYS_FSL_ERRATUM_A009008
221 select SYS_FSL_ERRATUM_A009635
222 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
223 select SYS_FSL_ERRATUM_A009798
224 select SYS_FSL_ERRATUM_A009801
225 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
226 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
227 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
228 select SYS_FSL_ERRATUM_A009203
229 select ARCH_EARLY_INIT_R
230 select BOARD_EARLY_INIT_F
232 select SYS_I2C_MXC_I2C1 if !TFABOOT
233 select SYS_I2C_MXC_I2C2 if !TFABOOT
234 select SYS_I2C_MXC_I2C3 if !TFABOOT
235 select SYS_I2C_MXC_I2C4 if !TFABOOT
236 select RESV_RAM if GIC_V3_ITS
237 imply DISTRO_DEFAULTS
240 imply SPL_SYS_I2C_LEGACY
244 select ARMV8_SET_SMPEN
245 select ESBC_HDR_LS if CHAIN_OF_TRUST
247 select FSL_DDR_INTERACTIVE
248 select FSL_LAYERSCAPE
250 select FSL_TZPC_BP147
253 select SYS_HAS_SERDES
254 select SYS_FSL_SRDS_1
255 select SYS_FSL_SRDS_2
257 select SYS_FSL_DDR_LE
258 select SYS_FSL_DDR_VER_50
261 select SYS_FSL_ERRATUM_A050204
262 select SYS_FSL_ERRATUM_A011334
263 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
264 select SYS_FSL_HAS_RGMII
265 select SYS_FSL_HAS_SEC
266 select SYS_FSL_HAS_CCN508
267 select SYS_FSL_HAS_DDR4
268 select SYS_FSL_SEC_COMPAT_5
269 select SYS_FSL_SEC_LE
270 select SYS_PCI_64BIT if PCI
271 select ARCH_EARLY_INIT_R
272 select BOARD_EARLY_INIT_F
274 select RESV_RAM if GIC_V3_ITS
275 imply DISTRO_DEFAULTS
279 imply SPL_SYS_I2C_LEGACY
283 select ARMV8_SET_SMPEN
284 select ESBC_HDR_LS if CHAIN_OF_TRUST
286 select FSL_DDR_INTERACTIVE
287 select FSL_LAYERSCAPE
289 select FSL_TZPC_BP147
291 select HAS_FSL_XHCI_USB if USB_HOST
293 select SYS_HAS_SERDES
294 select SYS_FSL_SRDS_1
295 select SYS_FSL_SRDS_2
296 select SYS_NXP_SRDS_3
298 select SYS_FSL_DDR_LE
299 select SYS_FSL_DDR_VER_50
302 select SYS_FSL_ERRATUM_A050204
303 select SYS_FSL_ERRATUM_A011334
304 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
305 select SYS_FSL_HAS_RGMII
306 select SYS_FSL_HAS_SEC
307 select SYS_FSL_HAS_CCN508
308 select SYS_FSL_HAS_DDR4
309 select SYS_FSL_SEC_COMPAT_5
310 select SYS_FSL_SEC_LE
311 select SYS_PCI_64BIT if PCI
312 select ARCH_EARLY_INIT_R
313 select BOARD_EARLY_INIT_F
315 select RESV_RAM if GIC_V3_ITS
316 imply DISTRO_DEFAULTS
321 imply SPL_SYS_I2C_LEGACY
325 select SKIP_LOWLEVEL_INIT
326 select SYS_FSL_CCSR_GUR_BE
327 select SYS_FSL_CCSR_SCFG_BE
328 select SYS_FSL_ESDHC_BE
329 select SYS_FSL_IFC_BE
330 select SYS_FSL_PEX_LUT_BE
331 select SYS_FSL_HAS_CCI400
332 select SYS_FSL_HAS_SEC
333 select SYS_FSL_SEC_COMPAT_5
334 select SYS_FSL_SEC_BE
337 select ARCH_MISC_INIT
338 select SYS_FSL_CCSR_GUR_LE
339 select SYS_FSL_CCSR_SCFG_LE
340 select SYS_FSL_ESDHC_LE
341 select SYS_FSL_IFC_LE
342 select SYS_FSL_PEX_LUT_LE
348 config SYS_FSL_CCSR_GUR_BE
351 config SYS_FSL_CCSR_SCFG_BE
354 config SYS_FSL_PEX_LUT_BE
357 config SYS_FSL_CCSR_GUR_LE
360 config SYS_FSL_CCSR_SCFG_LE
363 config SYS_FSL_ESDHC_LE
366 config SYS_FSL_IFC_LE
369 config SYS_FSL_PEX_LUT_LE
372 menu "Layerscape architecture"
373 depends on FSL_LSCH2 || FSL_LSCH3
375 config FSL_LAYERSCAPE
379 config HAS_FEATURE_GIC64K_ALIGN
381 default y if ARCH_LS1043A
383 config HAS_FEATURE_ENHANCED_MSI
385 default y if ARCH_LS1043A
387 menu "Layerscape PPA"
389 bool "FSL Layerscape PPA firmware support"
390 depends on !ARMV8_PSCI
391 select ARMV8_SEC_FIRMWARE_SUPPORT
392 select SEC_FIRMWARE_ARMV8_PSCI
393 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
395 The FSL Primary Protected Application (PPA) is a software component
396 which is loaded during boot stage, and then remains resident in RAM
397 and runs in the TrustZone after boot.
400 config SPL_FSL_LS_PPA
401 bool "FSL Layerscape PPA firmware support for SPL build"
402 depends on !ARMV8_PSCI
403 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
404 select SEC_FIRMWARE_ARMV8_PSCI
405 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
407 The FSL Primary Protected Application (PPA) is a software component
408 which is loaded during boot stage, and then remains resident in RAM
409 and runs in the TrustZone after boot. This is to load PPA during SPL
410 stage instead of the RAM version of U-Boot. Once PPA is initialized,
411 the rest of U-Boot (including RAM version) runs at EL2.
413 prompt "FSL Layerscape PPA firmware loading-media select"
414 depends on FSL_LS_PPA
415 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
416 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
417 default SYS_LS_PPA_FW_IN_XIP
419 config SYS_LS_PPA_FW_IN_XIP
422 Say Y here if the PPA firmware locate at XIP flash, such
423 as NOR or QSPI flash.
425 config SYS_LS_PPA_FW_IN_MMC
426 bool "eMMC or SD Card"
428 Say Y here if the PPA firmware locate at eMMC/SD card.
430 config SYS_LS_PPA_FW_IN_NAND
433 Say Y here if the PPA firmware locate at NAND flash.
437 config LS_PPA_ESBC_HDR_SIZE
438 hex "Length of PPA ESBC header"
439 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
442 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
443 NAND to memory to validate PPA image.
447 config SYS_FSL_ERRATUM_A008997
448 bool "Workaround for USB PHY erratum A008997"
450 config SYS_FSL_ERRATUM_A009007
453 Workaround for USB PHY erratum A009007
455 config SYS_FSL_ERRATUM_A009008
456 bool "Workaround for USB PHY erratum A009008"
458 config SYS_FSL_ERRATUM_A009798
459 bool "Workaround for USB PHY erratum A009798"
461 config SYS_FSL_ERRATUM_A050204
462 bool "Workaround for USB PHY erratum A050204"
464 USB3.0 Receiver needs to enable fixed equalization
465 for each of PHY instances in an SOC. This is similar
466 to erratum A-009007, but this one is for LX2160A and LX2162A,
467 and the register value is different.
469 config SYS_FSL_ERRATUM_A010315
470 bool "Workaround for PCIe erratum A010315"
472 config SYS_FSL_ERRATUM_A010539
473 bool "Workaround for PIN MUX erratum A010539"
476 int "Maximum number of CPUs permitted for Layerscape"
477 default 2 if ARCH_LS1028A
478 default 4 if ARCH_LS1043A
479 default 4 if ARCH_LS1046A
480 default 16 if ARCH_LS2080A
481 default 8 if ARCH_LS1088A
482 default 16 if ARCH_LX2160A
483 default 16 if ARCH_LX2162A
486 Set this number to the maximum number of possible CPUs in the SoC.
487 SoCs may have multiple clusters with each cluster may have multiple
488 ports. If some ports are reserved but higher ports are used for
489 cores, count the reserved ports. This will allocate enough memory
490 in spin table to properly handle all cores.
493 bool "Fan controller"
495 Enable the EMC2305 fan controller for configuration of fan
499 bool "Init the QSPI AHB bus"
501 The default setting for QSPI AHB bus just support 3bytes addressing.
502 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
503 bus for those flashes to support the full QSPI flash size.
505 config FSPI_AHB_EN_4BYTE
506 bool "Enable 4-byte Fast Read command for AHB mode"
508 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
509 But some FlexSPI flash sizes are up to 64MBytes.
510 This flag enables fast read command for AHB mode and modifies required
511 LUT to support full FlexSPI flash.
513 config SYS_CCI400_OFFSET
514 hex "Offset for CCI400 base"
515 depends on SYS_FSL_HAS_CCI400
516 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
517 default 0x180000 if FSL_LSCH2
519 Offset for CCI400 base
520 CCI400 base addr = CCSRBAR + CCI400_OFFSET
522 config SYS_FSL_IFC_BANK_COUNT
523 int "Maximum banks of Integrated flash controller"
524 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
525 default 4 if ARCH_LS1043A
526 default 4 if ARCH_LS1046A
527 default 8 if ARCH_LS2080A || ARCH_LS1088A
529 config SYS_FSL_HAS_CCI400
532 config SYS_FSL_HAS_CCN504
535 config SYS_FSL_HAS_CCN508
538 config SYS_FSL_HAS_DP_DDR
541 Defines the SoC has DP-DDR used for DPAA.
545 depends on SYS_FSL_HAS_DP_DDR
546 default 2 if ARCH_LS2080A
548 config DP_DDR_DIMM_SLOTS_PER_CTLR
550 depends on SYS_FSL_HAS_DP_DDR
551 default 1 if ARCH_LS2080A
553 config DP_DDR_NUM_CTRLS
555 depends on SYS_FSL_HAS_DP_DDR
556 default 1 if ARCH_LS2080A
558 config SYS_DP_DDR_BASE
560 depends on SYS_FSL_HAS_DP_DDR
561 default 0x6000000000 if ARCH_LS2080A
563 config SYS_DP_DDR_BASE_PHY
565 depends on SYS_FSL_HAS_DP_DDR
566 default 0 if ARCH_LS2080A
568 DDR controller uses this value as the base address for binding.
569 It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
571 config SYS_FSL_SRDS_1
574 config SYS_FSL_SRDS_2
577 config SYS_NXP_SRDS_3
580 config SYS_HAS_SERDES
592 config FSL_TZPC_BP147
596 menu "Layerscape clock tree configuration"
597 depends on FSL_LSCH2 || FSL_LSCH3
599 config CLUSTER_CLK_FREQ
600 int "Reference clock of core cluster"
601 depends on ARCH_LS1012A
604 This number is the reference clock frequency of core PLL.
605 For most platforms, the core PLL and Platform PLL have the same
606 reference clock, but for some platforms, LS1012A for instance,
607 they are provided sepatately.
609 config SYS_FSL_PCLK_DIV
610 int "Platform clock divider"
611 default 1 if ARCH_LS1028A
612 default 1 if ARCH_LS1043A
613 default 1 if ARCH_LS1046A
614 default 1 if ARCH_LS1088A
617 This is the divider that is used to derive Platform clock from
618 Platform PLL, in another word:
619 Platform_clk = Platform_PLL_freq / this_divider
621 config SYS_FSL_DSPI_CLK_DIV
622 int "DSPI clock divider"
623 default 1 if ARCH_LS1043A
626 This is the divider that is used to derive DSPI clock from Platform
627 clock, in another word DSPI_clk = Platform_clk / this_divider.
629 config SYS_FSL_DUART_CLK_DIV
630 int "DUART clock divider"
631 default 1 if ARCH_LS1043A
632 default 4 if ARCH_LX2160A
633 default 4 if ARCH_LX2162A
636 This is the divider that is used to derive DUART clock from Platform
637 clock, in another word DUART_clk = Platform_clk / this_divider.
639 config SYS_FSL_I2C_CLK_DIV
640 int "I2C clock divider"
641 default 1 if ARCH_LS1043A
642 default 4 if ARCH_LS1012A
643 default 4 if ARCH_LS1028A
644 default 8 if ARCH_LX2160A
645 default 8 if ARCH_LX2162A
646 default 8 if ARCH_LS1088A
649 This is the divider that is used to derive I2C clock from Platform
650 clock, in another word I2C_clk = Platform_clk / this_divider.
652 config SYS_FSL_IFC_CLK_DIV
653 int "IFC clock divider"
654 default 1 if ARCH_LS1043A
655 default 4 if ARCH_LS1012A
656 default 4 if ARCH_LS1028A
657 default 8 if ARCH_LX2160A
658 default 8 if ARCH_LX2162A
659 default 8 if ARCH_LS1088A
662 This is the divider that is used to derive IFC clock from Platform
663 clock, in another word IFC_clk = Platform_clk / this_divider.
665 config SYS_FSL_LPUART_CLK_DIV
666 int "LPUART clock divider"
667 default 1 if ARCH_LS1043A
670 This is the divider that is used to derive LPUART clock from Platform
671 clock, in another word LPUART_clk = Platform_clk / this_divider.
673 config SYS_FSL_SDHC_CLK_DIV
674 int "SDHC clock divider"
675 default 1 if ARCH_LS1043A
676 default 1 if ARCH_LS1012A
679 This is the divider that is used to derive SDHC clock from Platform
680 clock, in another word SDHC_clk = Platform_clk / this_divider.
682 config SYS_FSL_QMAN_CLK_DIV
683 int "QMAN clock divider"
684 default 1 if ARCH_LS1043A
687 This is the divider that is used to derive QMAN clock from Platform
688 clock, in another word QMAN_clk = Platform_clk / this_divider.
694 Reserve memory from the top, tracked by gd->arch.resv_ram. This
695 reserved RAM can be used by special driver that resides in memory
696 after U-Boot exits. It's up to implementation to allocate and allow
697 access to this reserved memory. For example, the reserved RAM can
698 be at the high end of physical memory. The reserve RAM may be
699 excluded from memory bank(s) passed to OS, or marked as reserved.
704 Ethernet controller 1, this is connected to
705 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
706 Provides DPAA2 capabilities
711 Ethernet controller 2, this is connected to
712 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
713 Provides DPAA2 capabilities
715 config SYS_FSL_ERRATUM_A008336
718 config SYS_FSL_ERRATUM_A008514
721 config SYS_FSL_ERRATUM_A008585
724 config SYS_FSL_ERRATUM_A008850
727 config SYS_FSL_ERRATUM_A009203
730 config SYS_FSL_ERRATUM_A009635
733 config SYS_FSL_ERRATUM_A009660
736 config SYS_FSL_ERRATUM_A050382
739 config SYS_FSL_HAS_RGMII
741 depends on SYS_FSL_EC1 || SYS_FSL_EC2
743 config HAS_FSL_XHCI_USB
746 For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
747 pins, select it when the pins are assigned to USB.
749 config SYS_FSL_BOOTROM_BASE
754 config SYS_FSL_BOOTROM_SIZE