4 select ARM_ERRATA_855873 if !TFABOOT
8 select SKIP_LOWLEVEL_INIT
13 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
14 select SYS_FSL_ERRATUM_A009798
15 select SYS_FSL_ERRATUM_A008997
16 select SYS_FSL_ERRATUM_A009007
17 select SYS_FSL_ERRATUM_A009008
18 select ARCH_EARLY_INIT_R
19 select BOARD_EARLY_INIT_F
21 select SYS_I2C_MXC_I2C1 if !DM_I2C
22 select SYS_I2C_MXC_I2C2 if !DM_I2C
27 select ARMV8_SET_SMPEN
32 select SYS_FSL_HAS_CCI400
37 select SYS_FSL_DDR_VER_50
38 select SYS_FSL_HAS_DDR3
39 select SYS_FSL_HAS_DDR4
40 select SYS_FSL_HAS_SEC
41 select SYS_FSL_SEC_COMPAT_5
44 select ARCH_EARLY_INIT_R
45 select BOARD_EARLY_INIT_F
47 select SYS_FSL_ERRATUM_A008997
48 select SYS_FSL_ERRATUM_A009007
49 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
50 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
51 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
52 select SYS_FSL_ERRATUM_A050382
53 select SYS_FSL_ERRATUM_A011334
54 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
55 select RESV_RAM if GIC_V3_ITS
60 select ARMV8_SET_SMPEN
61 select ARM_ERRATA_855873 if !TFABOOT
65 select HAS_FSL_XHCI_USB if USB_HOST
66 select SKIP_LOWLEVEL_INIT
71 select SYS_FSL_DDR_VER_50
72 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
73 select SYS_FSL_ERRATUM_A008997
74 select SYS_FSL_ERRATUM_A009007
75 select SYS_FSL_ERRATUM_A009008
76 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
77 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
78 select SYS_FSL_ERRATUM_A009798
79 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
80 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
81 select SYS_FSL_ERRATUM_A010539
82 select SYS_FSL_HAS_DDR3
83 select SYS_FSL_HAS_DDR4
84 select ARCH_EARLY_INIT_R
85 select BOARD_EARLY_INIT_F
87 select SYS_I2C_MXC_I2C1 if !DM_I2C
88 select SYS_I2C_MXC_I2C2 if !DM_I2C
89 select SYS_I2C_MXC_I2C3 if !DM_I2C
90 select SYS_I2C_MXC_I2C4 if !DM_I2C
96 select ARMV8_SET_SMPEN
100 select HAS_FSL_XHCI_USB if USB_HOST
101 select SKIP_LOWLEVEL_INIT
102 select SYS_FSL_SRDS_1
103 select SYS_HAS_SERDES
105 select SYS_FSL_DDR_BE
106 select SYS_FSL_DDR_VER_50
107 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
108 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
109 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
110 select SYS_FSL_ERRATUM_A008997
111 select SYS_FSL_ERRATUM_A009007
112 select SYS_FSL_ERRATUM_A009008
113 select SYS_FSL_ERRATUM_A009798
114 select SYS_FSL_ERRATUM_A009801
115 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
116 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
117 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
118 select SYS_FSL_ERRATUM_A010539
119 select SYS_FSL_HAS_DDR4
120 select SYS_FSL_SRDS_2
121 select ARCH_EARLY_INIT_R
122 select BOARD_EARLY_INIT_F
124 select SYS_I2C_MXC_I2C1 if !DM_I2C
125 select SYS_I2C_MXC_I2C2 if !DM_I2C
126 select SYS_I2C_MXC_I2C3 if !DM_I2C
127 select SYS_I2C_MXC_I2C4 if !DM_I2C
131 imply SPL_SYS_I2C_LEGACY
135 select ARMV8_SET_SMPEN
136 select ARM_ERRATA_855873 if !TFABOOT
137 select FSL_LAYERSCAPE
140 select SKIP_LOWLEVEL_INIT
141 select SYS_FSL_SRDS_1
142 select SYS_HAS_SERDES
144 select SYS_FSL_DDR_LE
145 select SYS_FSL_DDR_VER_50
148 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
149 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
150 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
151 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
152 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
153 select SYS_FSL_ERRATUM_A009007
154 select SYS_FSL_HAS_CCI400
155 select SYS_FSL_HAS_DDR4
156 select SYS_FSL_HAS_RGMII
157 select SYS_FSL_HAS_SEC
158 select SYS_FSL_SEC_COMPAT_5
159 select SYS_FSL_SEC_LE
160 select SYS_FSL_SRDS_1
161 select SYS_FSL_SRDS_2
164 select FSL_TZPC_BP147
165 select ARCH_EARLY_INIT_R
166 select BOARD_EARLY_INIT_F
168 select SYS_I2C_MXC_I2C1 if !TFABOOT
169 select SYS_I2C_MXC_I2C2 if !TFABOOT
170 select SYS_I2C_MXC_I2C3 if !TFABOOT
171 select SYS_I2C_MXC_I2C4 if !TFABOOT
172 select RESV_RAM if GIC_V3_ITS
175 imply SPL_SYS_I2C_LEGACY
180 select ARMV8_SET_SMPEN
181 select ARM_ERRATA_826974
182 select ARM_ERRATA_828024
183 select ARM_ERRATA_829520
184 select ARM_ERRATA_833471
185 select FSL_LAYERSCAPE
188 select SKIP_LOWLEVEL_INIT
189 select SYS_FSL_SRDS_1
190 select SYS_HAS_SERDES
192 select SYS_FSL_DDR_LE
193 select SYS_FSL_DDR_VER_50
194 select SYS_FSL_HAS_CCN504
195 select SYS_FSL_HAS_DP_DDR
196 select SYS_FSL_HAS_SEC
197 select SYS_FSL_HAS_DDR4
198 select SYS_FSL_SEC_COMPAT_5
199 select SYS_FSL_SEC_LE
200 select SYS_FSL_SRDS_2
204 select FSL_TZPC_BP147
205 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
206 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
207 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
208 select SYS_FSL_ERRATUM_A008585
209 select SYS_FSL_ERRATUM_A008997
210 select SYS_FSL_ERRATUM_A009007
211 select SYS_FSL_ERRATUM_A009008
212 select SYS_FSL_ERRATUM_A009635
213 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
214 select SYS_FSL_ERRATUM_A009798
215 select SYS_FSL_ERRATUM_A009801
216 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
217 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
218 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
219 select SYS_FSL_ERRATUM_A009203
220 select ARCH_EARLY_INIT_R
221 select BOARD_EARLY_INIT_F
223 select SYS_I2C_MXC_I2C1 if !TFABOOT
224 select SYS_I2C_MXC_I2C2 if !TFABOOT
225 select SYS_I2C_MXC_I2C3 if !TFABOOT
226 select SYS_I2C_MXC_I2C4 if !TFABOOT
227 select RESV_RAM if GIC_V3_ITS
228 imply DISTRO_DEFAULTS
231 imply SPL_SYS_I2C_LEGACY
235 select ARMV8_SET_SMPEN
236 select FSL_LAYERSCAPE
240 select SYS_HAS_SERDES
241 select SYS_FSL_SRDS_1
242 select SYS_FSL_SRDS_2
244 select SYS_FSL_DDR_LE
245 select SYS_FSL_DDR_VER_50
248 select SYS_FSL_ERRATUM_A050204
249 select SYS_FSL_ERRATUM_A011334
250 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
251 select SYS_FSL_HAS_RGMII
252 select SYS_FSL_HAS_SEC
253 select SYS_FSL_HAS_CCN508
254 select SYS_FSL_HAS_DDR4
255 select SYS_FSL_SEC_COMPAT_5
256 select SYS_FSL_SEC_LE
257 select ARCH_EARLY_INIT_R
258 select BOARD_EARLY_INIT_F
260 select RESV_RAM if GIC_V3_ITS
261 imply DISTRO_DEFAULTS
265 imply SPL_SYS_I2C_LEGACY
269 select ARMV8_SET_SMPEN
270 select FSL_LAYERSCAPE
273 select HAS_FSL_XHCI_USB if USB_HOST
275 select SYS_HAS_SERDES
276 select SYS_FSL_SRDS_1
277 select SYS_FSL_SRDS_2
278 select SYS_NXP_SRDS_3
280 select SYS_FSL_DDR_LE
281 select SYS_FSL_DDR_VER_50
284 select SYS_FSL_ERRATUM_A050204
285 select SYS_FSL_ERRATUM_A011334
286 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
287 select SYS_FSL_HAS_RGMII
288 select SYS_FSL_HAS_SEC
289 select SYS_FSL_HAS_CCN508
290 select SYS_FSL_HAS_DDR4
291 select SYS_FSL_SEC_COMPAT_5
292 select SYS_FSL_SEC_LE
293 select ARCH_EARLY_INIT_R
294 select BOARD_EARLY_INIT_F
296 select RESV_RAM if GIC_V3_ITS
297 imply DISTRO_DEFAULTS
302 imply SPL_SYS_I2C_LEGACY
306 select SKIP_LOWLEVEL_INIT
307 select SYS_FSL_HAS_CCI400
308 select SYS_FSL_HAS_SEC
309 select SYS_FSL_SEC_COMPAT_5
310 select SYS_FSL_SEC_BE
313 select ARCH_MISC_INIT
319 menu "Layerscape architecture"
320 depends on FSL_LSCH2 || FSL_LSCH3
322 config FSL_LAYERSCAPE
325 config HAS_FEATURE_GIC64K_ALIGN
327 default y if ARCH_LS1043A
329 config HAS_FEATURE_ENHANCED_MSI
331 default y if ARCH_LS1043A
333 menu "Layerscape PPA"
335 bool "FSL Layerscape PPA firmware support"
336 depends on !ARMV8_PSCI
337 select ARMV8_SEC_FIRMWARE_SUPPORT
338 select SEC_FIRMWARE_ARMV8_PSCI
339 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
341 The FSL Primary Protected Application (PPA) is a software component
342 which is loaded during boot stage, and then remains resident in RAM
343 and runs in the TrustZone after boot.
346 config SPL_FSL_LS_PPA
347 bool "FSL Layerscape PPA firmware support for SPL build"
348 depends on !ARMV8_PSCI
349 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
350 select SEC_FIRMWARE_ARMV8_PSCI
351 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
353 The FSL Primary Protected Application (PPA) is a software component
354 which is loaded during boot stage, and then remains resident in RAM
355 and runs in the TrustZone after boot. This is to load PPA during SPL
356 stage instead of the RAM version of U-Boot. Once PPA is initialized,
357 the rest of U-Boot (including RAM version) runs at EL2.
359 prompt "FSL Layerscape PPA firmware loading-media select"
360 depends on FSL_LS_PPA
361 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
362 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
363 default SYS_LS_PPA_FW_IN_XIP
365 config SYS_LS_PPA_FW_IN_XIP
368 Say Y here if the PPA firmware locate at XIP flash, such
369 as NOR or QSPI flash.
371 config SYS_LS_PPA_FW_IN_MMC
372 bool "eMMC or SD Card"
374 Say Y here if the PPA firmware locate at eMMC/SD card.
376 config SYS_LS_PPA_FW_IN_NAND
379 Say Y here if the PPA firmware locate at NAND flash.
383 config LS_PPA_ESBC_HDR_SIZE
384 hex "Length of PPA ESBC header"
385 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
388 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
389 NAND to memory to validate PPA image.
393 config SYS_FSL_ERRATUM_A008997
394 bool "Workaround for USB PHY erratum A008997"
396 config SYS_FSL_ERRATUM_A009007
399 Workaround for USB PHY erratum A009007
401 config SYS_FSL_ERRATUM_A009008
402 bool "Workaround for USB PHY erratum A009008"
404 config SYS_FSL_ERRATUM_A009798
405 bool "Workaround for USB PHY erratum A009798"
407 config SYS_FSL_ERRATUM_A050204
408 bool "Workaround for USB PHY erratum A050204"
410 USB3.0 Receiver needs to enable fixed equalization
411 for each of PHY instances in an SOC. This is similar
412 to erratum A-009007, but this one is for LX2160A and LX2162A,
413 and the register value is different.
415 config SYS_FSL_ERRATUM_A010315
416 bool "Workaround for PCIe erratum A010315"
418 config SYS_FSL_ERRATUM_A010539
419 bool "Workaround for PIN MUX erratum A010539"
422 int "Maximum number of CPUs permitted for Layerscape"
423 default 2 if ARCH_LS1028A
424 default 4 if ARCH_LS1043A
425 default 4 if ARCH_LS1046A
426 default 16 if ARCH_LS2080A
427 default 8 if ARCH_LS1088A
428 default 16 if ARCH_LX2160A
429 default 16 if ARCH_LX2162A
432 Set this number to the maximum number of possible CPUs in the SoC.
433 SoCs may have multiple clusters with each cluster may have multiple
434 ports. If some ports are reserved but higher ports are used for
435 cores, count the reserved ports. This will allocate enough memory
436 in spin table to properly handle all cores.
439 bool "Fan controller"
441 Enable the EMC2305 fan controller for configuration of fan
447 Enable Freescale Secure Boot feature
450 bool "Init the QSPI AHB bus"
452 The default setting for QSPI AHB bus just support 3bytes addressing.
453 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
454 bus for those flashes to support the full QSPI flash size.
456 config FSPI_AHB_EN_4BYTE
457 bool "Enable 4-byte Fast Read command for AHB mode"
459 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
460 But some FlexSPI flash sizes are up to 64MBytes.
461 This flag enables fast read command for AHB mode and modifies required
462 LUT to support full FlexSPI flash.
464 config SYS_CCI400_OFFSET
465 hex "Offset for CCI400 base"
466 depends on SYS_FSL_HAS_CCI400
467 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
468 default 0x180000 if FSL_LSCH2
470 Offset for CCI400 base
471 CCI400 base addr = CCSRBAR + CCI400_OFFSET
473 config SYS_FSL_IFC_BANK_COUNT
474 int "Maximum banks of Integrated flash controller"
475 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
476 default 4 if ARCH_LS1043A
477 default 4 if ARCH_LS1046A
478 default 8 if ARCH_LS2080A || ARCH_LS1088A
480 config SYS_FSL_HAS_CCI400
483 config SYS_FSL_HAS_CCN504
486 config SYS_FSL_HAS_CCN508
489 config SYS_FSL_HAS_DP_DDR
492 config SYS_FSL_SRDS_1
495 config SYS_FSL_SRDS_2
498 config SYS_NXP_SRDS_3
501 config SYS_HAS_SERDES
513 config FSL_TZPC_BP147
517 menu "Layerscape clock tree configuration"
518 depends on FSL_LSCH2 || FSL_LSCH3
521 bool "Enable clock tree initialization"
524 config CLUSTER_CLK_FREQ
525 int "Reference clock of core cluster"
526 depends on ARCH_LS1012A
529 This number is the reference clock frequency of core PLL.
530 For most platforms, the core PLL and Platform PLL have the same
531 reference clock, but for some platforms, LS1012A for instance,
532 they are provided sepatately.
534 config SYS_FSL_PCLK_DIV
535 int "Platform clock divider"
536 default 1 if ARCH_LS1028A
537 default 1 if ARCH_LS1043A
538 default 1 if ARCH_LS1046A
539 default 1 if ARCH_LS1088A
542 This is the divider that is used to derive Platform clock from
543 Platform PLL, in another word:
544 Platform_clk = Platform_PLL_freq / this_divider
546 config SYS_FSL_DSPI_CLK_DIV
547 int "DSPI clock divider"
548 default 1 if ARCH_LS1043A
551 This is the divider that is used to derive DSPI clock from Platform
552 clock, in another word DSPI_clk = Platform_clk / this_divider.
554 config SYS_FSL_DUART_CLK_DIV
555 int "DUART clock divider"
556 default 1 if ARCH_LS1043A
557 default 4 if ARCH_LX2160A
558 default 4 if ARCH_LX2162A
561 This is the divider that is used to derive DUART clock from Platform
562 clock, in another word DUART_clk = Platform_clk / this_divider.
564 config SYS_FSL_I2C_CLK_DIV
565 int "I2C clock divider"
566 default 1 if ARCH_LS1043A
567 default 4 if ARCH_LS1012A
568 default 4 if ARCH_LS1028A
569 default 8 if ARCH_LX2160A
570 default 8 if ARCH_LX2162A
571 default 8 if ARCH_LS1088A
574 This is the divider that is used to derive I2C clock from Platform
575 clock, in another word I2C_clk = Platform_clk / this_divider.
577 config SYS_FSL_IFC_CLK_DIV
578 int "IFC clock divider"
579 default 1 if ARCH_LS1043A
580 default 4 if ARCH_LS1012A
581 default 4 if ARCH_LS1028A
582 default 8 if ARCH_LX2160A
583 default 8 if ARCH_LX2162A
584 default 8 if ARCH_LS1088A
587 This is the divider that is used to derive IFC clock from Platform
588 clock, in another word IFC_clk = Platform_clk / this_divider.
590 config SYS_FSL_LPUART_CLK_DIV
591 int "LPUART clock divider"
592 default 1 if ARCH_LS1043A
595 This is the divider that is used to derive LPUART clock from Platform
596 clock, in another word LPUART_clk = Platform_clk / this_divider.
598 config SYS_FSL_SDHC_CLK_DIV
599 int "SDHC clock divider"
600 default 1 if ARCH_LS1043A
601 default 1 if ARCH_LS1012A
604 This is the divider that is used to derive SDHC clock from Platform
605 clock, in another word SDHC_clk = Platform_clk / this_divider.
607 config SYS_FSL_QMAN_CLK_DIV
608 int "QMAN clock divider"
609 default 1 if ARCH_LS1043A
612 This is the divider that is used to derive QMAN clock from Platform
613 clock, in another word QMAN_clk = Platform_clk / this_divider.
619 Reserve memory from the top, tracked by gd->arch.resv_ram. This
620 reserved RAM can be used by special driver that resides in memory
621 after U-Boot exits. It's up to implementation to allocate and allow
622 access to this reserved memory. For example, the reserved RAM can
623 be at the high end of physical memory. The reserve RAM may be
624 excluded from memory bank(s) passed to OS, or marked as reserved.
629 Ethernet controller 1, this is connected to
630 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
631 Provides DPAA2 capabilities
636 Ethernet controller 2, this is connected to
637 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
638 Provides DPAA2 capabilities
640 config SYS_FSL_ERRATUM_A008336
643 config SYS_FSL_ERRATUM_A008514
646 config SYS_FSL_ERRATUM_A008585
649 config SYS_FSL_ERRATUM_A008850
652 config SYS_FSL_ERRATUM_A009203
655 config SYS_FSL_ERRATUM_A009635
658 config SYS_FSL_ERRATUM_A009660
661 config SYS_FSL_ERRATUM_A050382
664 config SYS_FSL_HAS_RGMII
666 depends on SYS_FSL_EC1 || SYS_FSL_EC2
669 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
671 config HAS_FSL_XHCI_USB
674 For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
675 pins, select it when the pins are assigned to USB.
677 config SYS_FSL_BOOTROM_BASE
682 config SYS_FSL_BOOTROM_SIZE