4 select ARM_ERRATA_855873 if !TFABOOT
8 select SKIP_LOWLEVEL_INIT
13 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
14 select SYS_FSL_ERRATUM_A009798
15 select SYS_FSL_ERRATUM_A008997
16 select SYS_FSL_ERRATUM_A009007
17 select SYS_FSL_ERRATUM_A009008
18 select ARCH_EARLY_INIT_R
19 select BOARD_EARLY_INIT_F
21 select SYS_I2C_MXC_I2C1 if !DM_I2C
22 select SYS_I2C_MXC_I2C2 if !DM_I2C
27 select ARMV8_SET_SMPEN
32 select SYS_FSL_HAS_CCI400
37 select SYS_FSL_DDR_VER_50
38 select SYS_FSL_HAS_DDR3
39 select SYS_FSL_HAS_DDR4
40 select SYS_FSL_HAS_SEC
41 select SYS_FSL_SEC_COMPAT_5
45 select ARCH_EARLY_INIT_R
46 select BOARD_EARLY_INIT_F
48 select SYS_FSL_ERRATUM_A008997
49 select SYS_FSL_ERRATUM_A009007
50 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
51 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
52 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
53 select SYS_FSL_ERRATUM_A050382
54 select SYS_FSL_ERRATUM_A011334
55 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
56 select RESV_RAM if GIC_V3_ITS
61 select ARMV8_SET_SMPEN
62 select ARM_ERRATA_855873 if !TFABOOT
63 select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
67 select HAS_FSL_XHCI_USB if USB_HOST
68 select SKIP_LOWLEVEL_INIT
73 select SYS_FSL_DDR_VER_50
74 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
75 select SYS_FSL_ERRATUM_A008997
76 select SYS_FSL_ERRATUM_A009007
77 select SYS_FSL_ERRATUM_A009008
78 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
79 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
80 select SYS_FSL_ERRATUM_A009798
81 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
82 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
83 select SYS_FSL_ERRATUM_A010539
84 select SYS_FSL_HAS_DDR3
85 select SYS_FSL_HAS_DDR4
86 select ARCH_EARLY_INIT_R
87 select BOARD_EARLY_INIT_F
89 select SYS_I2C_MXC_I2C1 if !DM_I2C
90 select SYS_I2C_MXC_I2C2 if !DM_I2C
91 select SYS_I2C_MXC_I2C3 if !DM_I2C
92 select SYS_I2C_MXC_I2C4 if !DM_I2C
98 select ARMV8_SET_SMPEN
99 select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
100 select FSL_LAYERSCAPE
103 select HAS_FSL_XHCI_USB if USB_HOST
104 select SKIP_LOWLEVEL_INIT
105 select SYS_FSL_SRDS_1
106 select SYS_HAS_SERDES
108 select SYS_FSL_DDR_BE
109 select SYS_FSL_DDR_VER_50
110 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
111 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
112 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
113 select SYS_FSL_ERRATUM_A008997
114 select SYS_FSL_ERRATUM_A009007
115 select SYS_FSL_ERRATUM_A009008
116 select SYS_FSL_ERRATUM_A009798
117 select SYS_FSL_ERRATUM_A009801
118 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
119 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
120 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
121 select SYS_FSL_ERRATUM_A010539
122 select SYS_FSL_HAS_DDR4
123 select SYS_FSL_SRDS_2
124 select ARCH_EARLY_INIT_R
125 select BOARD_EARLY_INIT_F
127 select SYS_I2C_MXC_I2C1 if !DM_I2C
128 select SYS_I2C_MXC_I2C2 if !DM_I2C
129 select SYS_I2C_MXC_I2C3 if !DM_I2C
130 select SYS_I2C_MXC_I2C4 if !DM_I2C
134 imply SPL_SYS_I2C_LEGACY
138 select ARMV8_SET_SMPEN
139 select ARM_ERRATA_855873 if !TFABOOT
141 select FSL_LAYERSCAPE
144 select SKIP_LOWLEVEL_INIT
145 select SYS_FSL_SRDS_1
146 select SYS_HAS_SERDES
148 select SYS_FSL_DDR_LE
149 select SYS_FSL_DDR_VER_50
152 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
153 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
154 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
155 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
156 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
157 select SYS_FSL_ERRATUM_A009007
158 select SYS_FSL_HAS_CCI400
159 select SYS_FSL_HAS_DDR4
160 select SYS_FSL_HAS_RGMII
161 select SYS_FSL_HAS_SEC
162 select SYS_FSL_SEC_COMPAT_5
163 select SYS_FSL_SEC_LE
164 select SYS_FSL_SRDS_1
165 select SYS_FSL_SRDS_2
168 select FSL_TZPC_BP147
169 select ARCH_EARLY_INIT_R
170 select BOARD_EARLY_INIT_F
172 select SYS_I2C_MXC_I2C1 if !TFABOOT
173 select SYS_I2C_MXC_I2C2 if !TFABOOT
174 select SYS_I2C_MXC_I2C3 if !TFABOOT
175 select SYS_I2C_MXC_I2C4 if !TFABOOT
176 select RESV_RAM if GIC_V3_ITS
179 imply SPL_SYS_I2C_LEGACY
184 select ARMV8_SET_SMPEN
185 select ARM_ERRATA_826974
186 select ARM_ERRATA_828024
187 select ARM_ERRATA_829520
188 select ARM_ERRATA_833471
190 select FSL_LAYERSCAPE
193 select SKIP_LOWLEVEL_INIT
194 select SYS_FSL_SRDS_1
195 select SYS_HAS_SERDES
197 select SYS_FSL_DDR_LE
198 select SYS_FSL_DDR_VER_50
199 select SYS_FSL_HAS_CCN504
200 select SYS_FSL_HAS_DP_DDR
201 select SYS_FSL_HAS_SEC
202 select SYS_FSL_HAS_DDR4
203 select SYS_FSL_SEC_COMPAT_5
204 select SYS_FSL_SEC_LE
205 select SYS_FSL_SRDS_2
209 select FSL_TZPC_BP147
210 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
211 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
212 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
213 select SYS_FSL_ERRATUM_A008585
214 select SYS_FSL_ERRATUM_A008997
215 select SYS_FSL_ERRATUM_A009007
216 select SYS_FSL_ERRATUM_A009008
217 select SYS_FSL_ERRATUM_A009635
218 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
219 select SYS_FSL_ERRATUM_A009798
220 select SYS_FSL_ERRATUM_A009801
221 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
222 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
223 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
224 select SYS_FSL_ERRATUM_A009203
225 select ARCH_EARLY_INIT_R
226 select BOARD_EARLY_INIT_F
228 select SYS_I2C_MXC_I2C1 if !TFABOOT
229 select SYS_I2C_MXC_I2C2 if !TFABOOT
230 select SYS_I2C_MXC_I2C3 if !TFABOOT
231 select SYS_I2C_MXC_I2C4 if !TFABOOT
232 select RESV_RAM if GIC_V3_ITS
233 imply DISTRO_DEFAULTS
236 imply SPL_SYS_I2C_LEGACY
240 select ARMV8_SET_SMPEN
242 select FSL_DDR_INTERACTIVE
243 select FSL_LAYERSCAPE
245 select FSL_TZPC_BP147
248 select SYS_HAS_SERDES
249 select SYS_FSL_SRDS_1
250 select SYS_FSL_SRDS_2
252 select SYS_FSL_DDR_LE
253 select SYS_FSL_DDR_VER_50
256 select SYS_FSL_ERRATUM_A050204
257 select SYS_FSL_ERRATUM_A011334
258 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
259 select SYS_FSL_HAS_RGMII
260 select SYS_FSL_HAS_SEC
261 select SYS_FSL_HAS_CCN508
262 select SYS_FSL_HAS_DDR4
263 select SYS_FSL_SEC_COMPAT_5
264 select SYS_FSL_SEC_LE
265 select SYS_PCI_64BIT if PCI
266 select ARCH_EARLY_INIT_R
267 select BOARD_EARLY_INIT_F
269 select RESV_RAM if GIC_V3_ITS
270 imply DISTRO_DEFAULTS
274 imply SPL_SYS_I2C_LEGACY
278 select ARMV8_SET_SMPEN
280 select FSL_DDR_INTERACTIVE
281 select FSL_LAYERSCAPE
283 select FSL_TZPC_BP147
285 select HAS_FSL_XHCI_USB if USB_HOST
287 select SYS_HAS_SERDES
288 select SYS_FSL_SRDS_1
289 select SYS_FSL_SRDS_2
290 select SYS_NXP_SRDS_3
292 select SYS_FSL_DDR_LE
293 select SYS_FSL_DDR_VER_50
296 select SYS_FSL_ERRATUM_A050204
297 select SYS_FSL_ERRATUM_A011334
298 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
299 select SYS_FSL_HAS_RGMII
300 select SYS_FSL_HAS_SEC
301 select SYS_FSL_HAS_CCN508
302 select SYS_FSL_HAS_DDR4
303 select SYS_FSL_SEC_COMPAT_5
304 select SYS_FSL_SEC_LE
305 select SYS_PCI_64BIT if PCI
306 select ARCH_EARLY_INIT_R
307 select BOARD_EARLY_INIT_F
309 select RESV_RAM if GIC_V3_ITS
310 imply DISTRO_DEFAULTS
315 imply SPL_SYS_I2C_LEGACY
319 select SKIP_LOWLEVEL_INIT
320 select SYS_FSL_HAS_CCI400
321 select SYS_FSL_HAS_SEC
322 select SYS_FSL_SEC_COMPAT_5
323 select SYS_FSL_SEC_BE
326 select ARCH_MISC_INIT
332 menu "Layerscape architecture"
333 depends on FSL_LSCH2 || FSL_LSCH3
335 config FSL_LAYERSCAPE
338 config HAS_FEATURE_GIC64K_ALIGN
340 default y if ARCH_LS1043A
342 config HAS_FEATURE_ENHANCED_MSI
344 default y if ARCH_LS1043A
346 menu "Layerscape PPA"
348 bool "FSL Layerscape PPA firmware support"
349 depends on !ARMV8_PSCI
350 select ARMV8_SEC_FIRMWARE_SUPPORT
351 select SEC_FIRMWARE_ARMV8_PSCI
352 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
354 The FSL Primary Protected Application (PPA) is a software component
355 which is loaded during boot stage, and then remains resident in RAM
356 and runs in the TrustZone after boot.
359 config SPL_FSL_LS_PPA
360 bool "FSL Layerscape PPA firmware support for SPL build"
361 depends on !ARMV8_PSCI
362 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
363 select SEC_FIRMWARE_ARMV8_PSCI
364 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
366 The FSL Primary Protected Application (PPA) is a software component
367 which is loaded during boot stage, and then remains resident in RAM
368 and runs in the TrustZone after boot. This is to load PPA during SPL
369 stage instead of the RAM version of U-Boot. Once PPA is initialized,
370 the rest of U-Boot (including RAM version) runs at EL2.
372 prompt "FSL Layerscape PPA firmware loading-media select"
373 depends on FSL_LS_PPA
374 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
375 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
376 default SYS_LS_PPA_FW_IN_XIP
378 config SYS_LS_PPA_FW_IN_XIP
381 Say Y here if the PPA firmware locate at XIP flash, such
382 as NOR or QSPI flash.
384 config SYS_LS_PPA_FW_IN_MMC
385 bool "eMMC or SD Card"
387 Say Y here if the PPA firmware locate at eMMC/SD card.
389 config SYS_LS_PPA_FW_IN_NAND
392 Say Y here if the PPA firmware locate at NAND flash.
396 config LS_PPA_ESBC_HDR_SIZE
397 hex "Length of PPA ESBC header"
398 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
401 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
402 NAND to memory to validate PPA image.
406 config SYS_FSL_ERRATUM_A008997
407 bool "Workaround for USB PHY erratum A008997"
409 config SYS_FSL_ERRATUM_A009007
412 Workaround for USB PHY erratum A009007
414 config SYS_FSL_ERRATUM_A009008
415 bool "Workaround for USB PHY erratum A009008"
417 config SYS_FSL_ERRATUM_A009798
418 bool "Workaround for USB PHY erratum A009798"
420 config SYS_FSL_ERRATUM_A050204
421 bool "Workaround for USB PHY erratum A050204"
423 USB3.0 Receiver needs to enable fixed equalization
424 for each of PHY instances in an SOC. This is similar
425 to erratum A-009007, but this one is for LX2160A and LX2162A,
426 and the register value is different.
428 config SYS_FSL_ERRATUM_A010315
429 bool "Workaround for PCIe erratum A010315"
431 config SYS_FSL_ERRATUM_A010539
432 bool "Workaround for PIN MUX erratum A010539"
435 int "Maximum number of CPUs permitted for Layerscape"
436 default 2 if ARCH_LS1028A
437 default 4 if ARCH_LS1043A
438 default 4 if ARCH_LS1046A
439 default 16 if ARCH_LS2080A
440 default 8 if ARCH_LS1088A
441 default 16 if ARCH_LX2160A
442 default 16 if ARCH_LX2162A
445 Set this number to the maximum number of possible CPUs in the SoC.
446 SoCs may have multiple clusters with each cluster may have multiple
447 ports. If some ports are reserved but higher ports are used for
448 cores, count the reserved ports. This will allocate enough memory
449 in spin table to properly handle all cores.
452 bool "Fan controller"
454 Enable the EMC2305 fan controller for configuration of fan
460 Enable Freescale Secure Boot feature
463 bool "Init the QSPI AHB bus"
465 The default setting for QSPI AHB bus just support 3bytes addressing.
466 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
467 bus for those flashes to support the full QSPI flash size.
469 config FSPI_AHB_EN_4BYTE
470 bool "Enable 4-byte Fast Read command for AHB mode"
472 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
473 But some FlexSPI flash sizes are up to 64MBytes.
474 This flag enables fast read command for AHB mode and modifies required
475 LUT to support full FlexSPI flash.
477 config SYS_CCI400_OFFSET
478 hex "Offset for CCI400 base"
479 depends on SYS_FSL_HAS_CCI400
480 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
481 default 0x180000 if FSL_LSCH2
483 Offset for CCI400 base
484 CCI400 base addr = CCSRBAR + CCI400_OFFSET
486 config SYS_FSL_IFC_BANK_COUNT
487 int "Maximum banks of Integrated flash controller"
488 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
489 default 4 if ARCH_LS1043A
490 default 4 if ARCH_LS1046A
491 default 8 if ARCH_LS2080A || ARCH_LS1088A
493 config SYS_FSL_HAS_CCI400
496 config SYS_FSL_HAS_CCN504
499 config SYS_FSL_HAS_CCN508
502 config SYS_FSL_HAS_DP_DDR
505 config SYS_FSL_SRDS_1
508 config SYS_FSL_SRDS_2
511 config SYS_NXP_SRDS_3
514 config SYS_HAS_SERDES
526 config FSL_TZPC_BP147
530 menu "Layerscape clock tree configuration"
531 depends on FSL_LSCH2 || FSL_LSCH3
534 bool "Enable clock tree initialization"
537 config CLUSTER_CLK_FREQ
538 int "Reference clock of core cluster"
539 depends on ARCH_LS1012A
542 This number is the reference clock frequency of core PLL.
543 For most platforms, the core PLL and Platform PLL have the same
544 reference clock, but for some platforms, LS1012A for instance,
545 they are provided sepatately.
547 config SYS_FSL_PCLK_DIV
548 int "Platform clock divider"
549 default 1 if ARCH_LS1028A
550 default 1 if ARCH_LS1043A
551 default 1 if ARCH_LS1046A
552 default 1 if ARCH_LS1088A
555 This is the divider that is used to derive Platform clock from
556 Platform PLL, in another word:
557 Platform_clk = Platform_PLL_freq / this_divider
559 config SYS_FSL_DSPI_CLK_DIV
560 int "DSPI clock divider"
561 default 1 if ARCH_LS1043A
564 This is the divider that is used to derive DSPI clock from Platform
565 clock, in another word DSPI_clk = Platform_clk / this_divider.
567 config SYS_FSL_DUART_CLK_DIV
568 int "DUART clock divider"
569 default 1 if ARCH_LS1043A
570 default 4 if ARCH_LX2160A
571 default 4 if ARCH_LX2162A
574 This is the divider that is used to derive DUART clock from Platform
575 clock, in another word DUART_clk = Platform_clk / this_divider.
577 config SYS_FSL_I2C_CLK_DIV
578 int "I2C clock divider"
579 default 1 if ARCH_LS1043A
580 default 4 if ARCH_LS1012A
581 default 4 if ARCH_LS1028A
582 default 8 if ARCH_LX2160A
583 default 8 if ARCH_LX2162A
584 default 8 if ARCH_LS1088A
587 This is the divider that is used to derive I2C clock from Platform
588 clock, in another word I2C_clk = Platform_clk / this_divider.
590 config SYS_FSL_IFC_CLK_DIV
591 int "IFC clock divider"
592 default 1 if ARCH_LS1043A
593 default 4 if ARCH_LS1012A
594 default 4 if ARCH_LS1028A
595 default 8 if ARCH_LX2160A
596 default 8 if ARCH_LX2162A
597 default 8 if ARCH_LS1088A
600 This is the divider that is used to derive IFC clock from Platform
601 clock, in another word IFC_clk = Platform_clk / this_divider.
603 config SYS_FSL_LPUART_CLK_DIV
604 int "LPUART clock divider"
605 default 1 if ARCH_LS1043A
608 This is the divider that is used to derive LPUART clock from Platform
609 clock, in another word LPUART_clk = Platform_clk / this_divider.
611 config SYS_FSL_SDHC_CLK_DIV
612 int "SDHC clock divider"
613 default 1 if ARCH_LS1043A
614 default 1 if ARCH_LS1012A
617 This is the divider that is used to derive SDHC clock from Platform
618 clock, in another word SDHC_clk = Platform_clk / this_divider.
620 config SYS_FSL_QMAN_CLK_DIV
621 int "QMAN clock divider"
622 default 1 if ARCH_LS1043A
625 This is the divider that is used to derive QMAN clock from Platform
626 clock, in another word QMAN_clk = Platform_clk / this_divider.
632 Reserve memory from the top, tracked by gd->arch.resv_ram. This
633 reserved RAM can be used by special driver that resides in memory
634 after U-Boot exits. It's up to implementation to allocate and allow
635 access to this reserved memory. For example, the reserved RAM can
636 be at the high end of physical memory. The reserve RAM may be
637 excluded from memory bank(s) passed to OS, or marked as reserved.
642 Ethernet controller 1, this is connected to
643 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
644 Provides DPAA2 capabilities
649 Ethernet controller 2, this is connected to
650 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
651 Provides DPAA2 capabilities
653 config SYS_FSL_ERRATUM_A008336
656 config SYS_FSL_ERRATUM_A008514
659 config SYS_FSL_ERRATUM_A008585
662 config SYS_FSL_ERRATUM_A008850
665 config SYS_FSL_ERRATUM_A009203
668 config SYS_FSL_ERRATUM_A009635
671 config SYS_FSL_ERRATUM_A009660
674 config SYS_FSL_ERRATUM_A050382
677 config SYS_FSL_HAS_RGMII
679 depends on SYS_FSL_EC1 || SYS_FSL_EC2
682 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
684 config HAS_FSL_XHCI_USB
687 For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
688 pins, select it when the pins are assigned to USB.
690 config SYS_FSL_BOOTROM_BASE
695 config SYS_FSL_BOOTROM_SIZE