3 * David Feng <fenghua@phytium.com.cn>
6 * Alexander Graf <agraf@suse.de>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/system.h>
13 #include <asm/armv8/mmu.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #ifndef CONFIG_SYS_DCACHE_OFF
20 * With 4k page granule, a virtual address is split into 4 lookup parts
21 * spanning 9 bits each:
23 * _______________________________________________
25 * | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off |
26 * |_______|_______|_______|_______|_______|_______|
27 * 63-48 47-39 38-30 29-21 20-12 11-00
31 * Lv0: FF8000000000 --
38 u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
45 /* Find the largest address we need to support */
46 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
47 max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size);
49 /* Calculate the maximum physical (and thus virtual) address */
50 if (max_addr > (1ULL << 44)) {
53 } else if (max_addr > (1ULL << 42)) {
56 } else if (max_addr > (1ULL << 40)) {
59 } else if (max_addr > (1ULL << 36)) {
62 } else if (max_addr > (1ULL << 32)) {
71 tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
73 tcr = TCR_EL2_RSVD | (ips << 16);
75 tcr = TCR_EL3_RSVD | (ips << 16);
78 /* PTWs cacheable, inner/outer WBWA and inner shareable */
79 tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
80 tcr |= TCR_T0SZ(va_bits);
90 #define MAX_PTE_ENTRIES 512
92 static int pte_type(u64 *pte)
94 return *pte & PTE_TYPE_MASK;
97 /* Returns the LSB number for a PTE on level <level> */
98 static int level2shift(int level)
100 /* Page is 12 bits wide, every level translates 9 bits */
101 return (12 + 9 * (3 - level));
104 static u64 *find_pte(u64 addr, int level)
112 debug("addr=%llx level=%d\n", addr, level);
114 get_tcr(0, NULL, &va_bits);
118 if (level < start_level)
121 /* Walk through all page table levels to find our PTE */
122 pte = (u64*)gd->arch.tlb_addr;
123 for (i = start_level; i < 4; i++) {
124 idx = (addr >> level2shift(i)) & 0x1FF;
126 debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
131 /* PTE is no table (either invalid or block), can't traverse */
132 if (pte_type(pte) != PTE_TYPE_TABLE)
134 /* Off to the next level */
135 pte = (u64*)(*pte & 0x0000fffffffff000ULL);
138 /* Should never reach here */
142 /* Returns and creates a new full table (512 entries) */
143 static u64 *create_table(void)
145 u64 *new_table = (u64*)gd->arch.tlb_fillptr;
146 u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
148 /* Allocate MAX_PTE_ENTRIES pte entries */
149 gd->arch.tlb_fillptr += pt_len;
151 if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
152 panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
153 "Please increase the size in get_page_table_size()",
154 gd->arch.tlb_fillptr - gd->arch.tlb_addr,
157 /* Mark all entries as invalid */
158 memset(new_table, 0, pt_len);
163 static void set_pte_table(u64 *pte, u64 *table)
165 /* Point *pte to the new table */
166 debug("Setting %p to addr=%p\n", pte, table);
167 *pte = PTE_TYPE_TABLE | (ulong)table;
170 /* Splits a block PTE into table with subpages spanning the old block */
171 static void split_block(u64 *pte, int level)
176 /* level describes the parent level, we need the child ones */
177 int levelshift = level2shift(level + 1);
179 if (pte_type(pte) != PTE_TYPE_BLOCK)
180 panic("PTE %p (%llx) is not a block. Some driver code wants to "
181 "modify dcache settings for an range not covered in "
182 "mem_map.", pte, old_pte);
184 new_table = create_table();
185 debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
187 for (i = 0; i < MAX_PTE_ENTRIES; i++) {
188 new_table[i] = old_pte | (i << levelshift);
190 /* Level 3 block PTEs have the table type */
191 if ((level + 1) == 3)
192 new_table[i] |= PTE_TYPE_TABLE;
194 debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
197 /* Set the new table into effect */
198 set_pte_table(pte, new_table);
201 /* Add one mm_region map entry to the page tables */
202 static void add_map(struct mm_region *map)
205 u64 virt = map->virt;
206 u64 phys = map->phys;
207 u64 size = map->size;
208 u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
214 pte = find_pte(virt, 0);
215 if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
216 debug("Creating table for virt 0x%llx\n", virt);
217 new_table = create_table();
218 set_pte_table(pte, new_table);
221 for (level = 1; level < 4; level++) {
222 pte = find_pte(virt, level);
224 panic("pte not found\n");
226 blocksize = 1ULL << level2shift(level);
227 debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
228 virt, size, blocksize);
229 if (size >= blocksize && !(virt & (blocksize - 1))) {
230 /* Page fits, create block PTE */
231 debug("Setting PTE %p to block virt=%llx\n",
238 } else if (pte_type(pte) == PTE_TYPE_FAULT) {
239 /* Page doesn't fit, create subpages */
240 debug("Creating subtable for virt 0x%llx blksize=%llx\n",
242 new_table = create_table();
243 set_pte_table(pte, new_table);
244 } else if (pte_type(pte) == PTE_TYPE_BLOCK) {
245 debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
247 split_block(pte, level);
260 * This is a recursively called function to count the number of
261 * page tables we need to cover a particular PTE range. If you
262 * call this with level = -1 you basically get the full 48 bit
265 static int count_required_pts(u64 addr, int level, u64 maxaddr)
267 int levelshift = level2shift(level);
268 u64 levelsize = 1ULL << levelshift;
269 u64 levelmask = levelsize - 1;
270 u64 levelend = addr + levelsize;
273 enum pte_type pte_type = PTE_INVAL;
275 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
276 struct mm_region *map = &mem_map[i];
277 u64 start = map->virt;
278 u64 end = start + map->size;
280 /* Check if the PTE would overlap with the map */
281 if (max(addr, start) <= min(levelend, end)) {
282 start = max(addr, start);
283 end = min(levelend, end);
285 /* We need a sub-pt for this level */
286 if ((start & levelmask) || (end & levelmask)) {
287 pte_type = PTE_LEVEL;
291 /* Lv0 can not do block PTEs, so do levels here too */
293 pte_type = PTE_LEVEL;
297 /* PTE is active, but fits into a block */
298 pte_type = PTE_BLOCK;
303 * Block PTEs at this level are already covered by the parent page
304 * table, so we only need to count sub page tables.
306 if (pte_type == PTE_LEVEL) {
307 int sublevel = level + 1;
308 u64 sublevelsize = 1ULL << level2shift(sublevel);
310 /* Account for the new sub page table ... */
313 /* ... and for all child page tables that one might have */
314 for (i = 0; i < MAX_PTE_ENTRIES; i++) {
315 r += count_required_pts(addr, sublevel, maxaddr);
316 addr += sublevelsize;
318 if (addr >= maxaddr) {
320 * We reached the end of address space, no need
321 * to look any further.
331 /* Returns the estimated required size of all page tables */
332 __weak u64 get_page_table_size(void)
334 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
339 get_tcr(0, NULL, &va_bits);
343 /* Account for all page tables we would need to cover our memory map */
344 size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
347 * We need to duplicate our page table once to have an emergency pt to
348 * resort to when splitting page tables later on
353 * We may need to split page tables later on if dcache settings change,
354 * so reserve up to 4 (random pick) page tables for that.
361 void setup_pgtables(void)
365 if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
366 panic("Page table pointer not setup.");
369 * Allocate the first level we're on with invalidate entries.
370 * If the starting level is 0 (va_bits >= 39), then this is our
371 * Lv0 page table, otherwise it's the entry Lv1 page table.
375 /* Now add all MMU table entries one after another to the table */
376 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
377 add_map(&mem_map[i]);
380 static void setup_all_pgtables(void)
382 u64 tlb_addr = gd->arch.tlb_addr;
384 /* Reset the fill ptr */
385 gd->arch.tlb_fillptr = tlb_addr;
387 /* Create normal system page tables */
390 /* Create emergency page tables */
391 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
393 gd->arch.tlb_emerg = gd->arch.tlb_addr;
394 gd->arch.tlb_addr = tlb_addr;
397 /* to activate the MMU we need to set up virtual memory */
398 __weak void mmu_setup(void)
402 /* Set up page tables only once */
403 if (!gd->arch.tlb_fillptr)
404 setup_all_pgtables();
407 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
411 set_sctlr(get_sctlr() | CR_M);
415 * Performs a invalidation of the entire data cache at all levels
417 void invalidate_dcache_all(void)
419 __asm_invalidate_dcache_all();
423 * Performs a clean & invalidation of the entire data cache at all levels.
424 * This function needs to be inline to avoid using stack.
425 * __asm_flush_l3_cache return status of timeout
427 inline void flush_dcache_all(void)
431 __asm_flush_dcache_all();
432 ret = __asm_flush_l3_cache();
434 debug("flushing dcache returns 0x%x\n", ret);
436 debug("flushing dcache successfully.\n");
440 * Invalidates range in all levels of D-cache/unified cache
442 void invalidate_dcache_range(unsigned long start, unsigned long stop)
444 __asm_flush_dcache_range(start, stop);
448 * Flush range(clean & invalidate) from all levels of D-cache/unified cache
450 void flush_dcache_range(unsigned long start, unsigned long stop)
452 __asm_flush_dcache_range(start, stop);
455 void dcache_enable(void)
457 /* The data cache is not active unless the mmu is enabled */
458 if (!(get_sctlr() & CR_M)) {
459 invalidate_dcache_all();
460 __asm_invalidate_tlb_all();
464 set_sctlr(get_sctlr() | CR_C);
467 void dcache_disable(void)
473 /* if cache isn't enabled no need to disable */
477 set_sctlr(sctlr & ~(CR_C|CR_M));
480 __asm_invalidate_tlb_all();
483 int dcache_status(void)
485 return (get_sctlr() & CR_C) != 0;
488 u64 *__weak arch_get_page_table(void) {
489 puts("No page table offset defined\n");
494 static bool is_aligned(u64 addr, u64 size, u64 align)
496 return !(addr & (align - 1)) && !(size & (align - 1));
499 static u64 set_one_region(u64 start, u64 size, u64 attrs, int level)
501 int levelshift = level2shift(level);
502 u64 levelsize = 1ULL << levelshift;
503 u64 *pte = find_pte(start, level);
505 /* Can we can just modify the current level block PTE? */
506 if (is_aligned(start, size, levelsize)) {
507 *pte &= ~PMD_ATTRINDX_MASK;
509 debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
514 /* Unaligned or doesn't fit, maybe split block into table */
515 debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
517 /* Maybe we need to split the block into a table */
518 if (pte_type(pte) == PTE_TYPE_BLOCK)
519 split_block(pte, level);
521 /* And then double-check it became a table or already is one */
522 if (pte_type(pte) != PTE_TYPE_TABLE)
523 panic("PTE %p (%llx) for addr=%llx should be a table",
526 /* Roll on to the next page table level */
530 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
531 enum dcache_option option)
533 u64 attrs = PMD_ATTRINDX(option);
534 u64 real_start = start;
535 u64 real_size = size;
537 debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
539 if (!gd->arch.tlb_emerg)
540 panic("Emergency page table not setup.");
543 * We can not modify page tables that we're currently running on,
544 * so we first need to switch to the "emergency" page tables where
545 * we can safely modify our primary page tables and then switch back
547 __asm_switch_ttbr(gd->arch.tlb_emerg);
550 * Loop through the address range until we find a page granule that fits
551 * our alignment constraints, then set it to the new cache attributes
557 for (level = 1; level < 4; level++) {
558 r = set_one_region(start, size, attrs, level);
560 /* PTE successfully replaced */
569 /* We're done modifying page tables, switch back to our primary ones */
570 __asm_switch_ttbr(gd->arch.tlb_addr);
573 * Make sure there's nothing stale in dcache for a region that might
574 * have caches off now
576 flush_dcache_range(real_start, real_start + real_size);
579 #else /* CONFIG_SYS_DCACHE_OFF */
582 * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
583 * running however really wants to have dcache and the MMU active. Check that
584 * everything is sane and give the developer a hint if it isn't.
586 #ifndef CONFIG_SPL_BUILD
587 #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
590 void invalidate_dcache_all(void)
594 void flush_dcache_all(void)
598 void dcache_enable(void)
602 void dcache_disable(void)
606 int dcache_status(void)
611 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
612 enum dcache_option option)
616 #endif /* CONFIG_SYS_DCACHE_OFF */
618 #ifndef CONFIG_SYS_ICACHE_OFF
620 void icache_enable(void)
622 __asm_invalidate_icache_all();
623 set_sctlr(get_sctlr() | CR_I);
626 void icache_disable(void)
628 set_sctlr(get_sctlr() & ~CR_I);
631 int icache_status(void)
633 return (get_sctlr() & CR_I) != 0;
636 void invalidate_icache_all(void)
638 __asm_invalidate_icache_all();
641 #else /* CONFIG_SYS_ICACHE_OFF */
643 void icache_enable(void)
647 void icache_disable(void)
651 int icache_status(void)
656 void invalidate_icache_all(void)
660 #endif /* CONFIG_SYS_ICACHE_OFF */
663 * Enable dCache & iCache, whether cache is actually enabled
664 * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
666 void __weak enable_caches(void)