1 // SPDX-License-Identifier: GPL-2.0+
4 * David Feng <fenghua@phytium.com.cn>
7 * Alexander Graf <agraf@suse.de>
14 #include <asm/cache.h>
15 #include <asm/system.h>
16 #include <asm/armv8/mmu.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
23 * With 4k page granule, a virtual address is split into 4 lookup parts
24 * spanning 9 bits each:
26 * _______________________________________________
28 * | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off |
29 * |_______|_______|_______|_______|_______|_______|
30 * 63-48 47-39 38-30 29-21 20-12 11-00
34 * Lv0: FF8000000000 --
41 u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
48 /* Find the largest address we need to support */
49 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
50 max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size);
52 /* Calculate the maximum physical (and thus virtual) address */
53 if (max_addr > (1ULL << 44)) {
56 } else if (max_addr > (1ULL << 42)) {
59 } else if (max_addr > (1ULL << 40)) {
62 } else if (max_addr > (1ULL << 36)) {
65 } else if (max_addr > (1ULL << 32)) {
74 tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
76 tcr = TCR_EL2_RSVD | (ips << 16);
78 tcr = TCR_EL3_RSVD | (ips << 16);
81 /* PTWs cacheable, inner/outer WBWA and inner shareable */
82 tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
83 tcr |= TCR_T0SZ(va_bits);
93 #define MAX_PTE_ENTRIES 512
95 static int pte_type(u64 *pte)
97 return *pte & PTE_TYPE_MASK;
100 /* Returns the LSB number for a PTE on level <level> */
101 static int level2shift(int level)
103 /* Page is 12 bits wide, every level translates 9 bits */
104 return (12 + 9 * (3 - level));
107 static u64 *find_pte(u64 addr, int level)
115 debug("addr=%llx level=%d\n", addr, level);
117 get_tcr(0, NULL, &va_bits);
121 if (level < start_level)
124 /* Walk through all page table levels to find our PTE */
125 pte = (u64*)gd->arch.tlb_addr;
126 for (i = start_level; i < 4; i++) {
127 idx = (addr >> level2shift(i)) & 0x1FF;
129 debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
134 /* PTE is no table (either invalid or block), can't traverse */
135 if (pte_type(pte) != PTE_TYPE_TABLE)
137 /* Off to the next level */
138 pte = (u64*)(*pte & 0x0000fffffffff000ULL);
141 /* Should never reach here */
145 /* Returns and creates a new full table (512 entries) */
146 static u64 *create_table(void)
148 u64 *new_table = (u64*)gd->arch.tlb_fillptr;
149 u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
151 /* Allocate MAX_PTE_ENTRIES pte entries */
152 gd->arch.tlb_fillptr += pt_len;
154 if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
155 panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
156 "Please increase the size in get_page_table_size()",
157 gd->arch.tlb_fillptr - gd->arch.tlb_addr,
160 /* Mark all entries as invalid */
161 memset(new_table, 0, pt_len);
166 static void set_pte_table(u64 *pte, u64 *table)
168 /* Point *pte to the new table */
169 debug("Setting %p to addr=%p\n", pte, table);
170 *pte = PTE_TYPE_TABLE | (ulong)table;
173 /* Splits a block PTE into table with subpages spanning the old block */
174 static void split_block(u64 *pte, int level)
179 /* level describes the parent level, we need the child ones */
180 int levelshift = level2shift(level + 1);
182 if (pte_type(pte) != PTE_TYPE_BLOCK)
183 panic("PTE %p (%llx) is not a block. Some driver code wants to "
184 "modify dcache settings for an range not covered in "
185 "mem_map.", pte, old_pte);
187 new_table = create_table();
188 debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
190 for (i = 0; i < MAX_PTE_ENTRIES; i++) {
191 new_table[i] = old_pte | (i << levelshift);
193 /* Level 3 block PTEs have the table type */
194 if ((level + 1) == 3)
195 new_table[i] |= PTE_TYPE_TABLE;
197 debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
200 /* Set the new table into effect */
201 set_pte_table(pte, new_table);
204 /* Add one mm_region map entry to the page tables */
205 static void add_map(struct mm_region *map)
208 u64 virt = map->virt;
209 u64 phys = map->phys;
210 u64 size = map->size;
211 u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
217 pte = find_pte(virt, 0);
218 if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
219 debug("Creating table for virt 0x%llx\n", virt);
220 new_table = create_table();
221 set_pte_table(pte, new_table);
224 for (level = 1; level < 4; level++) {
225 pte = find_pte(virt, level);
227 panic("pte not found\n");
229 blocksize = 1ULL << level2shift(level);
230 debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
231 virt, size, blocksize);
232 if (size >= blocksize && !(virt & (blocksize - 1))) {
233 /* Page fits, create block PTE */
234 debug("Setting PTE %p to block virt=%llx\n",
237 *pte = phys | attrs | PTE_TYPE_PAGE;
244 } else if (pte_type(pte) == PTE_TYPE_FAULT) {
245 /* Page doesn't fit, create subpages */
246 debug("Creating subtable for virt 0x%llx blksize=%llx\n",
248 new_table = create_table();
249 set_pte_table(pte, new_table);
250 } else if (pte_type(pte) == PTE_TYPE_BLOCK) {
251 debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
253 split_block(pte, level);
266 * This is a recursively called function to count the number of
267 * page tables we need to cover a particular PTE range. If you
268 * call this with level = -1 you basically get the full 48 bit
271 static int count_required_pts(u64 addr, int level, u64 maxaddr)
273 int levelshift = level2shift(level);
274 u64 levelsize = 1ULL << levelshift;
275 u64 levelmask = levelsize - 1;
276 u64 levelend = addr + levelsize;
279 enum pte_type pte_type = PTE_INVAL;
281 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
282 struct mm_region *map = &mem_map[i];
283 u64 start = map->virt;
284 u64 end = start + map->size;
286 /* Check if the PTE would overlap with the map */
287 if (max(addr, start) <= min(levelend, end)) {
288 start = max(addr, start);
289 end = min(levelend, end);
291 /* We need a sub-pt for this level */
292 if ((start & levelmask) || (end & levelmask)) {
293 pte_type = PTE_LEVEL;
297 /* Lv0 can not do block PTEs, so do levels here too */
299 pte_type = PTE_LEVEL;
303 /* PTE is active, but fits into a block */
304 pte_type = PTE_BLOCK;
309 * Block PTEs at this level are already covered by the parent page
310 * table, so we only need to count sub page tables.
312 if (pte_type == PTE_LEVEL) {
313 int sublevel = level + 1;
314 u64 sublevelsize = 1ULL << level2shift(sublevel);
316 /* Account for the new sub page table ... */
319 /* ... and for all child page tables that one might have */
320 for (i = 0; i < MAX_PTE_ENTRIES; i++) {
321 r += count_required_pts(addr, sublevel, maxaddr);
322 addr += sublevelsize;
324 if (addr >= maxaddr) {
326 * We reached the end of address space, no need
327 * to look any further.
337 /* Returns the estimated required size of all page tables */
338 __weak u64 get_page_table_size(void)
340 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
345 get_tcr(0, NULL, &va_bits);
349 /* Account for all page tables we would need to cover our memory map */
350 size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
353 * We need to duplicate our page table once to have an emergency pt to
354 * resort to when splitting page tables later on
359 * We may need to split page tables later on if dcache settings change,
360 * so reserve up to 4 (random pick) page tables for that.
367 void setup_pgtables(void)
371 if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
372 panic("Page table pointer not setup.");
375 * Allocate the first level we're on with invalidate entries.
376 * If the starting level is 0 (va_bits >= 39), then this is our
377 * Lv0 page table, otherwise it's the entry Lv1 page table.
381 /* Now add all MMU table entries one after another to the table */
382 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
383 add_map(&mem_map[i]);
386 static void setup_all_pgtables(void)
388 u64 tlb_addr = gd->arch.tlb_addr;
389 u64 tlb_size = gd->arch.tlb_size;
391 /* Reset the fill ptr */
392 gd->arch.tlb_fillptr = tlb_addr;
394 /* Create normal system page tables */
397 /* Create emergency page tables */
398 gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr -
399 (uintptr_t)gd->arch.tlb_addr;
400 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
402 gd->arch.tlb_emerg = gd->arch.tlb_addr;
403 gd->arch.tlb_addr = tlb_addr;
404 gd->arch.tlb_size = tlb_size;
407 /* to activate the MMU we need to set up virtual memory */
408 __weak void mmu_setup(void)
412 /* Set up page tables only once */
413 if (!gd->arch.tlb_fillptr)
414 setup_all_pgtables();
417 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
421 set_sctlr(get_sctlr() | CR_M);
425 * Performs a invalidation of the entire data cache at all levels
427 void invalidate_dcache_all(void)
429 __asm_invalidate_dcache_all();
430 __asm_invalidate_l3_dcache();
434 * Performs a clean & invalidation of the entire data cache at all levels.
435 * This function needs to be inline to avoid using stack.
436 * __asm_flush_l3_dcache return status of timeout
438 inline void flush_dcache_all(void)
442 __asm_flush_dcache_all();
443 ret = __asm_flush_l3_dcache();
445 debug("flushing dcache returns 0x%x\n", ret);
447 debug("flushing dcache successfully.\n");
450 #ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
452 * Invalidates range in all levels of D-cache/unified cache
454 void invalidate_dcache_range(unsigned long start, unsigned long stop)
456 __asm_invalidate_dcache_range(start, stop);
460 * Flush range(clean & invalidate) from all levels of D-cache/unified cache
462 void flush_dcache_range(unsigned long start, unsigned long stop)
464 __asm_flush_dcache_range(start, stop);
467 void invalidate_dcache_range(unsigned long start, unsigned long stop)
471 void flush_dcache_range(unsigned long start, unsigned long stop)
474 #endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
476 void dcache_enable(void)
478 /* The data cache is not active unless the mmu is enabled */
479 if (!(get_sctlr() & CR_M)) {
480 invalidate_dcache_all();
481 __asm_invalidate_tlb_all();
485 set_sctlr(get_sctlr() | CR_C);
488 void dcache_disable(void)
494 /* if cache isn't enabled no need to disable */
498 set_sctlr(sctlr & ~(CR_C|CR_M));
501 __asm_invalidate_tlb_all();
504 int dcache_status(void)
506 return (get_sctlr() & CR_C) != 0;
509 u64 *__weak arch_get_page_table(void) {
510 puts("No page table offset defined\n");
515 static bool is_aligned(u64 addr, u64 size, u64 align)
517 return !(addr & (align - 1)) && !(size & (align - 1));
520 /* Use flag to indicate if attrs has more than d-cache attributes */
521 static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
523 int levelshift = level2shift(level);
524 u64 levelsize = 1ULL << levelshift;
525 u64 *pte = find_pte(start, level);
527 /* Can we can just modify the current level block PTE? */
528 if (is_aligned(start, size, levelsize)) {
530 *pte &= ~PMD_ATTRMASK;
531 *pte |= attrs & PMD_ATTRMASK;
533 *pte &= ~PMD_ATTRINDX_MASK;
534 *pte |= attrs & PMD_ATTRINDX_MASK;
536 debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
541 /* Unaligned or doesn't fit, maybe split block into table */
542 debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
544 /* Maybe we need to split the block into a table */
545 if (pte_type(pte) == PTE_TYPE_BLOCK)
546 split_block(pte, level);
548 /* And then double-check it became a table or already is one */
549 if (pte_type(pte) != PTE_TYPE_TABLE)
550 panic("PTE %p (%llx) for addr=%llx should be a table",
553 /* Roll on to the next page table level */
557 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
558 enum dcache_option option)
560 u64 attrs = PMD_ATTRINDX(option >> 2);
561 u64 real_start = start;
562 u64 real_size = size;
564 debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
566 if (!gd->arch.tlb_emerg)
567 panic("Emergency page table not setup.");
570 * We can not modify page tables that we're currently running on,
571 * so we first need to switch to the "emergency" page tables where
572 * we can safely modify our primary page tables and then switch back
574 __asm_switch_ttbr(gd->arch.tlb_emerg);
577 * Loop through the address range until we find a page granule that fits
578 * our alignment constraints, then set it to the new cache attributes
584 for (level = 1; level < 4; level++) {
585 /* Set d-cache attributes only */
586 r = set_one_region(start, size, attrs, false, level);
588 /* PTE successfully replaced */
597 /* We're done modifying page tables, switch back to our primary ones */
598 __asm_switch_ttbr(gd->arch.tlb_addr);
601 * Make sure there's nothing stale in dcache for a region that might
602 * have caches off now
604 flush_dcache_range(real_start, real_start + real_size);
608 * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
609 * The procecess is break-before-make. The target region will be marked as
610 * invalid during the process of changing.
612 void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
620 * Loop through the address range until we find a page granule that fits
621 * our alignment constraints, then set it to "invalid".
624 for (level = 1; level < 4; level++) {
625 /* Set PTE to fault */
626 r = set_one_region(start, size, PTE_TYPE_FAULT, true,
629 /* PTE successfully invalidated */
637 flush_dcache_range(gd->arch.tlb_addr,
638 gd->arch.tlb_addr + gd->arch.tlb_size);
639 __asm_invalidate_tlb_all();
642 * Loop through the address range until we find a page granule that fits
643 * our alignment constraints, then set it to the new cache attributes
648 for (level = 1; level < 4; level++) {
649 /* Set PTE to new attributes */
650 r = set_one_region(start, size, attrs, true, level);
652 /* PTE successfully updated */
659 flush_dcache_range(gd->arch.tlb_addr,
660 gd->arch.tlb_addr + gd->arch.tlb_size);
661 __asm_invalidate_tlb_all();
664 #else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
667 * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
668 * running however really wants to have dcache and the MMU active. Check that
669 * everything is sane and give the developer a hint if it isn't.
671 #ifndef CONFIG_SPL_BUILD
672 #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
675 void invalidate_dcache_all(void)
679 void flush_dcache_all(void)
683 void dcache_enable(void)
687 void dcache_disable(void)
691 int dcache_status(void)
696 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
697 enum dcache_option option)
701 #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
703 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
705 void icache_enable(void)
707 invalidate_icache_all();
708 set_sctlr(get_sctlr() | CR_I);
711 void icache_disable(void)
713 set_sctlr(get_sctlr() & ~CR_I);
716 int icache_status(void)
718 return (get_sctlr() & CR_I) != 0;
721 void invalidate_icache_all(void)
723 __asm_invalidate_icache_all();
724 __asm_invalidate_l3_icache();
727 #else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
729 void icache_enable(void)
733 void icache_disable(void)
737 int icache_status(void)
742 void invalidate_icache_all(void)
746 #endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
749 * Enable dCache & iCache, whether cache is actually enabled
750 * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
752 void __weak enable_caches(void)