3 config ARMV8_SPL_EXCEPTION_VECTORS
4 bool "Install crash dump exception vectors"
7 The default exception vector table is only used for the crash
8 dump, but still takes quite a lot of space in the image size.
10 Say N here if you are running out of code space in the image
11 and want to save some space at the cost of less debugging info.
13 config ARMV8_MULTIENTRY
14 bool "Enable multiple CPUs to enter into U-Boot"
16 config ARMV8_SET_SMPEN
17 bool "Enable data coherency with other cores in cluster"
19 Say Y here if there is not any trust firmware to set
20 CPUECTLR_EL1.SMPEN bit before U-Boot.
22 For A53, it enables data coherency with other cores in the
23 cluster, and for A57/A72, it enables receiving of instruction
24 cache and TLB maintenance operations.
25 Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
26 for single core systems. Unfortunately write access to this
27 register may be controlled by EL3/EL2 firmware. To be more
28 precise, by default (if there is EL2/EL3 firmware running)
29 this register is RO for NS EL1.
30 This switch can be used to avoid writing to CPUECTLR_EL1,
31 it can be safely enabled when EL2/EL3 initialized SMPEN bit
32 or when CPU implementation doesn't include that register.
34 config ARMV8_SPIN_TABLE
35 bool "Support spin-table enable method"
36 depends on ARMV8_MULTIENTRY && OF_LIBFDT
38 Say Y here to support "spin-table" enable method for booting Linux.
40 To use this feature, you must do:
41 - Specify enable-method = "spin-table" in each CPU node in the
42 Device Tree you are using to boot the kernel
43 - Bring secondary CPUs into U-Boot proper in a board specific
44 manner. This must be done *after* relocation. Otherwise, the
45 secondary CPUs will spin in unprotected memory area because the
46 master CPU protects the relocated spin code.
48 U-Boot automatically does:
49 - Set "cpu-release-addr" property of each CPU node
50 (overwrites it if already exists).
51 - Reserve the code for the spin-table and the release address
52 via a /memreserve/ region in the Device Tree.
54 menu "ARMv8 secure monitor firmware"
55 config ARMV8_SEC_FIRMWARE_SUPPORT
56 bool "Enable ARMv8 secure monitor firmware framework support"
60 This framework is aimed at making secure monitor firmware load
62 Note: Only FIT format image is supported.
63 You should prepare and provide the below information:
64 - Address of secure firmware.
65 - Address to hold the return address from secure firmware.
66 - Secure firmware FIT image related information.
67 Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME
68 - The target exception level that secure monitor firmware will
71 config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
72 bool "Enable ARMv8 secure monitor firmware framework support for SPL"
76 Say Y here to support this framework in SPL phase.
78 config SPL_RECOVER_DATA_SECTION
79 bool "save/restore SPL data section"
81 Say Y here to save SPL data section for cold boot, and restore
82 at warm boot in SPL phase.
84 config SEC_FIRMWARE_ARMV8_PSCI
85 bool "PSCI implementation in secure monitor firmware"
86 depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
88 This config enables the ARMv8 PSCI implementation in secure monitor
89 firmware. This is a private PSCI implementation and different from
90 those implemented under the common ARMv8 PSCI framework.
92 config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
93 bool "ARMv8 secure monitor firmware ERET address byteorder swap"
94 depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
96 Say Y here when the endianness of the register or memory holding the
97 Secure firmware exception return address is different with core's.
102 bool "Use PSCI for reset and shutdown"
104 select ARM_SMCCC if OF_CONTROL
105 depends on !ARCH_APPLE && !ARCH_BCM283X && !ARCH_EXYNOS7 && \
106 !TARGET_LS2080AQDS && \
107 !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
108 !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
109 !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
110 !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
111 !TARGET_LS1012AFRWY && \
112 !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
113 !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
114 !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
115 !TARGET_LS1046AFRWY && \
116 !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
117 !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
120 Most armv8 systems have PSCI support enabled in EL3, either through
121 ARM Trusted Firmware or other firmware.
123 On these systems, we do not need to implement system reset manually,
124 but can instead rely on higher level firmware to deal with it.
126 Select Y here to make use of PSCI calls for system reset
129 bool "Enable PSCI support" if EXPERT
131 PSCI is Power State Coordination Interface defined by ARM.
132 The PSCI in U-boot provides a general framework and each platform
133 can implement their own specific PSCI functions.
134 Say Y here to enable PSCI support on ARMv8 platform.
136 config ARMV8_PSCI_NR_CPUS
137 int "Maximum supported CPUs for PSCI"
138 depends on ARMV8_PSCI
141 The maximum number of CPUs supported in the PSCI firmware.
142 It is no problem to set a larger value than the number of CPUs in
143 the actual hardware implementation.
145 config ARMV8_PSCI_CPUS_PER_CLUSTER
146 int "Number of CPUs per cluster"
147 depends on ARMV8_PSCI
150 The number of CPUs per cluster, suppose each cluster has same number
151 of CPU cores, platforms with asymmetric clusters don't apply here.
152 A value 0 or no definition of it works for single cluster system.
153 System with multi-cluster should difine their own exact value.
155 config ARMV8_EA_EL3_FIRST
156 bool "External aborts and SError interrupt exception are taken in EL3"
158 Exception handling at all exception levels for External Abort and
159 SError interrupt exception are taken in EL3.
161 if SYS_HAS_ARMV8_SECURE_BASE
163 config ARMV8_SECURE_BASE
164 hex "Secure address for PSCI image"
165 depends on ARMV8_PSCI
167 Address for placing the PSCI text, data and stack sections.
168 If not defined, the PSCI sections are placed together with the u-boot
169 but platform can choose to place PSCI code image separately in other
170 places such as some secure RAM built-in SOC etc.