3 * Andre Przywara, Linaro
5 * Routines to transition ARMv7 processors from secure into non-secure state
6 * needed to enable ARMv7 virtualization for current hypervisors
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/armv7.h>
32 unsigned long gic_dist_addr;
34 static unsigned int read_id_pfr1(void)
38 asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));
42 static unsigned long get_gicd_base_address(void)
44 #ifdef CONFIG_ARM_GIC_BASE_ADDRESS
45 return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
50 /* check whether we are an Cortex-A15 or A7.
51 * The actual HYP switch should work with all CPUs supporting
52 * the virtualization extension, but we need the GIC address,
53 * which we know only for sure for those two CPUs.
55 asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
56 switch (midr & MIDR_PRIMARY_PART_MASK) {
57 case MIDR_CORTEX_A9_R0P1:
58 case MIDR_CORTEX_A15_R0P0:
59 case MIDR_CORTEX_A7_R0P0:
62 printf("nonsec: could not determine GIC address.\n");
66 /* get the GIC base address from the CBAR register */
67 asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
69 /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
70 * encode this). Bail out here since we cannot access this without
73 if ((periphbase & 0xff) != 0) {
74 printf("nonsec: PERIPHBASE is above 4 GB, no access.\n");
78 return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
82 int armv7_switch_nonsec(void)
85 unsigned itlinesnr, i;
87 /* check whether the CPU supports the security extensions */
89 if ((reg & 0xF0) == 0) {
90 printf("nonsec: Security extensions not implemented.\n");
94 /* the SCR register will be set directly in the monitor mode handler,
95 * according to the spec one should not tinker with it in secure state
96 * in SVC mode. Do not try to read it once in non-secure state,
97 * any access to it will trap.
100 gic_dist_addr = get_gicd_base_address();
101 if (gic_dist_addr == -1)
104 /* enable the GIC distributor */
105 writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
106 gic_dist_addr + GICD_CTLR);
108 /* TYPER[4:0] contains an encoded number of available interrupts */
109 itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
111 /* set all bits in the GIC group registers to one to allow access
112 * from non-secure state. The first 32 interrupts are private per
113 * CPU and will be set later when enabling the GIC for each core
115 for (i = 1; i <= itlinesnr; i++)
116 writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
118 /* call the non-sec switching code on this CPU */