2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/arch/imx-regs.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/crm_regs.h>
26 #ifdef CONFIG_FSL_ESDHC
27 #include <fsl_esdhc.h>
30 #ifdef CONFIG_FSL_ESDHC
31 DECLARE_GLOBAL_DATA_PTR;
34 #ifdef CONFIG_MXC_OCOTP
35 void enable_ocotp_clk(unsigned char enable)
37 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
40 reg = readl(&ccm->ccgr6);
42 reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
44 reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
45 writel(reg, &ccm->ccgr6);
49 static u32 get_mcu_main_clk(void)
51 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
52 u32 ccm_ccsr, ccm_cacrr, armclk_div;
53 u32 sysclk_sel, pll_pfd_sel = 0;
56 ccm_ccsr = readl(&ccm->ccsr);
57 sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
58 sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
60 ccm_cacrr = readl(&ccm->cacrr);
61 armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
62 armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
73 pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
74 pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
76 freq = PLL2_MAIN_FREQ;
77 else if (pll_pfd_sel == 1)
78 freq = PLL2_PFD1_FREQ;
79 else if (pll_pfd_sel == 2)
80 freq = PLL2_PFD2_FREQ;
81 else if (pll_pfd_sel == 3)
82 freq = PLL2_PFD3_FREQ;
83 else if (pll_pfd_sel == 4)
84 freq = PLL2_PFD4_FREQ;
87 freq = PLL2_MAIN_FREQ;
90 pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
91 pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
93 freq = PLL1_MAIN_FREQ;
94 else if (pll_pfd_sel == 1)
95 freq = PLL1_PFD1_FREQ;
96 else if (pll_pfd_sel == 2)
97 freq = PLL1_PFD2_FREQ;
98 else if (pll_pfd_sel == 3)
99 freq = PLL1_PFD3_FREQ;
100 else if (pll_pfd_sel == 4)
101 freq = PLL1_PFD4_FREQ;
104 freq = PLL3_MAIN_FREQ;
107 printf("unsupported system clock select\n");
110 return freq / armclk_div;
113 static u32 get_bus_clk(void)
115 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
116 u32 ccm_cacrr, busclk_div;
118 ccm_cacrr = readl(&ccm->cacrr);
120 busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
121 busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
124 return get_mcu_main_clk() / busclk_div;
127 static u32 get_ipg_clk(void)
129 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
130 u32 ccm_cacrr, ipgclk_div;
132 ccm_cacrr = readl(&ccm->cacrr);
134 ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
135 ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
138 return get_bus_clk() / ipgclk_div;
141 static u32 get_uart_clk(void)
143 return get_ipg_clk();
146 static u32 get_sdhc_clk(void)
148 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
149 u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
152 ccm_cscmr1 = readl(&ccm->cscmr1);
153 sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
154 sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
156 ccm_cscdr2 = readl(&ccm->cscdr2);
157 sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
158 sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
161 switch (sdhc_clk_sel) {
163 freq = PLL3_MAIN_FREQ;
166 freq = PLL3_PFD3_FREQ;
169 freq = PLL1_PFD3_FREQ;
172 freq = get_bus_clk();
176 return freq / sdhc_clk_div;
179 u32 get_fec_clk(void)
181 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
182 u32 ccm_cscmr2, rmii_clk_sel;
185 ccm_cscmr2 = readl(&ccm->cscmr2);
186 rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
187 rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
189 switch (rmii_clk_sel) {
191 freq = ENET_EXTERNAL_CLK;
194 freq = AUDIO_EXTERNAL_CLK;
197 freq = PLL5_MAIN_FREQ;
200 freq = PLL5_MAIN_FREQ / 2;
207 unsigned int mxc_get_clock(enum mxc_clock clk)
211 return get_mcu_main_clk();
213 return get_bus_clk();
215 return get_ipg_clk();
217 return get_uart_clk();
219 return get_sdhc_clk();
221 return get_fec_clk();
228 /* Dump some core clocks */
229 int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
233 printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
234 printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
235 printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
241 clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
246 #ifdef CONFIG_FEC_MXC
247 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
249 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
250 struct fuse_bank *bank = &ocotp->bank[4];
251 struct fuse_bank4_regs *fuse =
252 (struct fuse_bank4_regs *)bank->fuse_regs;
254 u32 value = readl(&fuse->mac_addr0);
255 mac[0] = (value >> 8);
258 value = readl(&fuse->mac_addr1);
259 mac[2] = value >> 24;
260 mac[3] = value >> 16;
266 #if defined(CONFIG_DISPLAY_CPUINFO)
267 static char *get_reset_cause(void)
270 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
272 cause = readl(&src_regs->srsr);
273 writel(cause, &src_regs->srsr);
280 return "JTAG HIGH-Z";
282 return "EXTERNAL RESET";
286 return "unknown reset";
290 int print_cpuinfo(void)
292 printf("CPU: Freescale Vybrid VF610 at %d MHz\n",
293 mxc_get_clock(MXC_ARM_CLK) / 1000000);
294 printf("Reset cause: %s\n", get_reset_cause());
300 int cpu_eth_init(bd_t *bis)
304 #if defined(CONFIG_FEC_MXC)
305 rc = fecmxc_initialize(bis);
311 #ifdef CONFIG_FSL_ESDHC
312 int cpu_mmc_init(bd_t *bis)
314 return fsl_esdhc_mmc_init(bis);
320 #ifdef CONFIG_FSL_ESDHC
321 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);