2 * Copyright (C) 2011-2014 Panasonic Corporation
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/umc-regs.h>
10 #include <asm/arch/ddrphy-regs.h>
12 static inline void umc_start_ssif(void __iomem *ssif_base)
14 writel(0x00000001, ssif_base + 0x0000b004);
15 writel(0xffffffff, ssif_base + 0x0000c004);
16 writel(0x07ffffff, ssif_base + 0x0000c008);
17 writel(0x00000001, ssif_base + 0x0000b000);
18 writel(0x00000001, ssif_base + 0x0000c000);
20 writel(0x03010100, ssif_base + UMC_HDMCHSEL);
21 writel(0x03010101, ssif_base + UMC_MDMCHSEL);
22 writel(0x03010100, ssif_base + UMC_DVCCHSEL);
23 writel(0x03010100, ssif_base + UMC_DMDCHSEL);
25 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
26 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
27 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
28 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
29 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
30 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
31 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
32 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
33 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
34 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
35 writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
37 writel(0x00000001, ssif_base + UMC_CPURST);
38 writel(0x00000001, ssif_base + UMC_IDSRST);
39 writel(0x00000001, ssif_base + UMC_IXMRST);
40 writel(0x00000001, ssif_base + UMC_HDMRST);
41 writel(0x00000001, ssif_base + UMC_MDMRST);
42 writel(0x00000001, ssif_base + UMC_HDDRST);
43 writel(0x00000001, ssif_base + UMC_MDDRST);
44 writel(0x00000001, ssif_base + UMC_SIORST);
45 writel(0x00000001, ssif_base + UMC_GIORST);
46 writel(0x00000001, ssif_base + UMC_HD2RST);
47 writel(0x00000001, ssif_base + UMC_VIORST);
48 writel(0x00000001, ssif_base + UMC_DVCRST);
49 writel(0x00000001, ssif_base + UMC_RGLRST);
50 writel(0x00000001, ssif_base + UMC_VPERST);
51 writel(0x00000001, ssif_base + UMC_AIORST);
52 writel(0x00000001, ssif_base + UMC_DMDRST);
55 static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
58 writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
59 writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
60 writel(0x5101387f, dramcont + UMC_INITCTLA);
61 writel(0x43030d3f, dramcont + UMC_INITCTLB);
62 writel(0x00ff00ff, dramcont + UMC_INITCTLC);
63 writel(0x00000d71, dramcont + UMC_DRMMR0);
64 writel(0x00000006, dramcont + UMC_DRMMR1);
65 writel(0x00000298, dramcont + UMC_DRMMR2);
66 writel(0x00000000, dramcont + UMC_DRMMR3);
67 writel(0x003f0617, dramcont + UMC_SPCCTLA);
68 writel(0x00ff0008, dramcont + UMC_SPCCTLB);
69 writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
70 writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
71 writel(0x04060802, dramcont + UMC_WDATACTL_D0);
72 writel(0x04060802, dramcont + UMC_WDATACTL_D1);
73 writel(0x04a02000, dramcont + UMC_DATASET);
74 writel(0x00000000, ca_base + 0x2300);
75 writel(0x00400020, dramcont + UMC_DCCGCTL);
76 writel(0x0000000f, dramcont + 0x7000);
77 writel(0x0000000f, dramcont + 0x8000);
78 writel(0x000000c3, dramcont + 0x8004);
79 writel(0x00000071, dramcont + 0x8008);
80 writel(0x00000004, dramcont + UMC_FLOWCTLG);
81 writel(0x00000000, dramcont + 0x0060);
82 writel(0x80000201, ca_base + 0xc20);
83 writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
84 writel(0x00200000, dramcont + UMC_FLOWCTLB);
85 writel(0x00004444, dramcont + UMC_FLOWCTLC);
86 writel(0x200a0a00, dramcont + UMC_SPCSETB);
87 writel(0x00010000, dramcont + UMC_SPCSETD);
88 writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
91 static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
93 void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
94 void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
95 void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
96 void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
97 void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
98 void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
99 void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
100 void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
101 void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
103 umc_dram_init_start(dramcont0);
104 umc_dram_init_start(dramcont1);
105 umc_dram_init_poll(dramcont0);
106 umc_dram_init_poll(dramcont1);
108 writel(0x00000101, dramcont0 + UMC_DIOCTLA);
110 ddrphy_init(phy0_0, freq, size_ch0);
112 ddrphy_prepare_training(phy0_0, 0);
113 ddrphy_training(phy0_0);
115 writel(0x00000103, dramcont0 + UMC_DIOCTLA);
117 ddrphy_init(phy0_1, freq, size_ch0);
119 ddrphy_prepare_training(phy0_1, 1);
120 ddrphy_training(phy0_1);
122 writel(0x00000101, dramcont1 + UMC_DIOCTLA);
124 ddrphy_init(phy1_0, freq, size_ch1);
126 ddrphy_prepare_training(phy1_0, 0);
127 ddrphy_training(phy1_0);
129 writel(0x00000103, dramcont1 + UMC_DIOCTLA);
131 ddrphy_init(phy1_1, freq, size_ch1);
133 ddrphy_prepare_training(phy1_1, 1);
134 ddrphy_training(phy1_1);
136 umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
137 umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
139 umc_start_ssif(ssif_base);
146 return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
147 CONFIG_SDRAM1_SIZE / 0x08000000);
150 #if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
151 (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
152 ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
153 (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1))
156 #error Unsupported DDR configuration.