2 * Copyright (C) 2011-2014 Panasonic Corporation
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/sc-regs.h>
10 #include <asm/arch/sg-regs.h>
12 #undef DPLL_SSC_RATE_1PER
20 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
21 * to FOUT ( DPLLCTRL.bit[29:20] )
23 tmp = readl(SC_DPLLCTRL);
25 #if CONFIG_DDR_FREQ == 1600
27 #elif CONFIG_DDR_FREQ == 1333
30 # error "Unsupported frequency"
35 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
37 #if defined(DPLL_SSC_RATE_1PER)
42 writel(tmp, SC_DPLLCTRL);
44 tmp = readl(SC_DPLLCTRL2);
45 tmp |= SC_DPLLCTRL2_NRSTDS;
46 writel(tmp, SC_DPLLCTRL2);
53 tmp = readl(SC_MPLLOSCCTL);
55 if (!(tmp & SC_MPLLOSCCTL_MPLLST))
56 return; /* already stopped */
58 tmp &= ~SC_MPLLOSCCTL_MPLLEN;
59 writel(tmp, SC_MPLLOSCCTL);
61 while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST)
67 u32 tmp, clk_mode_axosel;
69 /* Set VPLL27A & VPLL27B */
70 tmp = readl(SG_PINMON0);
71 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
73 #if defined(CONFIG_MACH_PH1_PRO4)
74 /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
75 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
76 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
80 /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
81 tmp = readl(SC_VPLL27ACTRL);
83 writel(tmp, SC_VPLL27ACTRL);
84 tmp = readl(SC_VPLL27BCTRL);
86 writel(tmp, SC_VPLL27BCTRL);
88 /* Unset VPLA_K_LD and VPLB_K_LD bit */
89 tmp = readl(SC_VPLL27ACTRL3);
91 writel(tmp, SC_VPLL27ACTRL3);
92 tmp = readl(SC_VPLL27BCTRL3);
94 writel(tmp, SC_VPLL27BCTRL3);
96 /* Set VPLA_M and VPLB_M to 0x20 */
97 tmp = readl(SC_VPLL27ACTRL2);
100 writel(tmp, SC_VPLL27ACTRL2);
101 tmp = readl(SC_VPLL27BCTRL2);
104 writel(tmp, SC_VPLL27BCTRL2);
106 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
107 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
108 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
109 tmp = readl(SC_VPLL27ACTRL3);
112 writel(tmp, SC_VPLL27ACTRL3);
113 tmp = readl(SC_VPLL27BCTRL3);
116 writel(tmp, SC_VPLL27BCTRL3);
118 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
119 tmp = readl(SC_VPLL27ACTRL3);
122 writel(tmp, SC_VPLL27ACTRL3);
123 tmp = readl(SC_VPLL27BCTRL3);
126 writel(tmp, SC_VPLL27BCTRL3);
132 /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
133 tmp = readl(SC_VPLL27ACTRL3);
135 writel(tmp, SC_VPLL27ACTRL3);
136 tmp = readl(SC_VPLL27BCTRL3);
138 writel(tmp, SC_VPLL27BCTRL3);
140 /* Unset VPLA_SNRST and VPLB_SNRST bit */
141 tmp = readl(SC_VPLL27ACTRL2);
143 writel(tmp, SC_VPLL27ACTRL2);
144 tmp = readl(SC_VPLL27BCTRL2);
146 writel(tmp, SC_VPLL27BCTRL2);
148 /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
149 tmp = readl(SC_VPLL27ACTRL);
151 writel(tmp, SC_VPLL27ACTRL);
152 tmp = readl(SC_VPLL27BCTRL);
154 writel(tmp, SC_VPLL27BCTRL);
164 * Wait 500 usec until dpll get stable
165 * We wait 1 usec in vpll_init() so 1 usec can be saved here.