2 * Sunxi usb-controller code shared between the ehci and musb controllers
4 * Copyright (C) 2014 Roman Byshko
6 * Roman Byshko <rbyshko@gmail.com>
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
11 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/usbc.h>
20 #ifdef CONFIG_AXP152_POWER
23 #ifdef CONFIG_AXP209_POWER
26 #ifdef CONFIG_AXP221_POWER
30 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800
31 #define SUNXI_USB_CSR 0x404
32 #define SUNXI_USB_PASSBY_EN 1
34 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
35 #define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
36 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
37 #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
39 static struct sunxi_usbc_hcd {
46 } sunxi_usbc_hcd[] = {
48 .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
49 .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB0,
50 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
58 .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
59 .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
60 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
67 #if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1)
69 .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
70 .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1,
71 #ifdef CONFIG_MACH_SUN6I
81 static int enabled_hcd_count;
83 static bool use_axp_drivebus(int index)
86 strcmp(CONFIG_USB0_VBUS_PIN, "axp_drivebus") == 0;
89 void *sunxi_usbc_get_io_base(int index)
93 return (void *)SUNXI_USB0_BASE;
95 return (void *)SUNXI_USB1_BASE;
97 return (void *)SUNXI_USB2_BASE;
103 static int get_vbus_gpio(int index)
105 if (use_axp_drivebus(index))
109 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
110 case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
111 case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
116 static void usb_phy_write(struct sunxi_usbc_hcd *sunxi_usbc, int addr,
119 int j = 0, usbc_bit = 0;
120 void *dest = sunxi_usbc_get_io_base(0) + SUNXI_USB_CSR;
122 usbc_bit = 1 << (sunxi_usbc->id * 2);
123 for (j = 0; j < len; j++) {
124 /* set the bit address to be written */
125 clrbits_le32(dest, 0xff << 8);
126 setbits_le32(dest, (addr + j) << 8);
128 clrbits_le32(dest, usbc_bit);
131 setbits_le32(dest, 1 << 7);
133 clrbits_le32(dest, 1 << 7);
135 setbits_le32(dest, usbc_bit);
137 clrbits_le32(dest, usbc_bit);
143 static void sunxi_usb_phy_init(struct sunxi_usbc_hcd *sunxi_usbc)
145 /* The following comments are machine
146 * translated from Chinese, you have been warned!
149 /* Regulation 45 ohms */
150 if (sunxi_usbc->id == 0)
151 usb_phy_write(sunxi_usbc, 0x0c, 0x01, 1);
153 /* adjust PHY's magnitude and rate */
154 usb_phy_write(sunxi_usbc, 0x20, 0x14, 5);
156 /* threshold adjustment disconnect */
157 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN6I
158 usb_phy_write(sunxi_usbc, 0x2a, 3, 2);
160 usb_phy_write(sunxi_usbc, 0x2a, 2, 2);
166 static void sunxi_usb_passby(struct sunxi_usbc_hcd *sunxi_usbc, int enable)
168 unsigned long bits = 0;
169 void *addr = sunxi_usbc_get_io_base(sunxi_usbc->id) +
170 SUNXI_USB_PMU_IRQ_ENABLE;
172 bits = SUNXI_EHCI_AHB_ICHR8_EN |
173 SUNXI_EHCI_AHB_INCR4_BURST_EN |
174 SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
175 SUNXI_EHCI_ULPI_BYPASS_EN;
178 setbits_le32(addr, bits);
180 clrbits_le32(addr, bits);
185 void sunxi_usbc_enable_squelch_detect(int index, int enable)
187 struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
189 usb_phy_write(sunxi_usbc, 0x3c, enable ? 0 : 2, 2);
192 int sunxi_usbc_request_resources(int index)
194 struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
196 sunxi_usbc->gpio_vbus = get_vbus_gpio(index);
197 if (sunxi_usbc->gpio_vbus != -1)
198 return gpio_request(sunxi_usbc->gpio_vbus, "usbc_vbus");
203 int sunxi_usbc_free_resources(int index)
205 struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
207 if (sunxi_usbc->gpio_vbus != -1)
208 return gpio_free(sunxi_usbc->gpio_vbus);
213 void sunxi_usbc_enable(int index)
215 struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
216 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
218 /* enable common PHY only once */
219 if (enabled_hcd_count == 0)
220 setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
222 setbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask);
223 setbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask);
224 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
225 setbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask);
228 sunxi_usb_phy_init(sunxi_usbc);
230 if (sunxi_usbc->id != 0)
231 sunxi_usb_passby(sunxi_usbc, SUNXI_USB_PASSBY_EN);
236 void sunxi_usbc_disable(int index)
238 struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
239 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
241 if (sunxi_usbc->id != 0)
242 sunxi_usb_passby(sunxi_usbc, !SUNXI_USB_PASSBY_EN);
244 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
245 clrbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask);
247 clrbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask);
248 clrbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask);
250 /* disable common PHY only once, for the last enabled hcd */
251 if (enabled_hcd_count == 1)
252 clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
257 void sunxi_usbc_vbus_enable(int index)
259 struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
262 if (use_axp_drivebus(index))
263 axp_drivebus_enable();
265 if (sunxi_usbc->gpio_vbus != -1)
266 gpio_direction_output(sunxi_usbc->gpio_vbus, 1);
269 void sunxi_usbc_vbus_disable(int index)
271 struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
274 if (use_axp_drivebus(index))
275 axp_drivebus_disable();
277 if (sunxi_usbc->gpio_vbus != -1)
278 gpio_direction_output(sunxi_usbc->gpio_vbus, 0);