arch/arm/cpu/armv7/sunxi/dram.c

   1 /*
   2  * sunxi DRAM controller initialization
   3  * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
   4  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   5  *
   6  * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
   7  * and earlier U-Boot Allwiner A10 SPL work
   8  *
   9  * (C) Copyright 2007-2012
  10  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  11  * Berg Xing <bergxing@allwinnertech.com>
  12  * Tom Cubie <tangliang@allwinnertech.com>
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 /*
  18  * Unfortunately the only documentation we have on the sun7i DRAM
  19  * controller is Allwinner boot0 + boot1 code, and that code uses
  20  * magic numbers & shifts with no explanations. Hence this code is
  21  * rather undocumented and full of magic.
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/dram.h>
  28 #include <asm/arch/timer.h>
  29 #include <asm/arch/sys_proto.h>
  30
  31 #define CPU_CFG_CHIP_VER(n) ((n) << 6)
  32 #define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
  33 #define CPU_CFG_CHIP_REV_A 0x0
  34 #define CPU_CFG_CHIP_REV_C1 0x1
  35 #define CPU_CFG_CHIP_REV_C2 0x2
  36 #define CPU_CFG_CHIP_REV_B 0x3
  37
  38 /*
  39  * Wait up to 1s for mask to be clear in given reg.
  40  */
  41 static void await_completion(u32 *reg, u32 mask)
  42 {
  43         unsigned long tmo = timer_get_us() + 1000000;
  44
  45         while (readl(reg) & mask) {
  46                 if (timer_get_us() > tmo)
  47                         panic("Timeout initialising DRAM\n");
  48         }
  49 }
  50
  51 /*
  52  * This performs the external DRAM reset by driving the RESET pin low and
  53  * then high again. According to the DDR3 spec, the RESET pin needs to be
  54  * kept low for at least 200 us.
  55  */
  56 static void mctl_ddr3_reset(void)
  57 {
  58         struct sunxi_dram_reg *dram =
  59                         (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  60
  61 #ifdef CONFIG_SUN4I
  62         struct sunxi_timer_reg *timer =
  63                         (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
  64         u32 reg_val;
  65
  66         writel(0, &timer->cpu_cfg);
  67         reg_val = readl(&timer->cpu_cfg);
  68
  69         if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
  70             CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
  71                 setbits_le32(&dram->mcr, DRAM_MCR_RESET);
  72                 udelay(200);
  73                 clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
  74         } else
  75 #endif
  76         {
  77                 clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
  78                 udelay(200);
  79                 setbits_le32(&dram->mcr, DRAM_MCR_RESET);
  80         }
  81         /* After the RESET pin is de-asserted, the DDR3 spec requires to wait
  82          * for additional 500 us before driving the CKE pin (Clock Enable)
  83          * high. The duration of this delay can be configured in the SDR_IDCR
  84          * (Initialization Delay Configuration Register) and applied
  85          * automatically by the DRAM controller during the DDR3 initialization
  86          * step. But SDR_IDCR has limited range on sun4i/sun5i hardware and
  87          * can't provide sufficient delay at DRAM clock frequencies higher than
  88          * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to
  89          * 533 MHz according to the datasheet). Additionally, there is no
  90          * official documentation for the SDR_IDCR register anywhere, and
  91          * there is always a chance that we are interpreting it wrong.
  92          * Better be safe than sorry, so add an explicit delay here. */
  93         udelay(500);
  94 }
  95
  96 static void mctl_set_drive(void)
  97 {
  98         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  99
 100 #ifdef CONFIG_SUN7I
 101         clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
 102 #else
 103         clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
 104 #endif
 105                         DRAM_MCR_MODE_EN(0x3) |
 106                         0xffc);
 107 }
 108
 109 static void mctl_itm_disable(void)
 110 {
 111         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 112
 113         clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);
 114 }
 115
 116 static void mctl_itm_enable(void)
 117 {
 118         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 119
 120         clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
 121 }
 122
 123 static void mctl_enable_dll0(u32 phase)
 124 {
 125         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 126
 127         clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
 128                         ((phase >> 16) & 0x3f) << 6);
 129         clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);
 130         udelay(2);
 131
 132         clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);
 133         udelay(22);
 134
 135         clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);
 136         udelay(22);
 137 }
 138
 139 /*
 140  * Note: This differs from pm/standby in that it checks the bus width
 141  */
 142 static void mctl_enable_dllx(u32 phase)
 143 {
 144         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 145         u32 i, n, bus_width;
 146
 147         bus_width = readl(&dram->dcr);
 148
 149         if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) ==
 150             DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
 151                 n = DRAM_DCR_NR_DLLCR_32BIT;
 152         else
 153                 n = DRAM_DCR_NR_DLLCR_16BIT;
 154
 155         for (i = 1; i < n; i++) {
 156                 clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
 157                                 (phase & 0xf) << 14);
 158                 clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
 159                                 DRAM_DLLCR_DISABLE);
 160                 phase >>= 4;
 161         }
 162         udelay(2);
 163
 164         for (i = 1; i < n; i++)
 165                 clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
 166                              DRAM_DLLCR_DISABLE);
 167         udelay(22);
 168
 169         for (i = 1; i < n; i++)
 170                 clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
 171                                 DRAM_DLLCR_NRESET);
 172         udelay(22);
 173 }
 174
 175 static u32 hpcr_value[32] = {
 176 #ifdef CONFIG_SUN5I
 177         0, 0, 0, 0,
 178         0, 0, 0, 0,
 179         0, 0, 0, 0,
 180         0, 0, 0, 0,
 181         0x1031, 0x1031, 0x0735, 0x1035,
 182         0x1035, 0x0731, 0x1031, 0,
 183         0x0301, 0x0301, 0x0301, 0x0301,
 184         0x0301, 0x0301, 0x0301, 0
 185 #endif
 186 #ifdef CONFIG_SUN4I
 187         0x0301, 0x0301, 0x0301, 0x0301,
 188         0x0301, 0x0301, 0, 0,
 189         0, 0, 0, 0,
 190         0, 0, 0, 0,
 191         0x1031, 0x1031, 0x0735, 0x5031,
 192         0x1035, 0x0731, 0x1031, 0x0735,
 193         0x1035, 0x1031, 0x0731, 0x1035,
 194         0x1031, 0x0301, 0x0301, 0x0731
 195 #endif
 196 #ifdef CONFIG_SUN7I
 197         0x0301, 0x0301, 0x0301, 0x0301,
 198         0x0301, 0x0301, 0x0301, 0x0301,
 199         0, 0, 0, 0,
 200         0, 0, 0, 0,
 201         0x1031, 0x1031, 0x0735, 0x1035,
 202         0x1035, 0x0731, 0x1031, 0x0735,
 203         0x1035, 0x1031, 0x0731, 0x1035,
 204         0x0001, 0x1031, 0, 0x1031
 205         /* last row differs from boot0 source table
 206          * 0x1031, 0x0301, 0x0301, 0x0731
 207          * but boot0 code skips #28 and #30, and sets #29 and #31 to the
 208          * value from #28 entry (0x1031)
 209          */
 210 #endif
 211 };
 212
 213 static void mctl_configure_hostport(void)
 214 {
 215         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 216         u32 i;
 217
 218         for (i = 0; i < 32; i++)
 219                 writel(hpcr_value[i], &dram->hpcr[i]);
 220 }
 221
 222 static void mctl_setup_dram_clock(u32 clk)
 223 {
 224         u32 reg_val;
 225         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 226
 227         /* setup DRAM PLL */
 228         reg_val = readl(&ccm->pll5_cfg);
 229         reg_val &= ~CCM_PLL5_CTRL_M_MASK;               /* set M to 0 (x1) */
 230         reg_val &= ~CCM_PLL5_CTRL_K_MASK;               /* set K to 0 (x1) */
 231         reg_val &= ~CCM_PLL5_CTRL_N_MASK;               /* set N to 0 (x0) */
 232         reg_val &= ~CCM_PLL5_CTRL_P_MASK;               /* set P to 0 (x1) */
 233         if (clk >= 540 && clk < 552) {
 234                 /* dram = 540MHz, pll5p = 540MHz */
 235                 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 236                 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
 237                 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
 238                 reg_val |= CCM_PLL5_CTRL_P(1);
 239         } else if (clk >= 512 && clk < 528) {
 240                 /* dram = 512MHz, pll5p = 384MHz */
 241                 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
 242                 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
 243                 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
 244                 reg_val |= CCM_PLL5_CTRL_P(2);
 245         } else if (clk >= 496 && clk < 504) {
 246                 /* dram = 496MHz, pll5p = 372MHz */
 247                 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
 248                 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
 249                 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
 250                 reg_val |= CCM_PLL5_CTRL_P(2);
 251         } else if (clk >= 468 && clk < 480) {
 252                 /* dram = 468MHz, pll5p = 468MHz */
 253                 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 254                 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
 255                 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
 256                 reg_val |= CCM_PLL5_CTRL_P(1);
 257         } else if (clk >= 396 && clk < 408) {
 258                 /* dram = 396MHz, pll5p = 396MHz */
 259                 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 260                 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
 261                 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
 262                 reg_val |= CCM_PLL5_CTRL_P(1);
 263         } else  {
 264                 /* any other frequency that is a multiple of 24 */
 265                 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 266                 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
 267                 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
 268                 reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
 269         }
 270         reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN;             /* PLL VCO Gain off */
 271         reg_val |= CCM_PLL5_CTRL_EN;                    /* PLL On */
 272         writel(reg_val, &ccm->pll5_cfg);
 273         udelay(5500);
 274
 275         setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
 276
 277 #if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
 278         /* reset GPS */
 279         clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
 280         setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
 281         udelay(1);
 282         clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
 283 #endif
 284
 285 #if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 286         /* setup MBUS clock */
 287         reg_val = CCM_MBUS_CTRL_GATE |
 288 #ifdef CONFIG_SUN7I
 289                   CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
 290                   CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
 291                   CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
 292 #else /* defined(CONFIG_SUN5I) */
 293                   CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
 294                   CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
 295                   CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
 296 #endif
 297         writel(reg_val, &ccm->mbus_clk_cfg);
 298 #endif
 299
 300         /*
 301          * open DRAMC AHB & DLL register clock
 302          * close it first
 303          */
 304 #if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 305         clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
 306 #else
 307         clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
 308 #endif
 309         udelay(22);
 310
 311         /* then open it */
 312 #if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 313         setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
 314 #else
 315         setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
 316 #endif
 317         udelay(22);
 318 }
 319
 320 static int dramc_scan_readpipe(void)
 321 {
 322         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 323         u32 reg_val;
 324
 325         /* data training trigger */
 326 #ifdef CONFIG_SUN7I
 327         clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
 328 #endif
 329         setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
 330
 331         /* check whether data training process has completed */
 332         await_completion(&dram->ccr, DRAM_CCR_DATA_TRAINING);
 333
 334         /* check data training result */
 335         reg_val = readl(&dram->csr);
 336         if (reg_val & DRAM_CSR_FAILED)
 337                 return -1;
 338
 339         return 0;
 340 }
 341
 342 static void dramc_clock_output_en(u32 on)
 343 {
 344 #if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 345         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 346
 347         if (on)
 348                 setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
 349         else
 350                 clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
 351 #endif
 352 #ifdef CONFIG_SUN4I
 353         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 354         if (on)
 355                 setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
 356         else
 357                 clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
 358 #endif
 359 }
 360
 361 static const u16 tRFC_table[2][6] = {
 362         /*       256Mb    512Mb    1Gb      2Gb      4Gb      8Gb      */
 363         /* DDR2  75ns     105ns    127.5ns  195ns    327.5ns  invalid  */
 364         {        77,      108,     131,     200,     336,     336 },
 365         /* DDR3  invalid  90ns     110ns    160ns    300ns    350ns    */
 366         {        93,      93,      113,     164,     308,     359 }
 367 };
 368
 369 static void dramc_set_autorefresh_cycle(u32 clk, u32 type, u32 density)
 370 {
 371         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 372         u32 tRFC, tREFI;
 373
 374         tRFC = (tRFC_table[type][density] * clk + 1023) >> 10;
 375         tREFI = (7987 * clk) >> 10;     /* <= 7.8us */
 376
 377         writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
 378 }
 379
 380 /*
 381  * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
 382  * means that DRAM is currently in self-refresh mode and retaining the old
 383  * data. Since we have no idea what to do in this situation yet, just set this
 384  * register to 0 and initialize DRAM in the same way as on any normal reboot
 385  * (discarding whatever was stored there).
 386  *
 387  * Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic
 388  * value for this write operation to have any effect. On sun5i hadware this
 389  * magic value is not necessary. And on sun4i hardware the writes to this
 390  * register seem to have no effect at all.
 391  */
 392 static void mctl_disable_power_save(void)
 393 {
 394         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 395         writel(0x16510000, &dram->ppwrsctl);
 396 }
 397
 398 /*
 399  * After the DRAM is powered up or reset, the DDR3 spec requires to wait at
 400  * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct
 401  * (SDR_IDCR) register appears to configure this delay, which gets applied
 402  * right at the time when the DRAM initialization is activated in the
 403  * 'mctl_ddr3_initialize' function.
 404  */
 405 static void mctl_set_cke_delay(void)
 406 {
 407         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 408
 409         /* The CKE delay is represented in DRAM clock cycles, multiplied by N
 410          * (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to
 411          * the maximum possible value 0x1ffff, just like in the Allwinner's
 412          * boot0 bootloader. The resulting delay value is somewhere between
 413          * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i
 414          * with 360 MHz DRAM clock speed). */
 415         setbits_le32(&dram->idcr, 0x1ffff);
 416 }
 417
 418 /*
 419  * This triggers the DRAM initialization. It performs sending the mode registers
 420  * to the DRAM among other things. Very likely the ZQCL command is also getting
 421  * executed (to do the initial impedance calibration on the DRAM side of the
 422  * wire). The memory controller and the PHY must be already configured before
 423  * calling this function.
 424  */
 425 static void mctl_ddr3_initialize(void)
 426 {
 427         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 428         setbits_le32(&dram->ccr, DRAM_CCR_INIT);
 429         await_completion(&dram->ccr, DRAM_CCR_INIT);
 430 }
 431
 432 unsigned long dramc_init(struct dram_para *para)
 433 {
 434         struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 435         u32 reg_val;
 436         u32 density;
 437         int ret_val;
 438
 439         /* check input dram parameter structure */
 440         if (!para)
 441                 return 0;
 442
 443         /* setup DRAM relative clock */
 444         mctl_setup_dram_clock(para->clock);
 445
 446         /* Disable any pad power save control */
 447         mctl_disable_power_save();
 448
 449         mctl_set_drive();
 450
 451         /* dram clock off */
 452         dramc_clock_output_en(0);
 453
 454 #ifdef CONFIG_SUN4I
 455         /* select dram controller 1 */
 456         writel(DRAM_CSEL_MAGIC, &dram->csel);
 457 #endif
 458
 459         mctl_itm_disable();
 460         mctl_enable_dll0(para->tpr3);
 461
 462         /* configure external DRAM */
 463         reg_val = 0x0;
 464         if (para->type == DRAM_MEMORY_TYPE_DDR3)
 465                 reg_val |= DRAM_DCR_TYPE_DDR3;
 466         reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
 467
 468         if (para->density == 256)
 469                 density = DRAM_DCR_CHIP_DENSITY_256M;
 470         else if (para->density == 512)
 471                 density = DRAM_DCR_CHIP_DENSITY_512M;
 472         else if (para->density == 1024)
 473                 density = DRAM_DCR_CHIP_DENSITY_1024M;
 474         else if (para->density == 2048)
 475                 density = DRAM_DCR_CHIP_DENSITY_2048M;
 476         else if (para->density == 4096)
 477                 density = DRAM_DCR_CHIP_DENSITY_4096M;
 478         else if (para->density == 8192)
 479                 density = DRAM_DCR_CHIP_DENSITY_8192M;
 480         else
 481                 density = DRAM_DCR_CHIP_DENSITY_256M;
 482
 483         reg_val |= DRAM_DCR_CHIP_DENSITY(density);
 484         reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
 485         reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
 486         reg_val |= DRAM_DCR_CMD_RANK_ALL;
 487         reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
 488         writel(reg_val, &dram->dcr);
 489
 490         dramc_clock_output_en(1);
 491
 492         mctl_set_cke_delay();
 493
 494         mctl_ddr3_reset();
 495
 496         udelay(1);
 497
 498         await_completion(&dram->ccr, DRAM_CCR_INIT);
 499
 500         mctl_enable_dllx(para->tpr3);
 501
 502         /* set refresh period */
 503         dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
 504
 505         /* set timing parameters */
 506         writel(para->tpr0, &dram->tpr0);
 507         writel(para->tpr1, &dram->tpr1);
 508         writel(para->tpr2, &dram->tpr2);
 509
 510         if (para->type == DRAM_MEMORY_TYPE_DDR3) {
 511                 reg_val = DRAM_MR_BURST_LENGTH(0x0);
 512 #if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
 513                 reg_val |= DRAM_MR_POWER_DOWN;
 514 #endif
 515                 reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
 516                 reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
 517         } else if (para->type == DRAM_MEMORY_TYPE_DDR2) {
 518                 reg_val = DRAM_MR_BURST_LENGTH(0x2);
 519                 reg_val |= DRAM_MR_CAS_LAT(para->cas);
 520                 reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
 521         }
 522         writel(reg_val, &dram->mr);
 523
 524         writel(para->emr1, &dram->emr);
 525         writel(para->emr2, &dram->emr2);
 526         writel(para->emr3, &dram->emr3);
 527
 528         /* set DQS window mode */
 529         clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
 530
 531 #ifdef CONFIG_SUN7I
 532         /* Command rate timing mode 2T & 1T */
 533         if (para->tpr4 & 0x1)
 534                 setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
 535 #endif
 536         /* initialize external DRAM */
 537         mctl_ddr3_initialize();
 538
 539         /* scan read pipe value */
 540         mctl_itm_enable();
 541         ret_val = dramc_scan_readpipe();
 542
 543         if (ret_val < 0)
 544                 return 0;
 545
 546         /* configure all host port */
 547         mctl_configure_hostport();
 548
 549         return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
 550 }