arch/arm/cpu/armv7/sunxi/clock_sun6i.c

   1 /*
   2  * sun6i specific clock code
   3  *
   4  * (C) Copyright 2007-2012
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/prcm.h>
  17 #include <asm/arch/sys_proto.h>
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 void clock_init_safe(void)
  21 {
  22         struct sunxi_ccm_reg * const ccm =
  23                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  24         struct sunxi_prcm_reg * const prcm =
  25                 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
  26
  27         /* Set PLL ldo voltage without this PLL6 does not work properly */
  28         clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
  29                         PRCM_PLL_CTRL_LDO_KEY);
  30         clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
  31                 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
  32                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
  33         clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
  34
  35         clock_set_pll1(408000000);
  36
  37         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  38         while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
  39                 ;
  40
  41         writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
  42
  43         writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
  44         writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
  45 }
  46 #endif
  47
  48 void clock_init_sec(void)
  49 {
  50 #ifdef CONFIG_MACH_SUN8I_H3
  51         struct sunxi_ccm_reg * const ccm =
  52                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  53
  54         setbits_le32(&ccm->ccu_sec_switch,
  55                      CCM_SEC_SWITCH_MBUS_NONSEC |
  56                      CCM_SEC_SWITCH_BUS_NONSEC |
  57                      CCM_SEC_SWITCH_PLL_NONSEC);
  58 #endif
  59 }
  60
  61 void clock_init_uart(void)
  62 {
  63 #if CONFIG_CONS_INDEX < 5
  64         struct sunxi_ccm_reg *const ccm =
  65                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  66
  67         /* uart clock source is apb2 */
  68         writel(APB2_CLK_SRC_OSC24M|
  69                APB2_CLK_RATE_N_1|
  70                APB2_CLK_RATE_M(1),
  71                &ccm->apb2_div);
  72
  73         /* open the clock for uart */
  74         setbits_le32(&ccm->apb2_gate,
  75                      CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
  76                                        CONFIG_CONS_INDEX - 1));
  77
  78         /* deassert uart reset */
  79         setbits_le32(&ccm->apb2_reset_cfg,
  80                      1 << (APB2_RESET_UART_SHIFT +
  81                            CONFIG_CONS_INDEX - 1));
  82 #else
  83         /* enable R_PIO and R_UART clocks, and de-assert resets */
  84         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
  85 #endif
  86 }
  87
  88 int clock_twi_onoff(int port, int state)
  89 {
  90         struct sunxi_ccm_reg *const ccm =
  91                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  92
  93         if (port == 5) {
  94                 if (state)
  95                         prcm_apb0_enable(
  96                                 PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
  97                 else
  98                         prcm_apb0_disable(
  99                                 PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
 100                 return 0;
 101         }
 102
 103         /* set the apb clock gate and reset for twi */
 104         if (state) {
 105                 setbits_le32(&ccm->apb2_gate,
 106                              CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
 107                 setbits_le32(&ccm->apb2_reset_cfg,
 108                              1 << (APB2_RESET_TWI_SHIFT + port));
 109         } else {
 110                 clrbits_le32(&ccm->apb2_reset_cfg,
 111                              1 << (APB2_RESET_TWI_SHIFT + port));
 112                 clrbits_le32(&ccm->apb2_gate,
 113                              CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
 114         }
 115
 116         return 0;
 117 }
 118
 119 #ifdef CONFIG_SPL_BUILD
 120 void clock_set_pll1(unsigned int clk)
 121 {
 122         struct sunxi_ccm_reg * const ccm =
 123                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 124         const int p = 0;
 125         int k = 1;
 126         int m = 1;
 127
 128         if (clk > 1152000000) {
 129                 k = 2;
 130         } else if (clk > 768000000) {
 131                 k = 3;
 132                 m = 2;
 133         }
 134
 135         /* Switch to 24MHz clock while changing PLL1 */
 136         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 137                ATB_DIV_2 << ATB_DIV_SHIFT |
 138                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 139                &ccm->cpu_axi_cfg);
 140
 141         /*
 142          * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m   (p is ignored)
 143          * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
 144          */
 145         writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
 146                CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
 147                CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
 148         sdelay(200);
 149
 150         /* Switch CPU to PLL1 */
 151         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 152                ATB_DIV_2 << ATB_DIV_SHIFT |
 153                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 154                &ccm->cpu_axi_cfg);
 155 }
 156 #endif
 157
 158 void clock_set_pll3(unsigned int clk)
 159 {
 160         struct sunxi_ccm_reg * const ccm =
 161                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 162         const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
 163
 164         if (clk == 0) {
 165                 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
 166                 return;
 167         }
 168
 169         /* PLL3 rate = 24000000 * n / m */
 170         writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
 171                CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
 172                &ccm->pll3_cfg);
 173 }
 174
 175 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 176 {
 177         struct sunxi_ccm_reg * const ccm =
 178                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 179         const int max_n = 32;
 180         int k = 1, m = 2;
 181
 182         if (sigma_delta_enable)
 183                 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
 184
 185         /* PLL5 rate = 24000000 * n * k / m */
 186         if (clk > 24000000 * k * max_n / m) {
 187                 m = 1;
 188                 if (clk > 24000000 * k * max_n / m)
 189                         k = 2;
 190         }
 191         writel(CCM_PLL5_CTRL_EN |
 192                (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
 193                CCM_PLL5_CTRL_UPD |
 194                CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
 195                CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
 196
 197         udelay(5500);
 198 }
 199
 200 #ifdef CONFIG_MACH_SUN6I
 201 void clock_set_mipi_pll(unsigned int clk)
 202 {
 203         struct sunxi_ccm_reg * const ccm =
 204                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 205         unsigned int k, m, n, value, diff;
 206         unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
 207         unsigned int src = clock_get_pll3();
 208
 209         /* All calculations are in KHz to avoid overflows */
 210         clk /= 1000;
 211         src /= 1000;
 212
 213         /* Pick the closest lower clock */
 214         for (k = 1; k <= 4; k++) {
 215                 for (m = 1; m <= 16; m++) {
 216                         for (n = 1; n <= 16; n++) {
 217                                 value = src * n * k / m;
 218                                 if (value > clk)
 219                                         continue;
 220
 221                                 diff = clk - value;
 222                                 if (diff < best_diff) {
 223                                         best_diff = diff;
 224                                         best_k = k;
 225                                         best_m = m;
 226                                         best_n = n;
 227                                 }
 228                                 if (diff == 0)
 229                                         goto done;
 230                         }
 231                 }
 232         }
 233
 234 done:
 235         writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
 236                CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
 237                CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
 238 }
 239 #endif
 240
 241 #ifdef CONFIG_MACH_SUN8I_A33
 242 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
 243 {
 244         struct sunxi_ccm_reg * const ccm =
 245                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 246
 247         if (sigma_delta_enable)
 248                 writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
 249
 250         writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
 251                (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
 252                CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
 253
 254         while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
 255                 ;
 256 }
 257 #endif
 258
 259 unsigned int clock_get_pll3(void)
 260 {
 261         struct sunxi_ccm_reg *const ccm =
 262                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 263         uint32_t rval = readl(&ccm->pll3_cfg);
 264         int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
 265         int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
 266
 267         /* Multiply by 1000 after dividing by m to avoid integer overflows */
 268         return (24000 * n / m) * 1000;
 269 }
 270
 271 unsigned int clock_get_pll6(void)
 272 {
 273         struct sunxi_ccm_reg *const ccm =
 274                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 275         uint32_t rval = readl(&ccm->pll6_cfg);
 276         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
 277         int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
 278         return 24000000 * n * k / 2;
 279 }
 280
 281 unsigned int clock_get_mipi_pll(void)
 282 {
 283         struct sunxi_ccm_reg *const ccm =
 284                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 285         uint32_t rval = readl(&ccm->mipi_pll_cfg);
 286         unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
 287         unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
 288         unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
 289         unsigned int src = clock_get_pll3();
 290
 291         /* Multiply by 1000 after dividing by m to avoid integer overflows */
 292         return ((src / 1000) * n * k / m) * 1000;
 293 }
 294
 295 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
 296 {
 297         int pll = clock_get_pll6() * 2;
 298         int div = 1;
 299
 300         while ((pll / div) > hz)
 301                 div++;
 302
 303         writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
 304                clk_cfg);
 305 }