2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * Some init for sunxi platform.
10 * SPDX-License-Identifier: GPL-2.0+
17 #ifdef CONFIG_SPL_BUILD
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/timer.h>
27 #ifdef CONFIG_SPL_BUILD
28 /* Pointer to the global data structure for SPL */
29 DECLARE_GLOBAL_DATA_PTR;
31 /* The sunxi internal brom will try to loader external bootloader
32 * from mmc0, nand flash, mmc2.
33 * Unfortunately we can't check how SPL was loaded so assume
34 * it's always the first SD/MMC controller
36 u32 spl_boot_device(void)
38 return BOOT_DEVICE_MMC1;
41 /* No confirmation data available in SPL yet. Hardcode bootmode */
42 u32 spl_boot_mode(void)
44 return MMCSD_MODE_RAW;
50 #if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
51 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
52 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
53 sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
54 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
55 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
56 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
57 sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
58 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
59 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
60 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
61 sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
63 #error Unsupported console port number. Please fix pin mux settings in board.c
69 void reset_cpu(ulong addr)
71 static const struct sunxi_wdog *wdog =
72 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
74 /* Set the watchdog for its shortest interval (.5s) and wait */
75 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
76 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
80 /* do some early init */
83 #if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
84 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
86 "mrc p15, 0, r0, c1, c0, 1\n"
87 "orr r0, r0, #1 << 6\n"
88 "mcr p15, 0, r0, c1, c0, 1\n");
95 #ifdef CONFIG_SPL_BUILD
97 preloader_console_init();
103 #ifndef CONFIG_SYS_DCACHE_OFF
104 void enable_caches(void)
106 /* Enable D-cache. I-cache is already enabled in start.S */
111 #ifdef CONFIG_CMD_NET
113 * Initializes on-chip ethernet controllers.
114 * to override, implement board_eth_init()
116 int cpu_eth_init(bd_t *bis)
120 #ifdef CONFIG_SUNXI_EMAC
121 rc = sunxi_emac_initialize(bis);
123 printf("sunxi: failed to initialize emac\n");
128 #ifdef CONFIG_SUNXI_GMAC
129 rc = sunxi_gmac_initialize(bis);
131 printf("sunxi: failed to initialize gmac\n");