arch/arm/cpu/armv7/sc8830/misc.c

   1 #include <common.h>
   2 #include <asm/io.h>
   3 #include <asm/arch/sprd_reg.h>
   4 #include <asm/arch/sci_types.h>
   5 #include <asm/arch/adi_hal_internal.h>
   6
   7 extern void __raw_bits_or(unsigned int v, unsigned int a);
   8
   9 /*
  10         REG_AON_APB_BOND_OPT0  ==> romcode set
  11         REG_AON_APB_BOND_OPT1  ==> set it later
  12
  13         !!! notice: these two registers can be set only one time!!!
  14
  15         B1[0] : B0[0]
  16         0     : 0     Jtag enable
  17         0     : 1     Jtag disable
  18         1     : 0     Jtag enable
  19         1     : 1     Jtag enable
  20 */
  21
  22 /*************************************************
  23 * 1 : enable jtag success                        *
  24 * 0 : enable jtag fail                           *
  25 *************************************************/
  26 int sprd_jtag_enable(void)
  27 {
  28         if (*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1)
  29         {
  30                 *((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) = 1;
  31                 if (!((*(volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) & 1))
  32                         return 0;
  33         }
  34         return 1;
  35 }
  36
  37 /*************************************************
  38 * 1 : disable jtag success                       *
  39 * 0 : disable jtag fail                          *
  40 *************************************************/
  41 int sprd_jtag_disable(void)
  42 {
  43         if (!(*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1))
  44         {
  45                 return 0;
  46         }
  47         else
  48         {
  49                 *((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) = 0;
  50                 if (*((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) & 1)
  51                         return 0;
  52                 else
  53                         return 1;
  54         }
  55 }
  56
  57 static void ap_slp_cp_dbg_cfg(void)
  58 {
  59         *((volatile unsigned int *)(REG_AP_AHB_MCU_PAUSE)) |= BIT_MCU_SLEEP_FOLLOW_CA7_EN; //when ap sleep, cp can continue debug
  60 }
  61
  62 static void ap_cpll_rel_cfg(void)
  63 {
  64         *((volatile unsigned int *)(REG_PMU_APB_CPLL_REL_CFG)) |= BIT_CPLL_AP_SEL;
  65 }
  66
  67 #if 0
  68 static void ap_close_wpll_en(void)
  69 {
  70        *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WPLL_AP_EN;
  71 }
  72
  73 static void ap_close_cpll_en(void)
  74 {
  75        *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_CPLL_AP_EN;
  76 }
  77
  78 static void ap_close_wifipll_en(void)
  79 {
  80        *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WIFIPLL1_AP_EN;
  81 }
  82 #endif
  83
  84 #ifndef  CONFIG_SPX30G
  85 static void bb_bg_auto_en(void)
  86 {
  87         *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<8;
  88 }
  89
  90 static void bb_ldo_auto_en(void)
  91 {
  92         *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<9;
  93 }
  94 #endif
  95
  96 #ifdef CONFIG_PBINT_7S_RESET_V1
  97
  98 #define PBINT_7S_HW_FLAG (BIT(7))
  99 #define PBINT_7S_SW_FLAG (BIT(12))
 100
 101 #define CONFIG_7S_RESET_SW_FLAG
 102 #ifdef CONFIG_7S_RESET_SW_FLAG
 103 static u32 pbint_7s_flag = 0;
 104 #endif
 105 int is_7s_reset(void)
 106 {
 107 #ifdef CONFIG_7S_RESET_SW_FLAG
 108         return pbint_7s_flag & PBINT_7S_SW_FLAG;
 109 #else
 110         return sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & PBINT_7S_SW_FLAG;
 111 #endif
 112 }
 113
 114 int is_7s_reset_for_systemdump(void)
 115 {
 116         int val;
 117         /* FIXME flag? */
 118         int mask = PBINT_7S_SW_FLAG | PBINT_7S_HW_FLAG;
 119         /* some chip just care software flag */
 120         int chip_id = ANA_GET_CHIP_ID();
 121         if (((chip_id >> 16) & 0xFFFF) == 0x2711) {
 122                 if ((chip_id & 0xFFFF) <= 0xA100) {
 123                         mask = PBINT_7S_SW_FLAG;
 124                 }
 125         }
 126 #ifdef CONFIG_7S_RESET_SW_FLAG
 127         val = pbint_7s_flag & mask;
 128 #else
 129         val = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & mask;
 130 #endif
 131         return (val == PBINT_7S_SW_FLAG);
 132 }
 133
 134 static inline int pbint_7s_rst_disable(uint32 disable)
 135 {
 136         if (disable) {
 137                 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_DISABLE);
 138         } else {
 139                 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_DISABLE);
 140         }
 141         return 0;
 142 }
 143 static inline int pbint_7s_rst_set_2keymode(uint32 mode)
 144 {
 145 #if defined CONFIG_ADIE_SC2723S || defined CONFIG_ADIE_SC2723
 146         if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xA000) {
 147                 if (!mode) {
 148                         sci_adi_clr(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 149                 } else {
 150                         sci_adi_set(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 151                 }
 152         } else {
 153                 if (!mode) {
 154                         sci_adi_set(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 155                 } else {
 156                         sci_adi_clr(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 157                 }
 158         }
 159 #else
 160 #error "please check pbint_7s_rst_set_2keymode reg"
 161 #endif
 162         return 0;
 163 }
 164 static inline int pbint_7s_rst_set_sw(uint32 mode)
 165 {
 166         if (mode) {
 167                 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_MODE);
 168         } else {
 169                 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_MODE);
 170         }
 171         return 0;
 172 }
 173
 174 static inline int pbint_7s_rst_set_swmode(uint32 mode)
 175 {
 176         if (mode) {
 177                 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_SWMODE);
 178         } else {
 179                 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_SWMODE);
 180         }
 181         return 0;
 182 }
 183
 184 static inline int pbint_7s_rst_set_threshold(uint32 th)
 185 {
 186         int mask = BITS_PBINT_7S_RST_THRESHOLD(-1);
 187         int shift = ffs(mask) - 1;
 188
 189         if (th>0) th--;
 190         sci_adi_write(ANA_REG_GLB_POR_7S_CTRL, (th << shift) & mask, mask);
 191         return 0;
 192 }
 193
 194 int pbint_7s_rst_cfg(uint32 en, uint32 sw_rst, uint32 short_rst)
 195 {
 196 #ifdef CONFIG_7S_RESET_SW_FLAG
 197         pbint_7s_flag = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG);
 198         sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 199         udelay(10);
 200         sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 201 #endif
 202         /* ignore sw_rst, please refer to config.h */
 203         if (en) {
 204                 pbint_7s_rst_set_threshold(CONFIG_7S_RST_THRESHOLD);
 205                 pbint_7s_rst_set_sw(!sw_rst);
 206
 207                 pbint_7s_rst_set_swmode(short_rst);
 208
 209                 pbint_7s_rst_set_2keymode(CONFIG_7S_RST_2KEY_MODE);
 210         }
 211         return pbint_7s_rst_disable(!en);
 212 }
 213 #elif defined CONFIG_PBINT_7S_RESET_V0
 214
 215 #define PBINT_7S_HW_FLAG (BIT(7))
 216 #define PBINT_7S_SW_FLAG (BIT(12))
 217
 218 #define CONFIG_7S_RESET_SW_FLAG
 219 #ifdef CONFIG_7S_RESET_SW_FLAG
 220 static u32 pbint_7s_flag = 0;
 221 #endif
 222 int is_7s_reset(void)
 223 {
 224 #ifdef CONFIG_7S_RESET_SW_FLAG
 225         return pbint_7s_flag & PBINT_7S_SW_FLAG;
 226 #else
 227         return sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & PBINT_7S_SW_FLAG;
 228 #endif
 229 }
 230
 231 int is_7s_reset_for_systemdump(void)
 232 {
 233         int val;
 234         int mask = PBINT_7S_SW_FLAG;
 235 #ifdef CONFIG_7S_RESET_SW_FLAG
 236         val = pbint_7s_flag & mask;
 237 #else
 238         val = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & mask;
 239 #endif
 240         return (val == mask);
 241 }
 242
 243 void pbint_7s_rst_cfg(uint32 en_rst, uint32 sw_rst, uint32 short_rst)
 244 {
 245         uint16 reg_data = ANA_REG_GET(ANA_REG_GLB_POR_7S_CTRL);
 246
 247 #ifdef CONFIG_7S_RESET_SW_FLAG
 248         pbint_7s_flag = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG);
 249         sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 250         udelay(10);
 251         sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 252 #endif
 253
 254         if (!en_rst)
 255         {
 256                 reg_data |=  BIT_PBINT_7S_RST_DISABLE;
 257         }
 258         else
 259         {
 260                 reg_data &= ~BIT_PBINT_7S_RST_DISABLE;
 261                 /* software reset */
 262                 if (!sw_rst)
 263                 {
 264                         reg_data |=  BIT_PBINT_7S_RST_MODE_RTCSET;
 265                         reg_data &= ~BIT_PBINT_7S_RST_MODE_RTCCLR;
 266                 }
 267                 else
 268                 {
 269                         reg_data &= ~BIT_PBINT_7S_RST_MODE_RTCSET;
 270                         reg_data |=  BIT_PBINT_7S_RST_MODE_RTCCLR;
 271                 }
 272                 /* 7s short reset */
 273                 if (short_rst)
 274                 {
 275                         reg_data |=  BIT_PBINT_7S_RST_SWMODE_RTCSET;
 276                         reg_data &= ~BIT_PBINT_7S_RST_SWMODE_RTCCLR;
 277                 }
 278                 else
 279                 {
 280                         reg_data &= ~BIT_PBINT_7S_RST_SWMODE_RTCSET;
 281                         reg_data |=  BIT_PBINT_7S_RST_SWMODE_RTCCLR;
 282                 }
 283         }
 284         ANA_REG_SET(ANA_REG_GLB_POR_7S_CTRL, reg_data);
 285         printf("ANA_REG_GLB_POR_7S_CTRL:%04X\r\n", ANA_REG_GET(ANA_REG_GLB_POR_7S_CTRL));
 286 }
 287 #endif
 288
 289 #if defined (CONFIG_OF_LIBFDT) && !defined (CONFIG_SPX30G)
 290 void scx35_pmu_reconfig(void)
 291 {
 292         /* FIXME:
 293          * turn on gpu/mm domain for clock device initcall, and then turn off asap.
 294          */
 295         __raw_writel(__raw_readl(REG_PMU_APB_PD_MM_TOP_CFG)
 296                      & ~(BIT_PD_MM_TOP_FORCE_SHUTDOWN),
 297                      REG_PMU_APB_PD_MM_TOP_CFG);
 298
 299         __raw_writel(__raw_readl(REG_PMU_APB_PD_GPU_TOP_CFG)
 300                      & ~(BIT_PD_GPU_TOP_FORCE_SHUTDOWN),
 301                      REG_PMU_APB_PD_GPU_TOP_CFG);
 302
 303         __raw_writel(__raw_readl(REG_AON_APB_APB_EB0) | BIT_MM_EB |
 304                      BIT_GPU_EB, REG_AON_APB_APB_EB0);
 305
 306         __raw_writel(__raw_readl(REG_MM_AHB_AHB_EB) | BIT_MM_CKG_EB,
 307                      REG_MM_AHB_AHB_EB);
 308
 309         __raw_writel(__raw_readl(REG_MM_AHB_GEN_CKG_CFG)
 310                      | BIT_MM_MTX_AXI_CKG_EN | BIT_MM_AXI_CKG_EN,
 311                      REG_MM_AHB_GEN_CKG_CFG);
 312
 313         __raw_writel(__raw_readl(REG_MM_CLK_MM_AHB_CFG) | 0x3,
 314                      REG_MM_CLK_MM_AHB_CFG);
 315
 316 }
 317
 318 #else
 319 void scx35_pmu_reconfig(void) {}
 320 #endif
 321 inline int is_hw_smpl_enable(void)
 322 {
 323 #if defined CONFIG_ADIE_SC2723S || defined CONFIG_ADIE_SC2723
 324         return !!(sci_adi_read(ANA_REG_GLB_SMPL_CTRL1) & BIT_SMPL_EN);
 325 #endif
 326         return 0;
 327 }
 328
 329 #if !defined CONFIG_SPX15 && !defined CONFIG_SPX30G
 330 int is_smpl_bootup(void)
 331 {
 332         if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xCA00) {
 333                 return sci_adi_read(ANA_REG_GLB_CA_CTRL2) & BIT_IS_SMPL_ON;
 334         }
 335         else {
 336                 return 0;
 337         }
 338 }
 339 #define SMPL_MODE_ENABLE_SET    (0x1935)
 340 static int smpl_config(void)
 341 {
 342         u32 val;
 343         if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xCA00) {
 344                 val = BITS_SMPL_ENABLE(SMPL_MODE_ENABLE_SET);
 345                 return sci_adi_write_fast(ANA_REG_GLB_CA_CTRL1, val, 1);
 346         }
 347 }
 348 #else
 349 #ifdef CONFIG_SMPL_MODE
 350 #if defined(CONFIG_TSHARK2TABE) || defined(CONFIG_GRANDPRIME3G_VE)|| defined(CONFIG_COREPRIME3G_VE) || defined(CONFIG_TSHARK2J2_3G) || defined(CONFIG_TIZENZ3_3G) || defined(CONFIG_GRANDPRIME_DTV)
 351 //#define CONFIG_SMPL_SW_FLAG
 352 #else
 353 #define CONFIG_SMPL_SW_FLAG
 354 #endif
 355 #ifdef CONFIG_SMPL_SW_FLAG
 356 static u32 smpl_flag = 0;
 357 #endif
 358 int is_smpl_bootup(void)
 359 {
 360 #ifdef CONFIG_SMPL_SW_FLAG
 361         return smpl_flag & BIT_IS_SMPL_ON_SW_FLAG;
 362 #else
 363 #ifdef CONFIG_PBINT_7S_RST_HW_SHORT
 364         return sci_adi_read(ANA_REG_GLB_SMPL_CTRL1) & BIT_SMPL_PWR_ON_SET;
 365 #else
 366         return sci_adi_read(ANA_REG_GLB_SMPL_CTRL1) & BIT_SMPL_PWR_ON_FLAG;
 367 #endif
 368 #endif
 369 }
 370
 371 #define SMPL_MODE_ENABLE_SET    (0x1935)
 372 static int smpl_config(void)
 373 {
 374         u32 val = BITS_SMPL_ENABLE(SMPL_MODE_ENABLE_SET);
 375 #ifdef CONFIG_SMPL_THRESHOLD
 376         val |= BITS_SMPL_THRESHOLD(CONFIG_SMPL_THRESHOLD);
 377 #endif
 378 #ifdef CONFIG_SMPL_SW_FLAG
 379         smpl_flag = sci_adi_read(ANA_REG_GLB_BA_CTRL1);
 380         sci_adi_set(ANA_REG_GLB_BA_CTRL1, BIT_IS_SMPL_ON_SW_CLR);
 381 #endif
 382 #if defined(CONFIG_TSHARK2TABE) || defined(CONFIG_GRANDPRIME3G_VE) || defined(CONFIG_COREPRIME3G_VE) || defined(CONFIG_TSHARK2J2_3G) || defined(CONFIG_TIZENZ3_3G) || defined(CONFIG_GRANDPRIME_DTV)
 383         return sci_adi_write_fast(ANA_REG_GLB_SMPL_CTRL0, val, 1);
 384 #else
 385         return sci_adi_write_fast(ANA_REG_GLB_BA_CTRL0, val, 1);
 386 #endif
 387 }
 388 #else
 389 __attribute__ ((gnu_inline))inline int is_smpl_bootup(void)
 390 {
 391         return 0;
 392 }
 393
 394 inline static int smpl_config(void)
 395 {
 396         return 0;
 397 }
 398 #endif
 399 #endif
 400 static void vbat_crash_vol_set(void)
 401 {
 402 #if !defined CONFIG_SPX15 && !defined CONFIG_SPX30G
 403         u32 val;
 404         if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xCA00) {
 405                 val = sci_adi_read(ANA_REG_GLB_CA_CTRL3);
 406                 val &= ~(3 << 14);
 407                 val |= (1 << 14);
 408                 sci_adi_write(ANA_REG_GLB_CA_CTRL3, val, 0xffff);
 409         }
 410 #endif
 411 }
 412
 413 void pmic_init(void)
 414 {
 415 #ifndef CONFIG_TIZEN
 416         u32 val;
 417 #endif
 418         pbint_7s_rst_cfg(CONFIG_7S_RST_MODULE_EN,
 419                                 CONFIG_7S_RST_SW_MODE,
 420                                 CONFIG_7S_RST_SHORT_MODE);
 421 #ifndef CONFIG_TIZEN
 422         smpl_config();
 423 #if defined CONFIG_ADIE_SC2723S || defined CONFIG_ADIE_SC2723
 424         sci_adi_set(ANA_REG_GLB_LDO_SHPT_PD2, BIT_LDO_VIBR_SHPT_PD);    //close vibr short protection
 425 #else
 426         val = BITS_SMPL_ENABLE(SMPL_MODE_DISABLE_SET);
 427         ci_adi_write_fast(ANA_REG_GLB_SMPL_CTRL0, val, 1);
 428 #endif  /* CONFIG_TIZEN */
 429
 430 #endif
 431 }
 432
 433 #ifdef CONFIG_TIZEN
 434 #define REBOOT_MODE_MASK        (0xFFFFFFF0)
 435 #define REBOOT_MODE_PREFIX      (0x12345670)
 436 #define REBOOT_THOR_DOWNLOAD            (0x1)
 437 #define REBOOT_RECOVERY                 (0x4)
 438 int tizen_reboot_check(void)
 439 {
 440         int inform3 = readl(INFORM3);
 441
 442         if ((inform3 & REBOOT_MODE_MASK) == REBOOT_MODE_PREFIX) {
 443                 if ((inform3 & 0xf) == REBOOT_THOR_DOWNLOAD) {
 444                         writel(0, INFORM3);
 445                         return 1;
 446                 }
 447         }
 448
 449         return 0;
 450 }
 451
 452 int tizen_reboot_recovery_check(void)
 453 {
 454         int inform3 = readl(INFORM3);
 455
 456         if ((inform3 & REBOOT_MODE_MASK) == REBOOT_MODE_PREFIX) {
 457                 if ((inform3 & 0xf) == REBOOT_RECOVERY) {
 458                         writel(0, INFORM3);
 459                         return 1;
 460                 }
 461         }
 462
 463         return 0;
 464 }
 465 #endif
 466
 467 #define REG32(x)                                    (*((volatile uint32 *)(x)))
 468 void gpu_clk_auto_gate_disable(void)
 469 {
 470         REG32(REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN) &= ~(0x7F);
 471 }
 472
 473 void misc_init(void)
 474 {
 475         scx35_pmu_reconfig();
 476         ap_slp_cp_dbg_cfg();
 477         ap_cpll_rel_cfg();
 478 #ifndef  CONFIG_SPX15
 479 //      ap_close_wpll_en();
 480 //      ap_close_cpll_en();
 481 //      ap_close_wifipll_en();
 482 #endif
 483 #ifndef  CONFIG_SPX30G
 484         bb_bg_auto_en();
 485         bb_ldo_auto_en();
 486 #endif
 487         /*
 488          * To avoid GPU lockup issue (Bug 413283, 428056),
 489          *  disable GPU clk auto gating on SC7730 board
 490          */
 491         gpu_clk_auto_gate_disable();
 492
 493         pmic_init();
 494
 495         vbat_crash_vol_set();
 496
 497 #ifdef CONFIG_SPX30G
 498 /*csi0_phy_powerdow & csi1_phy_powerdow*/
 499         __raw_bits_or((BIT_CSI1_PHY_PD | BIT_CSI0_PHY_PD), REG_AON_APB_PWR_CTRL);
 500 /*dsi_phy_powerdow*/
 501         __raw_bits_or(BIT_DSI_PHY_PD, REG_AON_APB_PWR_CTRL);
 502 #endif
 503         /* Fix /dev/stty_w open issues */
 504         ANA_REG_SET(ANA_REG_GLB_WDG_RST_MONITOR, 0);
 505 }
 506
 507 typedef struct mem_cs_info
 508 {
 509         uint32 cs_number;
 510         uint32 cs0_size;//bytes
 511         uint32 cs1_size;//bytes
 512 }mem_cs_info_t;
 513 PUBLIC int get_dram_cs_number(void)
 514 {
 515         mem_cs_info_t *cs_info_ptr = (mem_cs_info_t *)0x1C00;
 516         return cs_info_ptr->cs_number;
 517 }
 518 PUBLIC int get_dram_cs0_size(void)
 519 {
 520         mem_cs_info_t *cs_info_ptr = (mem_cs_info_t *)0x1C00;
 521         return cs_info_ptr->cs0_size;
 522 }