3 #include <asm/arch/sprd_reg.h>
4 #include <asm/arch/sci_types.h>
5 #include <asm/arch/adi_hal_internal.h>
7 REG_AON_APB_BOND_OPT0 ==> romcode set
8 REG_AON_APB_BOND_OPT1 ==> set it later
10 !!! notice: these two registers can be set only one time!!!
19 /*************************************************
20 * 1 : enable jtag success *
21 * 0 : enable jtag fail *
22 *************************************************/
23 int sprd_jtag_enable()
25 if (*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1)
27 *((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) = 1;
28 if (!((*(volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) & 1))
34 /*************************************************
35 * 1 : disable jtag success *
36 * 0 : disable jtag fail *
37 *************************************************/
38 int sprd_jtag_disable()
40 if (!(*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1))
46 *((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) = 0;
47 if (*((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) & 1)
54 static void ap_slp_cp_dbg_cfg()
56 *((volatile unsigned int *)(REG_AP_AHB_MCU_PAUSE)) |= BIT_MCU_SLEEP_FOLLOW_CA7_EN; //when ap sleep, cp can continue debug
59 static void ap_cpll_rel_cfg()
61 *((volatile unsigned int *)(REG_PMU_APB_CPLL_REL_CFG)) |= BIT_CPLL_AP_SEL;
64 static void bb_bg_auto_en()
66 *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<8;
70 static void ap_close_wpll_en()
72 *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WPLL_AP_EN;
75 static void ap_close_cpll_en()
77 *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_CPLL_AP_EN;
80 static void ap_close_wifipll_en()
82 *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WIFIPLL1_AP_EN;
86 static void bb_ldo_auto_en()
88 *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<9;
91 #ifdef CONFIG_PBINT_7S_RESET_V1
93 #define PBINT_7S_HW_FLAG (BIT(7))
94 #define PBINT_7S_SW_FLAG (BIT(12))
96 #define CONFIG_7S_RESET_SW_FLAG
97 #ifdef CONFIG_7S_RESET_SW_FLAG
98 static u32 pbint_7s_flag = 0;
100 int is_7s_reset(void)
102 #ifdef CONFIG_7S_RESET_SW_FLAG
103 return pbint_7s_flag & PBINT_7S_SW_FLAG;
105 return sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & PBINT_7S_SW_FLAG;
109 int is_7s_reset_for_systemdump(void)
113 int mask = PBINT_7S_SW_FLAG | PBINT_7S_HW_FLAG;
114 /* some chip just care software flag */
115 int chip_id = ANA_GET_CHIP_ID();
116 if (((chip_id >> 16) & 0xFFFF) == 0x2711) {
117 if ((chip_id & 0xFFFF) <= 0xA100) {
118 mask = PBINT_7S_SW_FLAG;
121 #ifdef CONFIG_7S_RESET_SW_FLAG
122 val = pbint_7s_flag & mask;
124 val = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & mask;
126 return (val == PBINT_7S_SW_FLAG);
129 static inline int pbint_7s_rst_disable(uint32 disable)
132 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_DISABLE);
134 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_DISABLE);
138 static inline int pbint_7s_rst_set_2keymode(uint32 mode)
140 #if defined CONFIG_ADIE_SC2723S || defined CONFIG_ADIE_SC2723
141 if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xA000) {
143 sci_adi_clr(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
145 sci_adi_set(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
149 sci_adi_set(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
151 sci_adi_clr(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
155 #error "please check pbint_7s_rst_set_2keymode reg"
159 static inline int pbint_7s_rst_set_sw(uint32 mode)
162 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_MODE);
164 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_MODE);
169 static inline int pbint_7s_rst_set_swmode(uint32 mode)
172 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_SWMODE);
174 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_SWMODE);
179 static inline int pbint_7s_rst_set_threshold(uint32 th)
181 int mask = BITS_PBINT_7S_RST_THRESHOLD(-1);
182 int shift = ffs(mask) - 1;
185 sci_adi_write(ANA_REG_GLB_POR_7S_CTRL, (th << shift) & mask, mask);
189 int pbint_7s_rst_cfg(uint32 en, uint32 sw_rst, uint32 short_rst)
191 #ifdef CONFIG_7S_RESET_SW_FLAG
192 pbint_7s_flag = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG);
193 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
195 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
197 /* ignore sw_rst, please refer to config.h */
199 pbint_7s_rst_set_threshold(CONFIG_7S_RST_THRESHOLD);
200 pbint_7s_rst_set_sw(!sw_rst);
202 pbint_7s_rst_set_swmode(short_rst);
204 pbint_7s_rst_set_2keymode(CONFIG_7S_RST_2KEY_MODE);
206 return pbint_7s_rst_disable(!en);
208 #elif defined CONFIG_PBINT_7S_RESET_V0
210 #define PBINT_7S_HW_FLAG (BIT(7))
211 #define PBINT_7S_SW_FLAG (BIT(12))
213 #define CONFIG_7S_RESET_SW_FLAG
214 #ifdef CONFIG_7S_RESET_SW_FLAG
215 static u32 pbint_7s_flag = 0;
217 int is_7s_reset(void)
219 #ifdef CONFIG_7S_RESET_SW_FLAG
220 return pbint_7s_flag & PBINT_7S_SW_FLAG;
222 return sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & PBINT_7S_SW_FLAG;
226 int is_7s_reset_for_systemdump(void)
229 int mask = PBINT_7S_SW_FLAG;
230 #ifdef CONFIG_7S_RESET_SW_FLAG
231 val = pbint_7s_flag & mask;
233 val = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & mask;
235 return (val == mask);
238 void pbint_7s_rst_cfg(uint32 en_rst, uint32 sw_rst, uint32 short_rst)
240 uint16 reg_data = ANA_REG_GET(ANA_REG_GLB_POR_7S_CTRL);
242 #ifdef CONFIG_7S_RESET_SW_FLAG
243 pbint_7s_flag = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG);
244 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
246 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
251 reg_data |= BIT_PBINT_7S_RST_DISABLE;
255 reg_data &= ~BIT_PBINT_7S_RST_DISABLE;
259 reg_data |= BIT_PBINT_7S_RST_MODE_RTCSET;
260 reg_data &= ~BIT_PBINT_7S_RST_MODE_RTCCLR;
264 reg_data &= ~BIT_PBINT_7S_RST_MODE_RTCSET;
265 reg_data |= BIT_PBINT_7S_RST_MODE_RTCCLR;
270 reg_data |= BIT_PBINT_7S_RST_SWMODE_RTCSET;
271 reg_data &= ~BIT_PBINT_7S_RST_SWMODE_RTCCLR;
275 reg_data &= ~BIT_PBINT_7S_RST_SWMODE_RTCSET;
276 reg_data |= BIT_PBINT_7S_RST_SWMODE_RTCCLR;
279 ANA_REG_SET(ANA_REG_GLB_POR_7S_CTRL, reg_data);
280 printf("ANA_REG_GLB_POR_7S_CTRL:%04X\r\n", ANA_REG_GET(ANA_REG_GLB_POR_7S_CTRL));
284 #if defined (CONFIG_OF_LIBFDT) && !defined (CONFIG_SPX30G)
285 void scx35_pmu_reconfig(void)
288 * turn on gpu/mm domain for clock device initcall, and then turn off asap.
290 __raw_writel(__raw_readl(REG_PMU_APB_PD_MM_TOP_CFG)
291 & ~(BIT_PD_MM_TOP_FORCE_SHUTDOWN),
292 REG_PMU_APB_PD_MM_TOP_CFG);
294 __raw_writel(__raw_readl(REG_PMU_APB_PD_GPU_TOP_CFG)
295 & ~(BIT_PD_GPU_TOP_FORCE_SHUTDOWN),
296 REG_PMU_APB_PD_GPU_TOP_CFG);
298 __raw_writel(__raw_readl(REG_AON_APB_APB_EB0) | BIT_MM_EB |
299 BIT_GPU_EB, REG_AON_APB_APB_EB0);
301 __raw_writel(__raw_readl(REG_MM_AHB_AHB_EB) | BIT_MM_CKG_EB,
304 __raw_writel(__raw_readl(REG_MM_AHB_GEN_CKG_CFG)
305 | BIT_MM_MTX_AXI_CKG_EN | BIT_MM_AXI_CKG_EN,
306 REG_MM_AHB_GEN_CKG_CFG);
308 __raw_writel(__raw_readl(REG_MM_CLK_MM_AHB_CFG) | 0x3,
309 REG_MM_CLK_MM_AHB_CFG);
314 void scx35_pmu_reconfig(void) {}
316 inline int is_hw_smpl_enable(void)
318 #if defined CONFIG_ADIE_SC2723S || defined CONFIG_ADIE_SC2723
319 return !!(sci_adi_read(ANA_REG_GLB_SMPL_CTRL1) & BIT_SMPL_EN);
324 #if !defined CONFIG_SPX15 && !defined CONFIG_SPX30G
325 int is_smpl_bootup(void)
327 if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xCA00) {
328 return sci_adi_read(ANA_REG_GLB_CA_CTRL2) & BIT_IS_SMPL_ON;
334 #define SMPL_MODE_ENABLE_SET (0x1935)
335 static int smpl_config(void)
338 if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xCA00) {
339 val = BITS_SMPL_ENABLE(SMPL_MODE_ENABLE_SET);
340 return sci_adi_write_fast(ANA_REG_GLB_CA_CTRL1, val, 1);
344 #ifdef CONFIG_SMPL_MODE
345 #if defined(CONFIG_TSHARK2TABE) || defined(CONFIG_GRANDPRIME3G_VE)|| defined(CONFIG_COREPRIME3G_VE) || defined(CONFIG_TSHARK2J2_3G) || defined(CONFIG_TIZENZ3_3G) || defined(CONFIG_GRANDPRIME_DTV)
346 //#define CONFIG_SMPL_SW_FLAG
348 #define CONFIG_SMPL_SW_FLAG
350 #ifdef CONFIG_SMPL_SW_FLAG
351 static u32 smpl_flag = 0;
353 int is_smpl_bootup(void)
355 #ifdef CONFIG_SMPL_SW_FLAG
356 return smpl_flag & BIT_IS_SMPL_ON_SW_FLAG;
358 #ifdef CONFIG_PBINT_7S_RST_HW_SHORT
359 return sci_adi_read(ANA_REG_GLB_SMPL_CTRL1) & BIT_SMPL_PWR_ON_SET;
361 return sci_adi_read(ANA_REG_GLB_SMPL_CTRL1) & BIT_SMPL_PWR_ON_FLAG;
366 #define SMPL_MODE_ENABLE_SET (0x1935)
367 static int smpl_config(void)
369 u32 val = BITS_SMPL_ENABLE(SMPL_MODE_ENABLE_SET);
370 #ifdef CONFIG_SMPL_THRESHOLD
371 val |= BITS_SMPL_THRESHOLD(CONFIG_SMPL_THRESHOLD);
373 #ifdef CONFIG_SMPL_SW_FLAG
374 smpl_flag = sci_adi_read(ANA_REG_GLB_BA_CTRL1);
375 sci_adi_set(ANA_REG_GLB_BA_CTRL1, BIT_IS_SMPL_ON_SW_CLR);
377 #if defined(CONFIG_TSHARK2TABE) || defined(CONFIG_GRANDPRIME3G_VE) || defined(CONFIG_COREPRIME3G_VE) || defined(CONFIG_TSHARK2J2_3G) || defined(CONFIG_TIZENZ3_3G) || defined(CONFIG_GRANDPRIME_DTV)
378 return sci_adi_write_fast(ANA_REG_GLB_SMPL_CTRL0, val, 1);
380 return sci_adi_write_fast(ANA_REG_GLB_BA_CTRL0, val, 1);
384 inline int is_smpl_bootup(void)
389 inline static int smpl_config(void)
395 static void vbat_crash_vol_set(void)
397 #if !defined CONFIG_SPX15 && !defined CONFIG_SPX30G
399 if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xCA00) {
400 val = sci_adi_read(ANA_REG_GLB_CA_CTRL3);
403 sci_adi_write(ANA_REG_GLB_CA_CTRL3, val, 0xffff);
411 pbint_7s_rst_cfg(CONFIG_7S_RST_MODULE_EN,
412 CONFIG_7S_RST_SW_MODE,
413 CONFIG_7S_RST_SHORT_MODE);
416 #if defined CONFIG_ADIE_SC2723S || defined CONFIG_ADIE_SC2723
417 sci_adi_set(ANA_REG_GLB_LDO_SHPT_PD2, BIT_LDO_VIBR_SHPT_PD); //close vibr short protection
419 val = BITS_SMPL_ENABLE(SMPL_MODE_DISABLE_SET);
420 ci_adi_write_fast(ANA_REG_GLB_SMPL_CTRL0, val, 1);
421 #endif /* CONFIG_TIZEN */
426 #define REG32(x) (*((volatile uint32 *)(x)))
427 void gpu_clk_auto_gate_disable()
429 REG32(REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN) &= ~(0x7F);
434 scx35_pmu_reconfig();
438 // ap_close_wpll_en();
439 // ap_close_cpll_en();
440 // ap_close_wifipll_en();
442 #ifndef CONFIG_SPX30G
447 * To avoid GPU lockup issue (Bug 413283, 428056),
448 * disable GPU clk auto gating on SC7730 board
450 gpu_clk_auto_gate_disable();
454 vbat_crash_vol_set();
457 /*csi0_phy_powerdow & csi1_phy_powerdow*/
458 __raw_bits_or((BIT_CSI1_PHY_PD | BIT_CSI0_PHY_PD), REG_AON_APB_PWR_CTRL);
460 __raw_bits_or(BIT_DSI_PHY_PD, REG_AON_APB_PWR_CTRL);
462 /* Fix /dev/stty_w open issues */
463 ANA_REG_SET(ANA_REG_GLB_WDG_RST_MONITOR, 0);
466 typedef struct mem_cs_info
469 uint32 cs0_size;//bytes
470 uint32 cs1_size;//bytes
472 PUBLIC int get_dram_cs_number(void)
474 mem_cs_info_t *cs_info_ptr = 0x1C00;
475 return cs_info_ptr->cs_number;
477 PUBLIC int get_dram_cs0_size(void)
479 mem_cs_info_t *cs_info_ptr = 0x1C00;
480 return cs_info_ptr->cs0_size;