1 /******************************************************************************
2 ** File Name: chip_phy_v3.c *
3 ** Author: Richard Yang *
5 ** Copyright: 2002 Spreatrum, Incoporated. All Rights Reserved. *
6 ** Description: This file defines the basic information on chip. *
7 ******************************************************************************
9 ******************************************************************************
11 ** ------------------------------------------------------------------------- *
12 ** DATE NAME DESCRIPTION *
13 ** 08/14/2002 Richard.Yang Create. *
14 ** 09/16/2003 Xueliang.Wang Modify CR4013 *
15 ** 08/23/2004 JImmy.Jia Modify for SC6600D *
16 ******************************************************************************/
18 /**---------------------------------------------------------------------------*
20 **---------------------------------------------------------------------------*/
22 #include "asm/arch/sc_reg.h"
23 #include "asm/arch/adi_hal_internal.h"
24 #include "asm/arch/wdg_drvapi.h"
25 #include "asm/arch/sprd_reg.h"
26 #include "asm/arch/boot_drvapi.h"
27 #include "asm/arch/regs_adi.h"
28 /**---------------------------------------------------------------------------*
30 **---------------------------------------------------------------------------*/
36 /**---------------------------------------------------------------------------*
38 **---------------------------------------------------------------------------*/
39 #define REG_ANA_INTC_BASE 0x40038380
40 #define REG_ANA_INTC_INT_EN (REG_ANA_INTC_BASE + 0x8)
41 #define BIT_DCDCOTP_INT_EN (0x1 << 10)
43 /**---------------------------------------------------------------------------*
45 **---------------------------------------------------------------------------*/
46 struct dcdc_core_ds_step_info{
52 /**---------------------------------------------------------------------------*
54 **---------------------------------------------------------------------------*/
56 /**---------------------------------------------------------------------------*
57 ** Function Definitions *
58 **---------------------------------------------------------------------------*/
59 /*****************************************************************************/
60 // Description : This function is used to reset MCU.
61 // Global resource dependence :
62 // Author : Xueliang.Wang
64 /*****************************************************************************/
65 void CHIP_ResetMCU (void) //reset interrupt disable??
67 // This loop is very important to let the reset process work well on V3 board
79 volatile uint32 tick1 = SCI_GetTickCount();
80 volatile uint32 tick2 = SCI_GetTickCount();
82 while ( (tick2 - tick1) < 500)
84 tick2 = SCI_GetTickCount();
89 /*****************************************************************************/
90 // Description: Returns the HW_RST register address.
92 // Note : Because there is no register which can restore information
93 // when watchdog resets the system, so we choose IRAM.
94 /*****************************************************************************/
95 LOCAL uint32 CHIP_PHY_GetHwRstAddr (void)
97 // Returns a DWORD of IRAM shared with DCAM
98 return ANA_REG_GLB_WDG_RST_MONITOR;
101 /*****************************************************************************/
102 // Description: Returns the reset mode register address.
105 /*****************************************************************************/
106 LOCAL uint32 CHIP_PHY_GetRstModeAddr (void)
108 return ANA_REG_GLB_POR_RST_MONITOR;
111 /*****************************************************************************/
112 // Description: Gets the register in analog die to judge the reset mode.
114 // Note: !It is called before __main now, so it can not call the adi
115 // interface because it contains SCI_DisableIRQ inside, below
116 // writes the adi read interface individually. Because the la-
117 // ckless of SCI_DisableIRQ, so this function must be called
118 // before system interrupt is turnned on!
119 /*****************************************************************************/
120 LOCAL uint32 CHIP_PHY_GetANAReg (void)
122 return ANA_REG_GET(ANA_REG_GLB_POR_RST_MONITOR);
125 /*****************************************************************************/
126 // Description: This fuction returns the HW_RST value written before reset.
129 /*****************************************************************************/
130 LOCAL uint32 CHIP_PHY_GetHWFlag (void)
132 // Switch IRAM from DCAM to ARM
133 return ANA_REG_GET (CHIP_PHY_GetHwRstAddr ());
136 /*****************************************************************************/
137 // Description: PHY layer realization of BOOT_SetRstMode.
139 // Note: The valid bit filed is from bit15 to bit0
140 /*****************************************************************************/
141 PUBLIC void CHIP_PHY_SetRstMode (uint32 val)
143 ANA_REG_AND (CHIP_PHY_GetRstModeAddr (), ~0xFFFF);
144 ANA_REG_OR (CHIP_PHY_GetRstModeAddr (), (val&0xFFFF));
147 /*****************************************************************************/
148 // Description: This fuction returns the reset mode value.
151 /*****************************************************************************/
152 PUBLIC uint32 CHIP_PHY_GetRstMode (void)
154 return (ANA_REG_GET (CHIP_PHY_GetRstModeAddr ()) & 0xFFFF);
157 /*****************************************************************************/
158 // Description: PHY layer realization of BOOT_ResetHWFlag. It resets the HW
159 // reset register after system initialization.
161 // Note: The valid bit filed of analog register is from bit11 to bit0.
162 // | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
163 // |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
165 // The valid bit filed of HW_RST is from bit11 to bit0.
166 /*****************************************************************************/
167 PUBLIC void CHIP_PHY_ResetHWFlag (uint32 val)
169 // Reset the analog die register
170 ANA_REG_AND(ANA_REG_GLB_POR_RST_MONITOR, ~0xFFF);
171 ANA_REG_OR (ANA_REG_GLB_POR_RST_MONITOR, (val&0xFFF));
174 ANA_REG_AND(CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
175 ANA_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
178 /*****************************************************************************/
179 // Description: PHY layer realization of BOOT_SetWDGHWFlag. It Writes flag
180 // to the register which would not be reset by watchdog reset.
182 // Note: The valid bit filed is from bit15 to bit0
183 /*****************************************************************************/
184 PUBLIC void CHIP_PHY_SetWDGHWFlag (WDG_HW_FLAG_T type, uint32 val)
186 if(TYPE_RESET == type)
188 ANA_REG_AND(CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
189 ANA_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
198 /*****************************************************************************/
199 // Description: PHY layer realization of __BOOT_IRAM_EN.
201 // Note: Do nothing. There are 32KB internal ram dedicated for ARM.
202 /*****************************************************************************/
203 PUBLIC void CHIP_PHY_BootIramEn ()
207 /*****************************************************************************/
208 // Description : This function returns whether the watchdog reset is caused
209 // by software reset or system halted.
211 // Note : The valid bit filed is from bit15 to bit0
212 /*****************************************************************************/
213 PUBLIC BOOLEAN CHIP_PHY_IsWDGRstByMCU (uint32 flag)
215 // Copy the value of HW_RST register to the register specific to reset mode
216 ANA_REG_SET (CHIP_PHY_GetRstModeAddr (),
217 (CHIP_PHY_GetHWFlag () & 0xFFFF));
219 if ((CHIP_PHY_GetHWFlag () & 0xFFFF) == (flag & 0xFFFF))
229 /*****************************************************************************/
230 // Description : This function returns whether the reset is caused by power
233 // Note : | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
234 // |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
235 /*****************************************************************************/
236 PUBLIC BOOLEAN CHIP_PHY_IsResetByPowerUp()
238 if ((CHIP_PHY_GetANAReg () & 0xF0) == 0x0)
248 /*****************************************************************************/
249 // Description : This function returns whether the reset is caused by watch-
252 // Note : | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
253 // |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
254 /*****************************************************************************/
255 PUBLIC BOOLEAN CHIP_PHY_IsResetByWatchDog()
257 if ((CHIP_PHY_GetANAReg () & 0xF) == 0x0)
267 /************************************************************
268 *select TDPLL's reference crystal,
269 *(1)--RF0---------xtlbuf0-----------
270 * -?-tdpll_ref_sel-----TDPLL
271 *(2)--RF1---------xtlbuf1-----------
272 1)rf_id = 0,TDPLL will select (1), or select (2)
273 ************************************************************/
274 PUBLIC uint32 TDPllRefConfig(TDPLL_REF_T rf_id)
277 /* before switch reference crystal, it must be sure that no module is using TDPLL */
278 pll_reg = readl(REG_AP_CLK_AP_AHB_CFG);
279 pll_reg &= ~AP_AHB_CLK_SEL_MASK;
280 writel(pll_reg, REG_AP_CLK_AP_AHB_CFG);
282 pll_reg = readl(REG_AON_CLK_PUB_AHB_CFG);
283 pll_reg &= ~PUB_AHB_CLK_SEL_MASK;
284 writel(pll_reg, REG_AON_CLK_PUB_AHB_CFG);
286 pll_reg = readl(REG_AP_CLK_AP_APB_CFG);
287 pll_reg &= ~AP_APB_CLK_SEL_MASK;
288 writel(pll_reg, REG_AP_CLK_AP_APB_CFG);
290 pll_reg = readl(REG_AON_CLK_AON_APB_CFG);
291 pll_reg &= ~PUB_APB_CLK_SEL_MASK;
292 writel(pll_reg, REG_AON_CLK_AON_APB_CFG);
294 pll_reg = readl(REG_AON_APB_PLL_SOFT_CNT_DONE);
295 pll_reg &= ~(BIT_TDPLL_SOFT_CNT_DONE);
296 writel(pll_reg, REG_AON_APB_PLL_SOFT_CNT_DONE);
299 /* switch TDPLL reference crystal */
300 if (rf_id == TDPLL_REF0)
302 pll_reg = readl(REG_PMU_APB_TDPLL_REL_CFG);
303 pll_reg &= ~(0x1 << 4);
304 writel(pll_reg, REG_PMU_APB_TDPLL_REL_CFG);
306 pll_reg = readl(REG_PMU_APB_XTL0_REL_CFG);
307 pll_reg |= BIT_XTL1_AP_SEL;
308 writel(pll_reg, REG_PMU_APB_XTL0_REL_CFG);
310 pll_reg = readl(REG_PMU_APB_XTLBUF0_REL_CFG);
311 pll_reg |= BIT_XTLBUF1_AP_SEL;
312 writel(pll_reg, REG_PMU_APB_XTLBUF0_REL_CFG);
314 else if(rf_id == TDPLL_REF1)
316 pll_reg = readl(REG_PMU_APB_TDPLL_REL_CFG);
317 pll_reg |= (0x1 << 4);
318 writel(pll_reg, REG_PMU_APB_TDPLL_REL_CFG);
320 pll_reg = readl(REG_PMU_APB_XTL1_REL_CFG);
321 pll_reg |= BIT_XTL1_AP_SEL;
322 writel(pll_reg, REG_PMU_APB_XTL1_REL_CFG);
324 pll_reg = readl(REG_PMU_APB_XTLBUF1_REL_CFG);
325 pll_reg |= BIT_XTLBUF1_AP_SEL;
326 writel(pll_reg, REG_PMU_APB_XTLBUF1_REL_CFG);
331 pll_reg = readl(REG_AON_APB_PLL_SOFT_CNT_DONE);
332 pll_reg |= (BIT_TDPLL_SOFT_CNT_DONE);
333 writel(pll_reg, REG_AON_APB_PLL_SOFT_CNT_DONE);
337 /* after switch, up ahb clock to 128M, APB to 64M */
338 pll_reg = readl(REG_AP_CLK_AP_AHB_CFG);
340 writel(pll_reg, REG_AP_CLK_AP_AHB_CFG);
342 pll_reg = readl(REG_AON_CLK_PUB_AHB_CFG);
344 writel(pll_reg, REG_AON_CLK_PUB_AHB_CFG);
346 pll_reg = readl(REG_AP_CLK_AP_APB_CFG);
348 writel(pll_reg, REG_AP_CLK_AP_APB_CFG);
350 pll_reg = readl(REG_AON_CLK_AON_APB_CFG);
352 writel(pll_reg, REG_AON_CLK_AON_APB_CFG);
363 void pmu_cp_modem_config(SPRD_MODEM_E modem)
366 if((modem == MODEM_WCDMA)||(modem == MODEM_TD)) {
367 CHIP_REG_SET(REG_PMU_APB_PD_CP0_SYS_CFG,
368 BIT_CP0_FORCE_DEEP_SLEEP |
369 BIT_PD_CP0_SYS_FORCE_SHUTDOWN |
370 BITS_PD_CP0_SYS_PWR_ON_DLY(0x08) |
371 BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(0x00) |
372 BITS_PD_CP0_SYS_ISO_ON_DLY(0x06) |
375 CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_0_CFG,
376 //BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN |
377 BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN |
378 BITS_PD_CP0_ARM9_0_PWR_ON_DLY(0x08) |
379 BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(0x06) |
380 BITS_PD_CP0_ARM9_0_ISO_ON_DLY(0x02) |
383 CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_1_CFG,
384 BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN |
385 //BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN |
386 BITS_PD_CP0_ARM9_1_PWR_ON_DLY(0x08) |
387 BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(0x06) |
388 BITS_PD_CP0_ARM9_1_ISO_ON_DLY(0x02) |
391 CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_2_CFG,
392 BIT_PD_CP0_ARM9_2_FORCE_SHUTDOWN |
393 //BIT_PD_CP0_ARM9_2_AUTO_SHUTDOWN_EN |
394 BITS_PD_CP0_ARM9_2_PWR_ON_DLY(0x08) |
395 BITS_PD_CP0_ARM9_2_PWR_ON_SEQ_DLY(0x06) |
396 BITS_PD_CP0_ARM9_2_ISO_ON_DLY(0x02) |
399 CHIP_REG_SET(REG_PMU_APB_PD_CP0_GSM_CFG,
400 //BIT_PD_CP0_GSM_FORCE_SHUTDOWN |
401 //BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN |
402 BITS_PD_CP0_GSM_PWR_ON_DLY(0x08) |
403 BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(0x04) |
404 BITS_PD_CP0_GSM_ISO_ON_DLY(0x04) |
407 CHIP_REG_SET(REG_PMU_APB_PD_CP0_CEVA_CFG,
408 //BIT_PD_CP0_CEVA_FORCE_SHUTDOWN |
409 //BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN |
410 BITS_PD_CP0_CEVA_PWR_ON_DLY(0x08) |
411 BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(0x06) |
412 BITS_PD_CP0_CEVA_ISO_ON_DLY(0x02) |
415 CHIP_REG_SET(REG_PMU_APB_PD_CP0_HU3GE_CFG,
416 BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN |
417 //BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN |
418 BITS_PD_CP0_HU3GE_PWR_ON_DLY(0x08) |
419 BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(0x02) |
420 BITS_PD_CP0_HU3GE_ISO_ON_DLY(0x04) |
423 CHIP_REG_SET(REG_PMU_APB_PD_CP0_TD_CFG,
424 BIT_PD_CP0_TD_FORCE_SHUTDOWN |
425 //BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN |
426 BITS_PD_CP0_TD_PWR_ON_DLY(0x08) |
427 BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(0x02) |
428 BITS_PD_CP0_TD_ISO_ON_DLY(0x04) |
436 CHIP_REG_SET(REG_PMU_APB_PD_CP0_HU3GE_CFG,
437 //BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN |
438 //BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN |
439 BITS_PD_CP0_HU3GE_PWR_ON_DLY(0x08) |
440 BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(0x02) |
441 BITS_PD_CP0_HU3GE_ISO_ON_DLY(0x04) |
446 CHIP_REG_SET(REG_PMU_APB_PD_CP0_TD_CFG,
447 //BIT_PD_CP0_TD_FORCE_SHUTDOWN |
448 //BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN |
449 BITS_PD_CP0_TD_PWR_ON_DLY(0x08) |
450 BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(0x02) |
451 BITS_PD_CP0_TD_ISO_ON_DLY(0x04) |
456 CHIP_REG_SET(REG_PMU_APB_PD_CP2_SYS_CFG,
457 BIT_CP2_FORCE_DEEP_SLEEP |
458 BIT_PD_CP2_SYS_FORCE_SHUTDOWN |
459 BITS_PD_CP2_SYS_PWR_ON_DLY(0x08) |
460 BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(0x00) |
461 BITS_PD_CP2_SYS_ISO_ON_DLY(0x06) |
464 CHIP_REG_SET(REG_PMU_APB_PD_CP2_ARM9_CFG,
465 //BIT_PD_CP2_ARM9_FORCE_SHUTDOWN |
466 BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN |
467 BITS_PD_CP2_ARM9_PWR_ON_DLY(0x08) |
468 BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(0x02) |
469 BITS_PD_CP2_ARM9_ISO_ON_DLY(0x04) |
472 CHIP_REG_SET(REG_PMU_APB_PD_CP2_WIFI_CFG,
473 //BIT_PD_CP2_WIFI_FORCE_SHUTDOWN |
474 BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN |
475 BITS_PD_CP2_WIFI_PWR_ON_DLY(0x08) |
476 BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(0x02) |
477 BITS_PD_CP2_WIFI_ISO_ON_DLY(0x04) |
486 void pmu_common_config(void)
488 CHIP_REG_SET(REG_PMU_APB_PD_CP0_SYS_CFG,
489 //BIT_CP0_FORCE_DEEP_SLEEP |
490 //BIT_PD_CP0_SYS_FORCE_SHUTDOWN |
491 //BIT_PD_CP0_SYS_AUTO_SHUTDOWN_EN |
492 BITS_PD_CP0_SYS_PWR_ON_DLY(0x08) |
493 BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(0x00) |
494 BITS_PD_CP0_SYS_ISO_ON_DLY(0x06) |
497 CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_0_CFG,
498 //BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN |
499 //BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN |
500 BITS_PD_CP0_ARM9_0_PWR_ON_DLY(0x08) |
501 BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(0x06) |
502 BITS_PD_CP0_ARM9_0_ISO_ON_DLY(0x02) |
505 CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_1_CFG,
506 //BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN |
507 //BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN |
508 BITS_PD_CP0_ARM9_1_PWR_ON_DLY(0x08) |
509 BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(0x06) |
510 BITS_PD_CP0_ARM9_1_ISO_ON_DLY(0x02) |
513 CHIP_REG_SET(REG_PMU_APB_PD_CP0_GSM_CFG,
514 //BIT_PD_CP0_GSM_FORCE_SHUTDOWN |
515 //BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN |
516 BITS_PD_CP0_GSM_PWR_ON_DLY(0x08) |
517 BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(0x04) |
518 BITS_PD_CP0_GSM_ISO_ON_DLY(0x04) |
521 CHIP_REG_SET(REG_PMU_APB_PD_CP0_CEVA_CFG,
522 //BIT_PD_CP0_CEVA_FORCE_SHUTDOWN |
523 //BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN |
524 BITS_PD_CP0_CEVA_PWR_ON_DLY(0x08) |
525 BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(0x06) |
526 BITS_PD_CP0_CEVA_ISO_ON_DLY(0x02) |
529 CHIP_REG_SET(REG_PMU_APB_PD_CP0_HU3GE_CFG,
530 //BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN |
531 //BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN |
532 BITS_PD_CP0_HU3GE_PWR_ON_DLY(0x08) |
533 BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(0x02) |
534 BITS_PD_CP0_HU3GE_ISO_ON_DLY(0x04) |
537 CHIP_REG_SET(REG_PMU_APB_PD_CP0_HARQ_CFG,
538 //BIT_PD_CP0_HARQ_FORCE_SHUTDOWN |
539 //BIT_PD_CP0_HARQ_AUTO_SHUTDOWN_EN |
540 BITS_PD_CP0_HARQ_PWR_ON_DLY(0x08) |
541 BITS_PD_CP0_HARQ_PWR_ON_SEQ_DLY(0x02) |
542 BITS_PD_CP0_HARQ_ISO_ON_DLY(0x04) |
545 CHIP_REG_SET(REG_PMU_APB_PD_CP0_TD_CFG,
546 //BIT_PD_CP0_TD_FORCE_SHUTDOWN |
547 //BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN |
548 BITS_PD_CP0_TD_PWR_ON_DLY(0x08) |
549 BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(0x02) |
550 BITS_PD_CP0_TD_ISO_ON_DLY(0x04) |
553 CHIP_REG_SET(REG_PMU_APB_PD_CP2_SYS_CFG,
554 //BIT_CP2_FORCE_DEEP_SLEEP |
555 //BIT_PD_CP2_SYS_FORCE_SHUTDOWN |
556 //BIT_PD_CP2_SYS_AUTO_SHUTDOWN_EN |
557 BITS_PD_CP2_SYS_PWR_ON_DLY(0x08) |
558 BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(0x00) |
559 BITS_PD_CP2_SYS_ISO_ON_DLY(0x06) |
562 CHIP_REG_SET(REG_PMU_APB_PD_CP2_ARM9_CFG,
563 //BIT_PD_CP2_ARM9_FORCE_SHUTDOWN |
564 //BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN |
565 BITS_PD_CP2_ARM9_PWR_ON_DLY(0x08) |
566 BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(0x02) |
567 BITS_PD_CP2_ARM9_ISO_ON_DLY(0x04) |
570 CHIP_REG_SET(REG_PMU_APB_PD_CP2_WIFI_CFG,
571 //BIT_PD_CP2_WIFI_FORCE_SHUTDOWN |
572 //BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN |
573 BITS_PD_CP2_WIFI_PWR_ON_DLY(0x08) |
574 BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(0x02) |
575 BITS_PD_CP2_WIFI_ISO_ON_DLY(0x04) |
578 CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
579 //BIT_PD_CA7_TOP_FORCE_SHUTDOWN |
580 //BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
581 BITS_PD_CA7_TOP_PWR_ON_DLY(8) |
582 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) |
583 BITS_PD_CA7_TOP_ISO_ON_DLY(4) |
586 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
587 //BIT_PD_CA7_C0_FORCE_SHUTDOWN |
588 //BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
589 BITS_PD_CA7_C0_PWR_ON_DLY(8) |
590 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) |
591 BITS_PD_CA7_C0_ISO_ON_DLY(2) |
595 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
596 //BIT_PD_CA7_C1_FORCE_SHUTDOWN |
597 //BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN |
598 BITS_PD_CA7_C1_PWR_ON_DLY(8) |
599 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) |
600 BITS_PD_CA7_C1_ISO_ON_DLY(2) |
604 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
605 //BIT_PD_CA7_C2_FORCE_SHUTDOWN |
606 //BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN |
607 BITS_PD_CA7_C2_PWR_ON_DLY(8) |
608 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) |
609 BITS_PD_CA7_C2_ISO_ON_DLY(2) |
613 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
614 //BIT_PD_CA7_C3_FORCE_SHUTDOWN |
615 //BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN |
616 BITS_PD_CA7_C3_PWR_ON_DLY(8) |
617 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) |
618 BITS_PD_CA7_C3_ISO_ON_DLY(2) |
622 CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
623 //BIT_PD_AP_SYS_FORCE_SHUTDOWN |
624 //BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
625 BITS_PD_AP_SYS_PWR_ON_DLY(8) |
626 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) |
627 BITS_PD_AP_SYS_ISO_ON_DLY(6) |
631 CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
632 //BIT_PD_MM_TOP_FORCE_SHUTDOWN |
633 //BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN |
634 BITS_PD_MM_TOP_PWR_ON_DLY(8) |
635 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) |
636 BITS_PD_MM_TOP_ISO_ON_DLY(4) |
640 CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
641 //BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
642 //BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN |
643 BITS_PD_GPU_TOP_PWR_ON_DLY(8) |
644 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) |
645 BITS_PD_GPU_TOP_ISO_ON_DLY(4) |
649 CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
650 //BIT_PD_PUB_SYS_FORCE_SHUTDOWN |
651 //BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
652 BITS_PD_PUB_SYS_PWR_ON_DLY(8) |
653 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) |
654 BITS_PD_PUB_SYS_ISO_ON_DLY(6) |
658 CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
659 BITS_XTL1_WAIT_CNT(0x39) |
660 BITS_XTL0_WAIT_CNT(0x39) |
664 CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
665 BITS_XTLBUF1_WAIT_CNT(7) |
666 BITS_XTLBUF0_WAIT_CNT(7) |
670 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
671 BITS_WPLL_WAIT_CNT(7) |
672 BITS_TDPLL_WAIT_CNT(7) |
673 BITS_DPLL_WAIT_CNT(7) |
674 BITS_MPLL_WAIT_CNT(7) |
678 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
679 BITS_WIFIPLL2_WAIT_CNT(7) |
680 BITS_WIFIPLL1_WAIT_CNT(7) |
681 BITS_CPLL_WAIT_CNT(7) |
685 ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
686 BITS_SLP_IN_WAIT_DCDCARM(7) |
687 BITS_SLP_OUT_WAIT_DCDCARM(8) |
693 static void dcdc_optimize_config(unsigned int para)
695 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
696 unsigned short dcdc_ctrl[]={
704 0x0808,/*mem & core*/
710 for(i=0;i<sizeof(dcdc_ctrl)/sizeof(dcdc_ctrl[0]);i++)
712 sci_adi_write(ANA_REG_GLB_DCDC_CTRL0 + (i << 2),dcdc_ctrl[i],0xffff);
717 static void dcdc_core_ds_config(unsigned int para)
719 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
720 uint32 dcdc_core_ctl_adi = 0;
723 uint32 dcdc_core_ctl_ds = -1;
724 uint32 dcdc_core_cal_adi = 0;
725 uint32 reg_val_cal = 0;
726 uint32 dcdc_core_cal_ds = -1;
727 static uint32 step_cal = 3;
728 uint32 step_cal_flag = 0;
730 static char dcdc_core_down_volt[]={4,1,1,2,3,5,0,6};
732 /*1100,700,800,900,1000,650,1200,1300*/
733 static uint32 step_ratio[]={10,10,6,3,3};
735 /*sleep dcdc cal transformer for sc2723*/
736 dcdc_core_cal_adi = (ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI)) & 0x1F;
737 /*step_cal = 3, so 3*3mV=9mV ~ 0.01V*/
738 dcdc_core_cal_ds = dcdc_core_cal_adi+step_cal;
740 dcdc_core_cal_ds = dcdc_core_cal_adi;
741 if(dcdc_core_cal_ds >= 0x1F) {
742 /*if cal > 1,set step_cal_flag = 1,carry bit*/
743 dcdc_core_cal_ds = dcdc_core_cal_ds - 0x1F;
749 reg_val_cal = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL1);
751 reg_val_cal |= dcdc_core_cal_ds << 5;
753 ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL1, reg_val_cal);
755 /*sleep dcdc ctl transformer for sc2723*/
756 dcdc_core_ctl_adi = (ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI) >> 5) & 0x1F;
757 if(0x1 == step_cal_flag) {
758 /*if step_cal_flag = 1,the ctl will first down and after up, so it no change*/
759 dcdc_core_ctl_ds = dcdc_core_ctl_adi;
762 dcdc_core_ctl_ds = dcdc_core_down_volt[dcdc_core_ctl_adi];
764 dcdc_core_ctl_ds = dcdc_core_ctl_adi; /*no transformer*/
766 reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL1);
768 reg_val |= dcdc_core_ctl_ds;
770 ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL1, reg_val);
771 /*enable the DCDC_CORE_SLEEP_OUT_STEP for dcdc core step down */
772 reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL0);
774 ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL0, reg_val);
777 uint32 dcdc_core_ctl_adi = 0;
779 uint32 dcdc_core_ctl_ds = -1;
781 static struct dcdc_core_ds_step_info step_info[5]={
782 {ANA_REG_GLB_MP_PWR_CTRL1, 0,ANA_REG_GLB_MP_PWR_CTRL2, 0},
783 {ANA_REG_GLB_MP_PWR_CTRL1, 3,ANA_REG_GLB_MP_PWR_CTRL2, 5},
784 {ANA_REG_GLB_MP_PWR_CTRL1, 6,ANA_REG_GLB_MP_PWR_CTRL2,10},
785 {ANA_REG_GLB_MP_PWR_CTRL1, 9,ANA_REG_GLB_MP_PWR_CTRL3, 0},
786 {ANA_REG_GLB_MP_PWR_CTRL1,12,ANA_REG_GLB_MP_PWR_CTRL3, 5}
788 static char dcdc_core_down_volt[]={4,1,1,2,3,5,0,6};
789 static char dcdc_core_up_volt[]={6,2,3,4,0,1,7,7};
790 uint32 dcdc_core_cal_adi,i;
791 /*1100,700,800,900,1000,650,1200,1300*/
792 static uint32 step_ratio[]={10,10,6,3,3};
793 dcdc_core_ctl_adi = (sci_adi_read(ANA_REG_GLB_MP_MISC_CTRL) >> 3) & 0x7;
794 dcdc_core_ctl_ds = dcdc_core_down_volt[dcdc_core_ctl_adi];
795 dcdc_core_ctl_ds = dcdc_core_ctl_adi;
797 reg_val = sci_adi_read(ANA_REG_GLB_DCDC_SLP_CTRL);
799 reg_val |= dcdc_core_ctl_ds;
800 sci_adi_write(ANA_REG_GLB_DCDC_SLP_CTRL, reg_val, 0xffff);
802 dcdc_core_cal_adi = sci_adi_read(ANA_REG_GLB_DCDC_CORE_ADI) & 0x1F;
803 if(dcdc_core_ctl_ds < dcdc_core_ctl_adi){
804 /*last step must equel function mode */
805 sci_adi_write(step_info[4].ctl_reg,dcdc_core_ctl_adi<<step_info[4].ctl_sht,0x07 << step_info[4].ctl_sht);
806 sci_adi_write(step_info[4].cal_reg,dcdc_core_cal_adi<<step_info[4].cal_sht,0x1F << step_info[4].cal_sht);
809 reg_val = dcdc_core_cal_adi + step_ratio[i];
810 if(reg_val <= 0x1F) {
811 sci_adi_write(step_info[i].ctl_reg,dcdc_core_ctl_ds<<step_info[i].ctl_sht,0x07<<step_info[i].ctl_sht);
812 sci_adi_write(step_info[i].cal_reg,reg_val<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
813 dcdc_core_cal_adi = reg_val;
815 sci_adi_write(step_info[i].ctl_reg,dcdc_core_up_volt[dcdc_core_ctl_ds]<<step_info[i].ctl_sht,
816 0x07 << step_info[i].ctl_sht);
817 sci_adi_write(step_info[i].cal_reg,(reg_val-0x1F)<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
818 dcdc_core_ctl_ds = dcdc_core_up_volt[dcdc_core_ctl_ds];
819 dcdc_core_cal_adi = reg_val - 0x1F;
824 /*every step should equal function mode*/
825 sci_adi_write(step_info[i].ctl_reg,dcdc_core_ctl_adi<<step_info[i].ctl_sht,0x07 << step_info[i].ctl_sht);
826 sci_adi_write(step_info[i].cal_reg,dcdc_core_cal_adi<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
831 struct ddr_phy_lp_reg_ctrl{
832 volatile unsigned int magic_header;
833 volatile unsigned int is_auto_pd;
834 volatile unsigned int magic_ender;
835 volatile unsigned int reg[3];
837 struct ddr_phy_lp_reg_ctrl lp_cfg=
840 #if defined(CONFIG_SP8730SEA)
850 static unsigned int dmc_phy_is_auto_pd(unsigned int is_auto_pd)
855 *(volatile unsigned int*)lp_cfg.reg[i] &= ~(0x1 << 25);
856 if(is_auto_pd & (0x1 << i)){
857 *(volatile unsigned int*)(lp_cfg.reg[i]) |= (0x1 << 24);
859 *(volatile unsigned int*)(lp_cfg.reg[i]) &= ~(0x1 << 24);
865 static void setup_ap_cp_sync_sleep_code(unsigned int start_addr)
868 unsigned int *sa = (unsigned int*)start_addr;
870 dmc_phy_is_auto_pd(lp_cfg.is_auto_pd);
872 /*enable cp2 can access 0x50001800*/
873 *(volatile unsigned int*)0x402e3038 &= ~(0x7 << 7);
874 /*enable cp0 can access 0x50001800*/
875 *(volatile unsigned int*)0x402e3028 &= ~(0x7 << 7);
877 /*set for indcate phy is alive*/
878 *(volatile unsigned int*)0x30040000 |= (0x1 << 0);
879 *(volatile unsigned int*)0x30010184 |= (0x1 << 0);
880 /*close umctl and phy and publ auto retention*/
881 *(volatile unsigned int*)0x402b012c &= ~((0x3 << 27)|(0x1 << 25));
885 void CSP_Init(unsigned int gen_para)
887 unsigned int reg_val;
888 calibrate_register_callback((void*)dcdc_core_ds_config);
889 setup_ap_cp_sync_sleep_code(0x50001800);
890 /*open adi clock auto gate for power consume*/
891 reg_val = readl(ADI_GSSI_CTL0);
892 reg_val &= ~(0x1 << 30);
893 writel(reg_val,ADI_GSSI_CTL0);
894 /*disable int ana dcd otp interrupt*/
895 ANA_REG_AND(REG_ANA_INTC_INT_EN,~BIT_DCDCOTP_INT_EN);
899 pmu_cp_modem_config(MODEM_CON);
901 dcdc_optimize_config(0x00000000);
902 /*setup bb ldo voltage level*/
903 reg_val = sci_adi_read(ANA_REG_GLB_LDO_SHPT_PD2);
905 sci_adi_write(ANA_REG_GLB_LDO_SHPT_PD2, reg_val, 0xffff);
907 reg_val = readl(REG_AON_APB_BB_BG_CTRL);
908 reg_val &= ~BITS_BB_LDO_V(0xF);
909 reg_val |= BITS_BB_LDO_V(0x4);
910 writel(reg_val,REG_AON_APB_BB_BG_CTRL);
914 /**---------------------------------------------------------------------------*
916 **---------------------------------------------------------------------------*/