arch/arm/cpu/armv7/sc8830/chip_x15/low_power.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5 #include <asm/arch/low_power.h>
   6
   7 //#define LDO_SLP_DEBUG
   8 #ifdef LDO_SLP_DEBUG
   9 typedef struct slp_test {
  10         unsigned int                                            reg;
  11         unsigned int                                            val;
  12 }test_t;
  13 test_t b[60];
  14
  15 void test_store (test_t *buf)
  16 {
  17         unsigned int i = 0;
  18
  19         buf[i].reg = ANA_REG_GLB_PWR_WR_PROT_VALUE;
  20         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE);
  21
  22         buf[i].reg = ANA_REG_GLB_LDO_DCDC_PD;
  23         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_LDO_DCDC_PD);
  24
  25         buf[i].reg = ANA_REG_GLB_DCDC_SLP_CTRL0;
  26         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL0);
  27
  28         buf[i].reg = ANA_REG_GLB_PWR_SLP_CTRL0;
  29         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_SLP_CTRL0);
  30
  31         buf[i].reg = ANA_REG_GLB_PWR_SLP_CTRL1;
  32         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_SLP_CTRL1);
  33
  34         buf[i].reg = ANA_REG_GLB_PWR_SLP_CTRL2;
  35         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_SLP_CTRL2);
  36
  37         buf[i].reg = ANA_REG_GLB_PWR_SLP_CTRL3;
  38         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_SLP_CTRL3);
  39
  40         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN0;
  41         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_XTL_EN0);
  42
  43         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN1;
  44         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_XTL_EN1);
  45
  46         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN2;
  47         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_XTL_EN2);
  48
  49         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN3;
  50         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_XTL_EN3);
  51
  52         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN4;
  53         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_PWR_XTL_EN4);
  54
  55         buf[i].reg = REG_PMU_APB_XTL0_REL_CFG;
  56         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTL0_REL_CFG);
  57
  58         buf[i].reg = REG_PMU_APB_XTL1_REL_CFG;
  59         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTL1_REL_CFG);
  60
  61         buf[i].reg = REG_PMU_APB_XTL2_REL_CFG;
  62         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTL2_REL_CFG);
  63
  64         buf[i].reg = REG_PMU_APB_XTLBUF0_REL_CFG;
  65         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTLBUF0_REL_CFG);
  66
  67         buf[i].reg = REG_PMU_APB_XTLBUF1_REL_CFG;
  68         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTLBUF1_REL_CFG);
  69
  70         buf[i].reg = REG_PMU_APB_MPLL_REL_CFG;
  71         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_MPLL_REL_CFG);
  72
  73         buf[i].reg = REG_PMU_APB_DPLL_REL_CFG;
  74         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_DPLL_REL_CFG);
  75
  76         buf[i].reg = REG_PMU_APB_TDPLL_REL_CFG;
  77         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
  78
  79         buf[i].reg = REG_PMU_APB_WPLL_REL_CFG;
  80         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
  81 /*
  82         buf[i].reg = ANA_REG_GLB_PWR_XTL_EN3;
  83         buf[i++].val = CHIP_REG_GET(ANA_REG_GLB_PWR_XTL_EN3);
  84 */
  85         buf[i].reg = REG_PMU_APB_CPLL_REL_CFG;
  86         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_CPLL_REL_CFG);
  87
  88         buf[i].reg = REG_PMU_APB_WIFIPLL1_REL_CFG;
  89         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_WIFIPLL1_REL_CFG);
  90
  91         buf[i].reg = REG_PMU_APB_WIFIPLL2_REL_CFG;
  92         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_WIFIPLL2_REL_CFG);
  93
  94         buf[i].reg = REG_PMU_APB_CGM_AP_EN;
  95         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_CGM_AP_EN);
  96
  97         buf[i].reg = REG_PMU_APB_PD_CA7_TOP_CFG;
  98         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_CA7_TOP_CFG);
  99
 100         buf[i].reg = REG_PMU_APB_PD_CA7_C0_CFG;
 101         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_CA7_C0_CFG);
 102
 103         buf[i].reg = REG_PMU_APB_PD_CA7_C1_CFG;
 104         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_CA7_C1_CFG);
 105
 106         buf[i].reg = REG_PMU_APB_PD_CA7_C2_CFG;
 107         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_CA7_C2_CFG);
 108
 109         buf[i].reg = REG_PMU_APB_PD_CA7_C3_CFG;
 110         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_CA7_C3_CFG);
 111
 112         buf[i].reg = REG_PMU_APB_PD_AP_SYS_CFG;
 113         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_AP_SYS_CFG);
 114
 115         buf[i].reg = REG_PMU_APB_PD_MM_TOP_CFG;
 116         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_MM_TOP_CFG);
 117
 118         buf[i].reg = REG_PMU_APB_PD_GPU_TOP_CFG;
 119         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_GPU_TOP_CFG);
 120
 121         buf[i].reg = REG_PMU_APB_PD_PUB_SYS_CFG;
 122         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PD_PUB_SYS_CFG);
 123
 124         buf[i].reg = REG_PMU_APB_XTL_WAIT_CNT;
 125         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTL_WAIT_CNT);
 126
 127         buf[i].reg = REG_PMU_APB_XTLBUF_WAIT_CNT;
 128         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_XTLBUF_WAIT_CNT);
 129
 130         buf[i].reg = REG_PMU_APB_PLL_WAIT_CNT1;
 131         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PLL_WAIT_CNT1);
 132
 133         buf[i].reg = REG_PMU_APB_PLL_WAIT_CNT2;
 134         buf[i++].val = CHIP_REG_GET(REG_PMU_APB_PLL_WAIT_CNT2);
 135
 136         buf[i].reg = ANA_REG_GLB_SLP_WAIT_DCDCARM;
 137         buf[i++].val = ANA_REG_GET(ANA_REG_GLB_SLP_WAIT_DCDCARM);
 138
 139         buf[i].reg = i;
 140         buf[i].val = 0x55AA55AA;
 141 }
 142 #endif
 143
 144 static struct ldo_lowpower_cfg *gp_ldo_cfg = NULL;
 145 static struct pll_cfg *gp_pll_cfg = NULL;
 146 static struct shutdown_cfg *gp_shutdown_cfg = NULL;
 147
 148 /*********************************************************************
 149 **      Description :
 150 **              This function used to get customize information. if not get, don't running.
 151 **      Param :
 152 **              None
 153 **      Return :
 154 **              none
 155 **      Date                                    Author                          Operation
 156 **      2014/01/23                      ypxie                           optimization
 157 *********************************************************************/
 158 void customize_low_power_init_prepare(struct ldo_lowpower_cfg *ldo,
 159                                                                 struct pll_cfg *pll,
 160                                                                 struct shutdown_cfg *shutdown)
 161 {
 162         gp_ldo_cfg = ldo;
 163         gp_pll_cfg = pll;
 164         gp_shutdown_cfg = shutdown;
 165 }
 166
 167 static void lowpower_earlyinit(void)
 168 {
 169         unsigned int reg_val;
 170
 171         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
 172                                 BIT_DCDC_TOP_CLKF_EN|BIT_DCDC_TOP_OSC_EN);
 173
 174         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0, BIT_SLP_IO_EN);
 175         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1, BIT_SLP_LDO_PD_EN);
 176         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0, BIT_LDO_XTL_EN);
 177         CHIP_REG_SET(REG_PMU_APB_CGM_AP_EN,0x1FFF81);
 178
 179         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL0);
 180         reg_val &= ~BITS_DCDC_CORE_CTL_DS_SW(7);
 181         reg_val |= BITS_DCDC_CORE_CTL_DS_SW(4);
 182         ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL0,reg_val);
 183
 184         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,0x0908);
 185         /*plls wait, xtl0/1 wait, xtlbuf0/1 wait time*/
 186
 187         if (ANA_GET_CHIP_ID() != 0x2711a000) {
 188                 CHIP_REG_SET(REG_AON_CLK_FM_CFG,
 189                         //BIT_CLK_FM_PAD_SEL |
 190                         //BIT_CLK_FM_SEL |
 191                         0 );
 192
 193                 CHIP_REG_SET(REG_AON_APB_GPS_26M_REF_SEL,
 194                         //BIT_XTLBUF1_GPS_SEL |
 195                         BIT_XTLBUF0_GPS_SEL |
 196                         //BIT_GPS_26M_REF_SEL |
 197                         0 );
 198         }
 199 }
 200
 201 static void wr_prot_dis(void)
 202 {
 203         unsigned int reg_val = 0;
 204
 205         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
 206                                 BITS_PWR_WR_PROT_VALUE(0x6e7f));
 207
 208         do{
 209                 reg_val = (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE)
 210                                 & BIT_PWR_WR_PROT);
 211         }while(reg_val == 0);
 212 }
 213
 214 static void wr_prot_en(void)
 215 {
 216         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE, BITS_PWR_WR_PROT_VALUE(0));
 217 }
 218
 219 static unsigned long ffs(unsigned int x)
 220 {
 221         unsigned long i = 0;
 222         if(x == 0)
 223                 i = 32;
 224         else {
 225                 while((x & (1<<i)) == 0) {
 226                         i ++;
 227                 }
 228                 i++;
 229         }
 230         return i;
 231 }
 232
 233 static unsigned long __ffs(unsigned int x)
 234 {
 235         return ffs(x) -1;
 236 }
 237
 238 /* pll */
 239 static void pll_xtl_with_sys_config(struct pll_cfg *cfg, struct pll_reg_bit *pll_reg)
 240 {
 241         /*enable all xtl for simply config.  xtlbuf0 is for ap, xtlbuf1 is for tdpll, choose!*/
 242         unsigned int i = 0, j;
 243         unsigned int sel_mode = 0, sel_tmp = 0;
 244
 245         if ((!cfg) || (cfg[0].pll_id == RESERVED_NUM) || (pll_reg == NULL)) {
 246                 return;
 247         }
 248
 249         /*collecting the current system mode, like TD only ..etc.*/
 250         while (cfg[i].pll_id != RESERVED_NUM) {
 251                 j = 0;
 252                 while (pll_reg[j].pll_id != RESERVED_NUM) {
 253                         if (cfg[i].pll_id == pll_reg[j].pll_id) {
 254                                 break;
 255                         }
 256                         ++j;
 257                 }
 258
 259                 /* set xtl ref */
 260                 if (pll_reg[j].cgm_ap_reg != -1) {
 261                         if (cfg[i].cgm_ap_en != NO_USED) {
 262                                 if (cfg[i].cgm_ap_en == LP_EN) {
 263                                         CHIP_REG_OR(pll_reg[j].cgm_ap_reg, pll_reg[j].cgm_ap_reg_bitmsk);
 264                                 }
 265                                 else if (cfg[i].cgm_ap_en == LP_DIS){
 266                                         CHIP_REG_AND(pll_reg[j].cgm_ap_reg, ~(pll_reg[j].cgm_ap_reg_bitmsk));
 267                                 }
 268                         }
 269                 }
 270
 271                 sel_mode = 0;
 272                 /* set select by ap,cp0,cp1,cp2 */
 273                 if (pll_reg[j].pll_sys_reg != -1) {
 274                         if(cfg[i].sys != NO_USED) {
 275                                 if (cfg[i].sys & AP_SYS) {
 276                                         sel_mode |= BIT(0);
 277                                 }
 278                                 if (cfg[i].sys & CP0_SYS) {
 279                                         sel_mode |= BIT(1);
 280                                 }
 281                                 if (cfg[i].sys & CP1_SYS) {
 282                                         sel_mode |= BIT(2);
 283                                 }
 284                                 if (cfg[i].sys & CP2_SYS) {
 285                                         sel_mode |= BIT(3);
 286                                 }
 287
 288                                 if (cfg[i].sys & REF_SYS) {
 289                                         sel_mode |= BIT(4);
 290                                 }
 291
 292                                 sel_tmp = CHIP_REG_GET(pll_reg[j].pll_sys_reg);
 293                                 sel_tmp &= ~pll_reg[j].pll_sys_reg_bitmsk;
 294                                 sel_tmp |= (sel_mode << __ffs(pll_reg[j].pll_sys_reg_bitmsk)
 295                                                         & pll_reg[j].pll_sys_reg_bitmsk);
 296
 297                                 CHIP_REG_SET(pll_reg[j].pll_sys_reg, sel_tmp);
 298                         }
 299                 }
 300
 301                 if (pll_reg[j].pll_wait_reg != -1) {
 302                         if (cfg[i].wait != NO_USED) {
 303                                 sel_mode = cfg[i].wait << __ffs(pll_reg[j].pll_wait_reg_bitmsk);
 304                                 sel_mode &= pll_reg[j].pll_wait_reg_bitmsk;
 305
 306                                 sel_tmp = CHIP_REG_GET(pll_reg[j].pll_wait_reg);
 307                                 sel_tmp &= ~pll_reg[j].pll_wait_reg_bitmsk;
 308                                 sel_tmp |= sel_mode;
 309
 310                                 CHIP_REG_SET(pll_reg[j].pll_wait_reg, sel_tmp);
 311                         }
 312                 }
 313
 314                 ++i;
 315         }
 316 }
 317
 318 static void pd_shutdown_config(struct shutdown_cfg *cfg,
 319                                                 struct pd_reg_bit *pd_reg)
 320 {
 321         /*enable all xtl for simply config.  xtlbuf0 is for ap, xtlbuf1 is for tdpll, choose!*/
 322         unsigned int i = 0, j;
 323         unsigned int reg_value = 0;
 324
 325         if ((!cfg) || (cfg[0].pd_shutdown_id == RESERVED_NUM) || (pd_reg == NULL)) {
 326                 return;
 327         }
 328
 329         /*collecting the current system mode, like TD only ..etc.*/
 330         while (cfg[i].pd_shutdown_id != RESERVED_NUM) {
 331                 j = 0;
 332                 while (pd_reg[j].pd_shutdown_id != RESERVED_NUM) {
 333                         if (cfg[i].pd_shutdown_id == pd_reg[j].pd_shutdown_id) {
 334                                 break;
 335                         }
 336                         ++j;
 337                 }
 338
 339                 if (pd_reg[j].pd_shutdown_id == RESERVED_NUM) {
 340                         continue;
 341                 }
 342
 343                 if (pd_reg[j].pd_reg != -1) {
 344                         if(cfg[i].iso_on_delay != NO_USED) {
 345                                 reg_value = cfg[i].iso_on_delay << __ffs(pd_reg[j].iso_on_delay_bitmsk);
 346                                 CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].iso_on_delay_bitmsk);
 347                                 CHIP_REG_OR(pd_reg[j].pd_reg, reg_value);
 348                         }
 349
 350                         if(cfg[i].pwr_on_seq_delay != NO_USED) {//pwr_on_seq_delay
 351                                 reg_value = cfg[i].pwr_on_seq_delay
 352                                                         << __ffs(pd_reg[j].pwr_on_seq_delay_bitmsk);
 353                                 CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].pwr_on_seq_delay_bitmsk);
 354                                 CHIP_REG_OR(pd_reg[j].pd_reg, reg_value);
 355                         }
 356
 357                         if(cfg[i].pwr_on_delay != NO_USED) {//pwr_on_delay
 358                                 reg_value = cfg[i].pwr_on_delay << __ffs(pd_reg[j].pwr_on_delay_bitmsk);
 359                                 CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].pwr_on_delay_bitmsk);
 360                                 CHIP_REG_OR(pd_reg[j].pd_reg,reg_value);
 361                         }
 362
 363                         if(cfg[i].auto_shutdown != NO_USED) {
 364                                 if(cfg[i].auto_shutdown == LP_EN) {//auto_shutdown
 365                                         CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].auto_shutdown_bitmsk);
 366                                 }
 367                                 else if(cfg[i].auto_shutdown == LP_DIS) {
 368                                         CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].auto_shutdown_bitmsk);
 369                                 }
 370                         }
 371
 372                         if(cfg[i].force_shutdown != NO_USED) {
 373                                 if(cfg[i].force_shutdown == LP_EN) {//force_shutdown
 374                                         CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].force_shutdown_bitmsk);
 375                                 }
 376                                 else if(cfg[i].force_shutdown == LP_DIS) {
 377                                         CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].force_shutdown_bitmsk);
 378                                 }
 379                         }
 380
 381                         if(cfg[i].debug_shutdown != NO_USED) {
 382                                 if(cfg[i].debug_shutdown == LP_EN) {//debug_shutdown
 383                                         CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].debug_shutdown_bitmsk);
 384                                 }
 385                                 else if(cfg[i].debug_shutdown == LP_DIS) {
 386                                         CHIP_REG_AND(pd_reg[j].pd_reg, ~(pd_reg[j].debug_shutdown_bitmsk));
 387                                 }
 388                         }
 389                 }
 390                 ++i;
 391         }
 392 }
 393
 394 static void ddie_pll_lowpower_init(void)
 395 {
 396         /*default all:xtl0/1/2 to ap, default all:xtlbuf0/1 to ap +*/
 397         pll_xtl_with_sys_config(gp_pll_cfg, pll_reg_tb);
 398         pd_shutdown_config(gp_shutdown_cfg, shutdown_tb);
 399 }
 400
 401 /* ldo */
 402
 403 static  void ldo_set_sts(struct ldo_lowpower_cfg *cfg, struct ldo_reg_bit *reg)
 404 {
 405         if (reg->ldo_pd_reg != -1) {
 406                 if (cfg->ldo_pd == LP_DIS) {
 407                         ANA_REG_OR(reg->ldo_pd_reg, reg->ldo_pd_reg_bitmsk);
 408                 } else if (cfg->ldo_pd == LP_EN) {
 409                         ANA_REG_BIC(reg->ldo_pd_reg, reg->ldo_pd_reg_bitmsk);
 410                 }
 411         }
 412 }
 413
 414 static  void ldo_set_sts_sleep(struct ldo_lowpower_cfg *cfg, struct ldo_reg_bit *reg)
 415 {
 416         if (cfg->status_in_sleep == SLP_PD_MODE) {
 417                 if (reg->ldo_pd_reg != -1) {
 418                         ANA_REG_OR(reg->slp_pd_reg, reg->slp_pd_reg_bitmsk);
 419                 }
 420                 if (reg->slp_lp_reg != -1) {
 421                         ANA_REG_BIC(reg->slp_lp_reg, reg->slp_lp_reg_bitmsk);
 422                 }
 423         } else if (cfg->status_in_sleep == SLP_LP_MODE) {
 424                 if (reg->slp_pd_reg != -1) {
 425                         ANA_REG_BIC(reg->slp_pd_reg, reg->slp_pd_reg_bitmsk);
 426                 }
 427                 if (reg->slp_lp_reg != -1) {
 428                         ANA_REG_OR(reg->slp_lp_reg, reg->slp_lp_reg_bitmsk);
 429                 }
 430         } else if (cfg->status_in_sleep == SLP_NO_MODE) {
 431                 if (reg->slp_pd_reg != -1) {
 432                         ANA_REG_BIC(reg->slp_pd_reg, reg->slp_pd_reg_bitmsk);
 433                 }
 434                 if (reg->slp_lp_reg != -1) {
 435                         ANA_REG_BIC(reg->slp_lp_reg, reg->slp_lp_reg_bitmsk);
 436                 }
 437         }
 438 }
 439
 440 /* ldo_id, cfg_to_xtl, cfg_to_ext_xtl,power_sts_in_sleep; */
 441 static void ldo_set_xtl(struct ldo_lowpower_cfg *cfg, struct ldo_reg_bit *reg)
 442 {
 443         unsigned int v = 0, tmp = 0;
 444         unsigned int shft = 0;
 445
 446         if (reg->xtl_reg != -1) {
 447                 shft = __ffs(reg->xtl_reg_bitmsk);
 448
 449                 if (cfg->select_by_xtl & BY_XTL0)
 450                         v |= BIT(0);
 451                 /* no xtl1 in 7715 */
 452                 /*if (cfg->select_by_xtl & BY_XTL1)
 453                         v |= BIT(1);*/
 454                 if (cfg->select_by_xtl & BY_XTL2)
 455                         v |= BIT(1);
 456                 v = v << shft;
 457                 v &= reg->xtl_reg_bitmsk;
 458
 459                 tmp = ANA_REG_GET(reg->xtl_reg);
 460                 tmp &= ~reg->xtl_reg_bitmsk;
 461                 tmp |= v;
 462
 463                 ANA_REG_SET(reg->xtl_reg, tmp);
 464         }
 465 }
 466
 467 static  void ldo_set_exxtl(struct ldo_lowpower_cfg *cfg, struct ldo_reg_bit *reg)
 468 {
 469         unsigned int v = 0, tmp = 0;
 470         unsigned int shft = 0;
 471
 472         if (reg->ext_xtl_reg != -1) {
 473                 shft = __ffs(reg->ext_xtl_reg_bitmsk);
 474
 475                 if (cfg->select_by_ext_xtl & BY_EXT_XTL0)
 476                         v |= BIT(0);
 477                 if (cfg->select_by_ext_xtl & BY_EXT_XTL1)
 478                         v |= BIT(1);
 479                 /* no xtl1 in 7715 */
 480                 /*if (cfg->select_by_ext_xtl & BY_EXT_XTL2)
 481                         v |= BIT(2);*/
 482
 483                 v = v << shft;
 484                 v &= reg->ext_xtl_reg_bitmsk;
 485
 486                 tmp = ANA_REG_GET(reg->ext_xtl_reg);
 487                 tmp &= ~reg->ext_xtl_reg_bitmsk;
 488                 tmp |= v;
 489
 490                 ANA_REG_SET(reg->ext_xtl_reg, tmp);
 491         }
 492 }
 493
 494 static void adie_ldo_lowpower_init()
 495 {
 496         struct ldo_lowpower_cfg *ldo_cfg = gp_ldo_cfg;
 497         struct ldo_reg_bit *ldo_reg = ldo_reg_tb;
 498         unsigned int i = 0, j = 0;
 499
 500         if ((!ldo_cfg) || (ldo_reg == NULL))
 501                 return;
 502
 503         while (ldo_cfg[i].ldo_id != RESERVED_NUM) {
 504                 j = 0;
 505                 while (ldo_reg[j].ldo_id != RESERVED_NUM) {
 506                         if (ldo_cfg[i].ldo_id == ldo_reg[j].ldo_id) {
 507                                 break;
 508                         }
 509                         ++j;
 510                 }
 511
 512                 if (ldo_reg[j].ldo_id == RESERVED_NUM) {
 513                         continue;
 514                 }
 515
 516                 if (ldo_cfg[i].ldo_pd != NO_USED) {
 517                         ldo_set_sts(&ldo_cfg[i], &ldo_reg[j]);
 518                 }
 519                 if (ldo_cfg[i].status_in_sleep != NO_USED) {
 520                         ldo_set_sts_sleep(&ldo_cfg[i], &ldo_reg[j]);
 521                 }
 522                 if (ldo_cfg[i].select_by_xtl!= NO_USED) {
 523                         ldo_set_xtl(&ldo_cfg[i], &ldo_reg[j]);
 524                 }
 525                 if (ldo_cfg[i].select_by_ext_xtl != NO_USED) {
 526                         ldo_set_exxtl(&ldo_cfg[i], &ldo_reg[j]);
 527                 }
 528                 ++i;
 529         }
 530 }
 531
 532 /*********************************************************************
 533 **      Description :
 534 **              This function used to init low power. Before running this function, must be running
 535 **              customize_low_power_init_prepare().
 536 **      Param :
 537 **              None
 538 **      Return :
 539 **              none
 540 **      Date                                    Author                          Operation
 541 **      2014/01/23                      ypxie                           optimization
 542 *********************************************************************/
 543 void low_power_init(void)
 544 {
 545         /*
 546         Every ldo LP/PD depend on AP, we can make ap select xtl_buf_en0, xtl_buf_en1,
 547         xtl_buf_en2 and cp0 select xtl_buf_en0, cp1 select xtl-buf_en1, cp2 select xtl_buf_en2, so
 548         ldo_x can flexiblly config to xtl0/cp0, xtl1/cp1, xtl2/cp2. But now, we can make this process
 549         to simple. make xtl_buf_en0 == xtl_buf_en1 == xtl_buf_en2
 550         if cp(X) is exist, slecet all xtl_Buf_en0/1/2.
 551         */
 552         wr_prot_dis();
 553         lowpower_earlyinit();
 554         ddie_pll_lowpower_init();
 555         adie_ldo_lowpower_init();
 556         wr_prot_en();
 557
 558         /* used test register */
 559         //test_store(&b);
 560 }